hw/intc/puv3_intc.c

   1 /*
   2  * INTC device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/irq.h"
  14 #include "hw/sysbus.h"
  15 #include "qom/object.h"
  16
  17 #undef DEBUG_PUV3
  18 #include "hw/unicore32/puv3.h"
  19 #include "qemu/module.h"
  20 #include "qemu/log.h"
  21
  22 #define TYPE_PUV3_INTC "puv3_intc"
  23 typedef struct PUV3INTCState PUV3INTCState;
  24 DECLARE_INSTANCE_CHECKER(PUV3INTCState, PUV3_INTC,
  25                          TYPE_PUV3_INTC)
  26
  27 struct PUV3INTCState {
  28     SysBusDevice parent_obj;
  29
  30     MemoryRegion iomem;
  31     qemu_irq parent_irq;
  32
  33     uint32_t reg_ICMR;
  34     uint32_t reg_ICPR;
  35 };
  36
  37 /* Update interrupt status after enabled or pending bits have been changed.  */
  38 static void puv3_intc_update(PUV3INTCState *s)
  39 {
  40     if (s->reg_ICMR & s->reg_ICPR) {
  41         qemu_irq_raise(s->parent_irq);
  42     } else {
  43         qemu_irq_lower(s->parent_irq);
  44     }
  45 }
  46
  47 /* Process a change in an external INTC input. */
  48 static void puv3_intc_handler(void *opaque, int irq, int level)
  49 {
  50     PUV3INTCState *s = opaque;
  51
  52     DPRINTF("irq 0x%x, level 0x%x\n", irq, level);
  53     if (level) {
  54         s->reg_ICPR |= (1 << irq);
  55     } else {
  56         s->reg_ICPR &= ~(1 << irq);
  57     }
  58     puv3_intc_update(s);
  59 }
  60
  61 static uint64_t puv3_intc_read(void *opaque, hwaddr offset,
  62         unsigned size)
  63 {
  64     PUV3INTCState *s = opaque;
  65     uint32_t ret = 0;
  66
  67     switch (offset) {
  68     case 0x04: /* INTC_ICMR */
  69         ret = s->reg_ICMR;
  70         break;
  71     case 0x0c: /* INTC_ICIP */
  72         ret = s->reg_ICPR; /* the same value with ICPR */
  73         break;
  74     default:
  75         qemu_log_mask(LOG_GUEST_ERROR,
  76                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
  77                       __func__, offset);
  78     }
  79     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  80     return ret;
  81 }
  82
  83 static void puv3_intc_write(void *opaque, hwaddr offset,
  84         uint64_t value, unsigned size)
  85 {
  86     PUV3INTCState *s = opaque;
  87
  88     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  89     switch (offset) {
  90     case 0x00: /* INTC_ICLR */
  91     case 0x14: /* INTC_ICCR */
  92         break;
  93     case 0x04: /* INTC_ICMR */
  94         s->reg_ICMR = value;
  95         break;
  96     default:
  97         qemu_log_mask(LOG_GUEST_ERROR,
  98                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
  99                       __func__, offset);
 100         return;
 101     }
 102     puv3_intc_update(s);
 103 }
 104
 105 static const MemoryRegionOps puv3_intc_ops = {
 106     .read = puv3_intc_read,
 107     .write = puv3_intc_write,
 108     .impl = {
 109         .min_access_size = 4,
 110         .max_access_size = 4,
 111     },
 112     .endianness = DEVICE_NATIVE_ENDIAN,
 113 };
 114
 115 static void puv3_intc_realize(DeviceState *dev, Error **errp)
 116 {
 117     PUV3INTCState *s = PUV3_INTC(dev);
 118     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 119
 120     qdev_init_gpio_in(dev, puv3_intc_handler, PUV3_IRQS_NR);
 121     sysbus_init_irq(sbd, &s->parent_irq);
 122
 123     s->reg_ICMR = 0;
 124     s->reg_ICPR = 0;
 125
 126     memory_region_init_io(&s->iomem, OBJECT(s), &puv3_intc_ops, s, "puv3_intc",
 127                           PUV3_REGS_OFFSET);
 128     sysbus_init_mmio(sbd, &s->iomem);
 129 }
 130
 131 static void puv3_intc_class_init(ObjectClass *klass, void *data)
 132 {
 133     DeviceClass *dc = DEVICE_CLASS(klass);
 134     dc->realize = puv3_intc_realize;
 135 }
 136
 137 static const TypeInfo puv3_intc_info = {
 138     .name = TYPE_PUV3_INTC,
 139     .parent = TYPE_SYS_BUS_DEVICE,
 140     .instance_size = sizeof(PUV3INTCState),
 141     .class_init = puv3_intc_class_init,
 142 };
 143
 144 static void puv3_intc_register_type(void)
 145 {
 146     type_register_static(&puv3_intc_info);
 147 }
 148
 149 type_init(puv3_intc_register_type)