hw/intc/xlnx-zynqmp-ipi.c

   1 /*
   2  * QEMU model of the IPI Inter Processor Interrupt block
   3  *
   4  * Copyright (c) 2014 Xilinx Inc.
   5  *
   6  * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
   7  * Written by Alistair Francis <alistair.francis@xilinx.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "hw/sysbus.h"
  30 #include "hw/register.h"
  31 #include "qemu/bitops.h"
  32 #include "qemu/log.h"
  33 #include "qemu/module.h"
  34 #include "hw/intc/xlnx-zynqmp-ipi.h"
  35 #include "hw/irq.h"
  36
  37 #ifndef XLNX_ZYNQMP_IPI_ERR_DEBUG
  38 #define XLNX_ZYNQMP_IPI_ERR_DEBUG 0
  39 #endif
  40
  41 #define DB_PRINT_L(lvl, fmt, args...) do {\
  42     if (XLNX_ZYNQMP_IPI_ERR_DEBUG >= lvl) {\
  43         qemu_log(TYPE_XLNX_ZYNQMP_IPI ": %s:" fmt, __func__, ## args);\
  44     } \
  45 } while (0)
  46
  47 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
  48
  49 REG32(IPI_TRIG, 0x0)
  50     FIELD(IPI_TRIG, PL_3, 27, 1)
  51     FIELD(IPI_TRIG, PL_2, 26, 1)
  52     FIELD(IPI_TRIG, PL_1, 25, 1)
  53     FIELD(IPI_TRIG, PL_0, 24, 1)
  54     FIELD(IPI_TRIG, PMU_3, 19, 1)
  55     FIELD(IPI_TRIG, PMU_2, 18, 1)
  56     FIELD(IPI_TRIG, PMU_1, 17, 1)
  57     FIELD(IPI_TRIG, PMU_0, 16, 1)
  58     FIELD(IPI_TRIG, RPU_1, 9, 1)
  59     FIELD(IPI_TRIG, RPU_0, 8, 1)
  60     FIELD(IPI_TRIG, APU, 0, 1)
  61 REG32(IPI_OBS, 0x4)
  62     FIELD(IPI_OBS, PL_3, 27, 1)
  63     FIELD(IPI_OBS, PL_2, 26, 1)
  64     FIELD(IPI_OBS, PL_1, 25, 1)
  65     FIELD(IPI_OBS, PL_0, 24, 1)
  66     FIELD(IPI_OBS, PMU_3, 19, 1)
  67     FIELD(IPI_OBS, PMU_2, 18, 1)
  68     FIELD(IPI_OBS, PMU_1, 17, 1)
  69     FIELD(IPI_OBS, PMU_0, 16, 1)
  70     FIELD(IPI_OBS, RPU_1, 9, 1)
  71     FIELD(IPI_OBS, RPU_0, 8, 1)
  72     FIELD(IPI_OBS, APU, 0, 1)
  73 REG32(IPI_ISR, 0x10)
  74     FIELD(IPI_ISR, PL_3, 27, 1)
  75     FIELD(IPI_ISR, PL_2, 26, 1)
  76     FIELD(IPI_ISR, PL_1, 25, 1)
  77     FIELD(IPI_ISR, PL_0, 24, 1)
  78     FIELD(IPI_ISR, PMU_3, 19, 1)
  79     FIELD(IPI_ISR, PMU_2, 18, 1)
  80     FIELD(IPI_ISR, PMU_1, 17, 1)
  81     FIELD(IPI_ISR, PMU_0, 16, 1)
  82     FIELD(IPI_ISR, RPU_1, 9, 1)
  83     FIELD(IPI_ISR, RPU_0, 8, 1)
  84     FIELD(IPI_ISR, APU, 0, 1)
  85 REG32(IPI_IMR, 0x14)
  86     FIELD(IPI_IMR, PL_3, 27, 1)
  87     FIELD(IPI_IMR, PL_2, 26, 1)
  88     FIELD(IPI_IMR, PL_1, 25, 1)
  89     FIELD(IPI_IMR, PL_0, 24, 1)
  90     FIELD(IPI_IMR, PMU_3, 19, 1)
  91     FIELD(IPI_IMR, PMU_2, 18, 1)
  92     FIELD(IPI_IMR, PMU_1, 17, 1)
  93     FIELD(IPI_IMR, PMU_0, 16, 1)
  94     FIELD(IPI_IMR, RPU_1, 9, 1)
  95     FIELD(IPI_IMR, RPU_0, 8, 1)
  96     FIELD(IPI_IMR, APU, 0, 1)
  97 REG32(IPI_IER, 0x18)
  98     FIELD(IPI_IER, PL_3, 27, 1)
  99     FIELD(IPI_IER, PL_2, 26, 1)
 100     FIELD(IPI_IER, PL_1, 25, 1)
 101     FIELD(IPI_IER, PL_0, 24, 1)
 102     FIELD(IPI_IER, PMU_3, 19, 1)
 103     FIELD(IPI_IER, PMU_2, 18, 1)
 104     FIELD(IPI_IER, PMU_1, 17, 1)
 105     FIELD(IPI_IER, PMU_0, 16, 1)
 106     FIELD(IPI_IER, RPU_1, 9, 1)
 107     FIELD(IPI_IER, RPU_0, 8, 1)
 108     FIELD(IPI_IER, APU, 0, 1)
 109 REG32(IPI_IDR, 0x1c)
 110     FIELD(IPI_IDR, PL_3, 27, 1)
 111     FIELD(IPI_IDR, PL_2, 26, 1)
 112     FIELD(IPI_IDR, PL_1, 25, 1)
 113     FIELD(IPI_IDR, PL_0, 24, 1)
 114     FIELD(IPI_IDR, PMU_3, 19, 1)
 115     FIELD(IPI_IDR, PMU_2, 18, 1)
 116     FIELD(IPI_IDR, PMU_1, 17, 1)
 117     FIELD(IPI_IDR, PMU_0, 16, 1)
 118     FIELD(IPI_IDR, RPU_1, 9, 1)
 119     FIELD(IPI_IDR, RPU_0, 8, 1)
 120     FIELD(IPI_IDR, APU, 0, 1)
 121
 122 /* APU
 123  * RPU_0
 124  * RPU_1
 125  * PMU_0
 126  * PMU_1
 127  * PMU_2
 128  * PMU_3
 129  * PL_0
 130  * PL_1
 131  * PL_2
 132  * PL_3
 133  */
 134 int index_array[NUM_IPIS] = {0, 8, 9, 16, 17, 18, 19, 24, 25, 26, 27};
 135 static const char *index_array_names[NUM_IPIS] = {"APU", "RPU_0", "RPU_1",
 136                                                   "PMU_0", "PMU_1", "PMU_2",
 137                                                   "PMU_3", "PL_0", "PL_1",
 138                                                   "PL_2", "PL_3"};
 139
 140 static void xlnx_zynqmp_ipi_set_trig(XlnxZynqMPIPI *s, uint32_t val)
 141 {
 142     int i, ipi_index, ipi_mask;
 143
 144     for (i = 0; i < NUM_IPIS; i++) {
 145         ipi_index = index_array[i];
 146         ipi_mask = (1 << ipi_index);
 147         DB_PRINT("Setting %s=%d\n", index_array_names[i],
 148                  !!(val & ipi_mask));
 149         qemu_set_irq(s->irq_trig_out[i], !!(val & ipi_mask));
 150     }
 151 }
 152
 153 static void xlnx_zynqmp_ipi_set_obs(XlnxZynqMPIPI *s, uint32_t val)
 154 {
 155     int i, ipi_index, ipi_mask;
 156
 157     for (i = 0; i < NUM_IPIS; i++) {
 158         ipi_index = index_array[i];
 159         ipi_mask = (1 << ipi_index);
 160         DB_PRINT("Setting %s=%d\n", index_array_names[i],
 161                  !!(val & ipi_mask));
 162         qemu_set_irq(s->irq_obs_out[i], !!(val & ipi_mask));
 163     }
 164 }
 165
 166 static void xlnx_zynqmp_ipi_update_irq(XlnxZynqMPIPI *s)
 167 {
 168     bool pending = s->regs[R_IPI_ISR] & ~s->regs[R_IPI_IMR];
 169
 170     DB_PRINT("irq=%d isr=%x mask=%x\n",
 171              pending, s->regs[R_IPI_ISR], s->regs[R_IPI_IMR]);
 172     qemu_set_irq(s->irq, pending);
 173 }
 174
 175 static uint64_t xlnx_zynqmp_ipi_trig_prew(RegisterInfo *reg, uint64_t val64)
 176 {
 177     XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
 178
 179     xlnx_zynqmp_ipi_set_trig(s, val64);
 180
 181     return val64;
 182 }
 183
 184 static void xlnx_zynqmp_ipi_trig_postw(RegisterInfo *reg, uint64_t val64)
 185 {
 186     XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
 187
 188     /* TRIG generates a pulse on the outbound signals. We use the
 189      * post-write callback to bring the signal back-down.
 190      */
 191     s->regs[R_IPI_TRIG] = 0;
 192
 193     xlnx_zynqmp_ipi_set_trig(s, 0);
 194 }
 195
 196 static uint64_t xlnx_zynqmp_ipi_isr_prew(RegisterInfo *reg, uint64_t val64)
 197 {
 198     XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
 199
 200     xlnx_zynqmp_ipi_set_obs(s, val64);
 201
 202     return val64;
 203 }
 204
 205 static void xlnx_zynqmp_ipi_isr_postw(RegisterInfo *reg, uint64_t val64)
 206 {
 207     XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
 208
 209     xlnx_zynqmp_ipi_update_irq(s);
 210 }
 211
 212 static uint64_t xlnx_zynqmp_ipi_ier_prew(RegisterInfo *reg, uint64_t val64)
 213 {
 214     XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
 215     uint32_t val = val64;
 216
 217     s->regs[R_IPI_IMR] &= ~val;
 218     xlnx_zynqmp_ipi_update_irq(s);
 219     return 0;
 220 }
 221
 222 static uint64_t xlnx_zynqmp_ipi_idr_prew(RegisterInfo *reg, uint64_t val64)
 223 {
 224     XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
 225     uint32_t val = val64;
 226
 227     s->regs[R_IPI_IMR] |= val;
 228     xlnx_zynqmp_ipi_update_irq(s);
 229     return 0;
 230 }
 231
 232 static const RegisterAccessInfo xlnx_zynqmp_ipi_regs_info[] = {
 233     {   .name = "IPI_TRIG",  .addr = A_IPI_TRIG,
 234         .rsvd = 0xf0f0fcfe,
 235         .ro = 0xf0f0fcfe,
 236         .pre_write = xlnx_zynqmp_ipi_trig_prew,
 237         .post_write = xlnx_zynqmp_ipi_trig_postw,
 238     },{ .name = "IPI_OBS",  .addr = A_IPI_OBS,
 239         .rsvd = 0xf0f0fcfe,
 240         .ro = 0xffffffff,
 241     },{ .name = "IPI_ISR",  .addr = A_IPI_ISR,
 242         .rsvd = 0xf0f0fcfe,
 243         .ro = 0xf0f0fcfe,
 244         .w1c = 0xf0f0301,
 245         .pre_write = xlnx_zynqmp_ipi_isr_prew,
 246         .post_write = xlnx_zynqmp_ipi_isr_postw,
 247     },{ .name = "IPI_IMR",  .addr = A_IPI_IMR,
 248         .reset = 0xf0f0301,
 249         .rsvd = 0xf0f0fcfe,
 250         .ro = 0xffffffff,
 251     },{ .name = "IPI_IER",  .addr = A_IPI_IER,
 252         .rsvd = 0xf0f0fcfe,
 253         .ro = 0xf0f0fcfe,
 254         .pre_write = xlnx_zynqmp_ipi_ier_prew,
 255     },{ .name = "IPI_IDR",  .addr = A_IPI_IDR,
 256         .rsvd = 0xf0f0fcfe,
 257         .ro = 0xf0f0fcfe,
 258         .pre_write = xlnx_zynqmp_ipi_idr_prew,
 259     }
 260 };
 261
 262 static void xlnx_zynqmp_ipi_reset(DeviceState *dev)
 263 {
 264     XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(dev);
 265     int i;
 266
 267     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
 268         register_reset(&s->regs_info[i]);
 269     }
 270
 271     xlnx_zynqmp_ipi_update_irq(s);
 272 }
 273
 274 static void xlnx_zynqmp_ipi_handler(void *opaque, int n, int level)
 275 {
 276     XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(opaque);
 277     uint32_t val = (!!level) << n;
 278
 279     DB_PRINT("IPI input irq[%d]=%d\n", n, level);
 280
 281     s->regs[R_IPI_ISR] |= val;
 282     xlnx_zynqmp_ipi_set_obs(s, s->regs[R_IPI_ISR]);
 283     xlnx_zynqmp_ipi_update_irq(s);
 284 }
 285
 286 static void xlnx_zynqmp_obs_handler(void *opaque, int n, int level)
 287 {
 288     XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(opaque);
 289
 290     DB_PRINT("OBS input irq[%d]=%d\n", n, level);
 291
 292     s->regs[R_IPI_OBS] &= ~(1ULL << n);
 293     s->regs[R_IPI_OBS] |= (level << n);
 294 }
 295
 296 static const MemoryRegionOps xlnx_zynqmp_ipi_ops = {
 297     .read = register_read_memory,
 298     .write = register_write_memory,
 299     .endianness = DEVICE_LITTLE_ENDIAN,
 300     .valid = {
 301         .min_access_size = 4,
 302         .max_access_size = 4,
 303     },
 304 };
 305
 306 static void xlnx_zynqmp_ipi_realize(DeviceState *dev, Error **errp)
 307 {
 308     qdev_init_gpio_in_named(dev, xlnx_zynqmp_ipi_handler, "IPI_INPUTS", 32);
 309     qdev_init_gpio_in_named(dev, xlnx_zynqmp_obs_handler, "OBS_INPUTS", 32);
 310 }
 311
 312 static void xlnx_zynqmp_ipi_init(Object *obj)
 313 {
 314     XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(obj);
 315     DeviceState *dev = DEVICE(obj);
 316     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 317     RegisterInfoArray *reg_array;
 318     char *irq_name;
 319     int i;
 320
 321     memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_IPI,
 322                        R_XLNX_ZYNQMP_IPI_MAX * 4);
 323     reg_array =
 324         register_init_block32(DEVICE(obj), xlnx_zynqmp_ipi_regs_info,
 325                               ARRAY_SIZE(xlnx_zynqmp_ipi_regs_info),
 326                               s->regs_info, s->regs,
 327                               &xlnx_zynqmp_ipi_ops,
 328                               XLNX_ZYNQMP_IPI_ERR_DEBUG,
 329                               R_XLNX_ZYNQMP_IPI_MAX * 4);
 330     memory_region_add_subregion(&s->iomem,
 331                                 0x0,
 332                                 &reg_array->mem);
 333     sysbus_init_mmio(sbd, &s->iomem);
 334     sysbus_init_irq(sbd, &s->irq);
 335
 336     for (i = 0; i < NUM_IPIS; i++) {
 337         qdev_init_gpio_out_named(dev, &s->irq_trig_out[i],
 338                                  index_array_names[i], 1);
 339
 340         irq_name = g_strdup_printf("OBS_%s", index_array_names[i]);
 341         qdev_init_gpio_out_named(dev, &s->irq_obs_out[i],
 342                                  irq_name, 1);
 343         g_free(irq_name);
 344     }
 345 }
 346
 347 static const VMStateDescription vmstate_zynqmp_pmu_ipi = {
 348     .name = TYPE_XLNX_ZYNQMP_IPI,
 349     .version_id = 1,
 350     .minimum_version_id = 1,
 351     .fields = (VMStateField[]) {
 352         VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPIPI, R_XLNX_ZYNQMP_IPI_MAX),
 353         VMSTATE_END_OF_LIST(),
 354     }
 355 };
 356
 357 static void xlnx_zynqmp_ipi_class_init(ObjectClass *klass, void *data)
 358 {
 359     DeviceClass *dc = DEVICE_CLASS(klass);
 360
 361     dc->reset = xlnx_zynqmp_ipi_reset;
 362     dc->realize = xlnx_zynqmp_ipi_realize;
 363     dc->vmsd = &vmstate_zynqmp_pmu_ipi;
 364 }
 365
 366 static const TypeInfo xlnx_zynqmp_ipi_info = {
 367     .name          = TYPE_XLNX_ZYNQMP_IPI,
 368     .parent        = TYPE_SYS_BUS_DEVICE,
 369     .instance_size = sizeof(XlnxZynqMPIPI),
 370     .class_init    = xlnx_zynqmp_ipi_class_init,
 371     .instance_init = xlnx_zynqmp_ipi_init,
 372 };
 373
 374 static void xlnx_zynqmp_ipi_register_types(void)
 375 {
 376     type_register_static(&xlnx_zynqmp_ipi_info);
 377 }
 378
 379 type_init(xlnx_zynqmp_ipi_register_types)