hw/ipack/tpci200.c

   1 /*
   2  * QEMU TEWS TPCI200 IndustryPack carrier emulation
   3  *
   4  * Copyright (C) 2012 Igalia, S.L.
   5  * Author: Alberto Garcia <berto@igalia.com>
   6  *
   7  * This code is licensed under the GNU GPL v2 or (at your option) any
   8  * later version.
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "qemu/units.h"
  13 #include "hw/ipack/ipack.h"
  14 #include "hw/irq.h"
  15 #include "hw/pci/pci.h"
  16 #include "qemu/bitops.h"
  17 #include "qemu/module.h"
  18
  19 /* #define DEBUG_TPCI */
  20
  21 #ifdef DEBUG_TPCI
  22 #define DPRINTF(fmt, ...) \
  23     do { fprintf(stderr, "TPCI200: " fmt, ## __VA_ARGS__); } while (0)
  24 #else
  25 #define DPRINTF(fmt, ...) do { } while (0)
  26 #endif
  27
  28 #define N_MODULES 4
  29
  30 #define IP_ID_SPACE  2
  31 #define IP_INT_SPACE 3
  32 #define IP_IO_SPACE_ADDR_MASK  0x7F
  33 #define IP_ID_SPACE_ADDR_MASK  0x3F
  34 #define IP_INT_SPACE_ADDR_MASK 0x3F
  35
  36 #define STATUS_INT(IP, INTNO) BIT((IP) * 2 + (INTNO))
  37 #define STATUS_TIME(IP)       BIT((IP) + 12)
  38 #define STATUS_ERR_ANY        0xF00
  39
  40 #define CTRL_CLKRATE          BIT(0)
  41 #define CTRL_RECOVER          BIT(1)
  42 #define CTRL_TIME_INT         BIT(2)
  43 #define CTRL_ERR_INT          BIT(3)
  44 #define CTRL_INT_EDGE(INTNO)  BIT(4 + (INTNO))
  45 #define CTRL_INT(INTNO)       BIT(6 + (INTNO))
  46
  47 #define REG_REV_ID    0x00
  48 #define REG_IP_A_CTRL 0x02
  49 #define REG_IP_B_CTRL 0x04
  50 #define REG_IP_C_CTRL 0x06
  51 #define REG_IP_D_CTRL 0x08
  52 #define REG_RESET     0x0A
  53 #define REG_STATUS    0x0C
  54 #define IP_N_FROM_REG(REG) ((REG) / 2 - 1)
  55
  56 typedef struct {
  57     PCIDevice dev;
  58     IPackBus bus;
  59     MemoryRegion mmio;
  60     MemoryRegion io;
  61     MemoryRegion las0;
  62     MemoryRegion las1;
  63     MemoryRegion las2;
  64     MemoryRegion las3;
  65     bool big_endian[3];
  66     uint8_t ctrl[N_MODULES];
  67     uint16_t status;
  68     uint8_t int_set;
  69 } TPCI200State;
  70
  71 #define TYPE_TPCI200 "tpci200"
  72
  73 #define TPCI200(obj) \
  74     OBJECT_CHECK(TPCI200State, (obj), TYPE_TPCI200)
  75
  76 static const uint8_t local_config_regs[] = {
  77     0x00, 0xFF, 0xFF, 0x0F, 0x00, 0xFC, 0xFF, 0x0F, 0x00, 0x00, 0x00,
  78     0x0E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
  79     0x00, 0x08, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x01,
  80     0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0xA0, 0x60, 0x41, 0xD4,
  81     0xA2, 0x20, 0x41, 0x14, 0xA2, 0x20, 0x41, 0x14, 0xA2, 0x20, 0x01,
  82     0x14, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x08, 0x01, 0x02,
  83     0x00, 0x04, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x02, 0x41,
  84     0x00, 0x00, 0x00, 0x00, 0x40, 0x7A, 0x00, 0x52, 0x92, 0x24, 0x02
  85 };
  86
  87 static void adjust_addr(bool big_endian, hwaddr *addr, unsigned size)
  88 {
  89     /* During 8 bit access in big endian mode,
  90        odd and even addresses are swapped */
  91     if (big_endian && size == 1) {
  92         *addr ^= 1;
  93     }
  94 }
  95
  96 static uint64_t adjust_value(bool big_endian, uint64_t *val, unsigned size)
  97 {
  98     /* Local spaces only support 8/16 bit access,
  99      * so there's no need to care for sizes > 2 */
 100     if (big_endian && size == 2) {
 101         *val = bswap16(*val);
 102     }
 103     return *val;
 104 }
 105
 106 static void tpci200_set_irq(void *opaque, int intno, int level)
 107 {
 108     IPackDevice *ip = opaque;
 109     IPackBus *bus = IPACK_BUS(qdev_get_parent_bus(DEVICE(ip)));
 110     PCIDevice *pcidev = PCI_DEVICE(BUS(bus)->parent);
 111     TPCI200State *dev = TPCI200(pcidev);
 112     unsigned ip_n = ip->slot;
 113     uint16_t prev_status = dev->status;
 114
 115     assert(ip->slot >= 0 && ip->slot < N_MODULES);
 116
 117     /* The requested interrupt must be enabled in the IP CONTROL
 118      * register */
 119     if (!(dev->ctrl[ip_n] & CTRL_INT(intno))) {
 120         return;
 121     }
 122
 123     /* Update the interrupt status in the IP STATUS register */
 124     if (level) {
 125         dev->status |=  STATUS_INT(ip_n, intno);
 126     } else {
 127         dev->status &= ~STATUS_INT(ip_n, intno);
 128     }
 129
 130     /* Return if there are no changes */
 131     if (dev->status == prev_status) {
 132         return;
 133     }
 134
 135     DPRINTF("IP %u INT%u#: %u\n", ip_n, intno, level);
 136
 137     /* Check if the interrupt is edge sensitive */
 138     if (dev->ctrl[ip_n] & CTRL_INT_EDGE(intno)) {
 139         if (level) {
 140             pci_set_irq(&dev->dev, !dev->int_set);
 141             pci_set_irq(&dev->dev,  dev->int_set);
 142         }
 143     } else {
 144         unsigned i, j;
 145         uint16_t level_status = dev->status;
 146
 147         /* Check if there are any level sensitive interrupts set by
 148            removing the ones that are edge sensitive from the status
 149            register */
 150         for (i = 0; i < N_MODULES; i++) {
 151             for (j = 0; j < 2; j++) {
 152                 if (dev->ctrl[i] & CTRL_INT_EDGE(j)) {
 153                     level_status &= ~STATUS_INT(i, j);
 154                 }
 155             }
 156         }
 157
 158         if (level_status && !dev->int_set) {
 159             pci_irq_assert(&dev->dev);
 160             dev->int_set = 1;
 161         } else if (!level_status && dev->int_set) {
 162             pci_irq_deassert(&dev->dev);
 163             dev->int_set = 0;
 164         }
 165     }
 166 }
 167
 168 static uint64_t tpci200_read_cfg(void *opaque, hwaddr addr, unsigned size)
 169 {
 170     TPCI200State *s = opaque;
 171     uint8_t ret = 0;
 172     if (addr < ARRAY_SIZE(local_config_regs)) {
 173         ret = local_config_regs[addr];
 174     }
 175     /* Endianness is stored in the first bit of these registers */
 176     if ((addr == 0x2b && s->big_endian[0]) ||
 177         (addr == 0x2f && s->big_endian[1]) ||
 178         (addr == 0x33 && s->big_endian[2])) {
 179         ret |= 1;
 180     }
 181     DPRINTF("Read from LCR 0x%x: 0x%x\n", (unsigned) addr, (unsigned) ret);
 182     return ret;
 183 }
 184
 185 static void tpci200_write_cfg(void *opaque, hwaddr addr, uint64_t val,
 186                               unsigned size)
 187 {
 188     TPCI200State *s = opaque;
 189     /* Endianness is stored in the first bit of these registers */
 190     if (addr == 0x2b || addr == 0x2f || addr == 0x33) {
 191         unsigned las = (addr - 0x2b) / 4;
 192         s->big_endian[las] = val & 1;
 193         DPRINTF("LAS%u big endian mode: %u\n", las, (unsigned) val & 1);
 194     } else {
 195         DPRINTF("Write to LCR 0x%x: 0x%x\n", (unsigned) addr, (unsigned) val);
 196     }
 197 }
 198
 199 static uint64_t tpci200_read_las0(void *opaque, hwaddr addr, unsigned size)
 200 {
 201     TPCI200State *s = opaque;
 202     uint64_t ret = 0;
 203
 204     switch (addr) {
 205
 206     case REG_REV_ID:
 207         DPRINTF("Read REVISION ID\n"); /* Current value is 0x00 */
 208         break;
 209
 210     case REG_IP_A_CTRL:
 211     case REG_IP_B_CTRL:
 212     case REG_IP_C_CTRL:
 213     case REG_IP_D_CTRL:
 214         {
 215             unsigned ip_n = IP_N_FROM_REG(addr);
 216             ret = s->ctrl[ip_n];
 217             DPRINTF("Read IP %c CONTROL: 0x%x\n", 'A' + ip_n, (unsigned) ret);
 218         }
 219         break;
 220
 221     case REG_RESET:
 222         DPRINTF("Read RESET\n"); /* Not implemented */
 223         break;
 224
 225     case REG_STATUS:
 226         ret = s->status;
 227         DPRINTF("Read STATUS: 0x%x\n", (unsigned) ret);
 228         break;
 229
 230     /* Reserved */
 231     default:
 232         DPRINTF("Unsupported read from LAS0 0x%x\n", (unsigned) addr);
 233         break;
 234     }
 235
 236     return adjust_value(s->big_endian[0], &ret, size);
 237 }
 238
 239 static void tpci200_write_las0(void *opaque, hwaddr addr, uint64_t val,
 240                                unsigned size)
 241 {
 242     TPCI200State *s = opaque;
 243
 244     adjust_value(s->big_endian[0], &val, size);
 245
 246     switch (addr) {
 247
 248     case REG_REV_ID:
 249         DPRINTF("Write Revision ID: 0x%x\n", (unsigned) val); /* No effect */
 250         break;
 251
 252     case REG_IP_A_CTRL:
 253     case REG_IP_B_CTRL:
 254     case REG_IP_C_CTRL:
 255     case REG_IP_D_CTRL:
 256         {
 257             unsigned ip_n = IP_N_FROM_REG(addr);
 258             s->ctrl[ip_n] = val;
 259             DPRINTF("Write IP %c CONTROL: 0x%x\n", 'A' + ip_n, (unsigned) val);
 260         }
 261         break;
 262
 263     case REG_RESET:
 264         DPRINTF("Write RESET: 0x%x\n", (unsigned) val); /* Not implemented */
 265         break;
 266
 267     case REG_STATUS:
 268         {
 269             unsigned i;
 270
 271             for (i = 0; i < N_MODULES; i++) {
 272                 IPackDevice *ip = ipack_device_find(&s->bus, i);
 273
 274                 if (ip != NULL) {
 275                     if (val & STATUS_INT(i, 0)) {
 276                         DPRINTF("Clear IP %c INT0# status\n", 'A' + i);
 277                         qemu_irq_lower(ip->irq[0]);
 278                     }
 279                     if (val & STATUS_INT(i, 1)) {
 280                         DPRINTF("Clear IP %c INT1# status\n", 'A' + i);
 281                         qemu_irq_lower(ip->irq[1]);
 282                     }
 283                 }
 284
 285                 if (val & STATUS_TIME(i)) {
 286                     DPRINTF("Clear IP %c timeout\n", 'A' + i);
 287                     s->status &= ~STATUS_TIME(i);
 288                 }
 289             }
 290
 291             if (val & STATUS_ERR_ANY) {
 292                 DPRINTF("Unexpected write to STATUS register: 0x%x\n",
 293                         (unsigned) val);
 294             }
 295         }
 296         break;
 297
 298     /* Reserved */
 299     default:
 300         DPRINTF("Unsupported write to LAS0 0x%x: 0x%x\n",
 301                 (unsigned) addr, (unsigned) val);
 302         break;
 303     }
 304 }
 305
 306 static uint64_t tpci200_read_las1(void *opaque, hwaddr addr, unsigned size)
 307 {
 308     TPCI200State *s = opaque;
 309     IPackDevice *ip;
 310     uint64_t ret = 0;
 311     unsigned ip_n, space;
 312     uint8_t offset;
 313
 314     adjust_addr(s->big_endian[1], &addr, size);
 315
 316     /*
 317      * The address is divided into the IP module number (0-4), the IP
 318      * address space (I/O, ID, INT) and the offset within that space.
 319      */
 320     ip_n = addr >> 8;
 321     space = (addr >> 6) & 3;
 322     ip = ipack_device_find(&s->bus, ip_n);
 323
 324     if (ip == NULL) {
 325         DPRINTF("Read LAS1: IP module %u not installed\n", ip_n);
 326     } else {
 327         IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
 328         switch (space) {
 329
 330         case IP_ID_SPACE:
 331             offset = addr & IP_ID_SPACE_ADDR_MASK;
 332             if (k->id_read) {
 333                 ret = k->id_read(ip, offset);
 334             }
 335             break;
 336
 337         case IP_INT_SPACE:
 338             offset = addr & IP_INT_SPACE_ADDR_MASK;
 339
 340             /* Read address 0 to ACK IP INT0# and address 2 to ACK IP INT1# */
 341             if (offset == 0 || offset == 2) {
 342                 unsigned intno = offset / 2;
 343                 bool int_set = s->status & STATUS_INT(ip_n, intno);
 344                 bool int_edge_sensitive = s->ctrl[ip_n] & CTRL_INT_EDGE(intno);
 345                 if (int_set && !int_edge_sensitive) {
 346                     qemu_irq_lower(ip->irq[intno]);
 347                 }
 348             }
 349
 350             if (k->int_read) {
 351                 ret = k->int_read(ip, offset);
 352             }
 353             break;
 354
 355         default:
 356             offset = addr & IP_IO_SPACE_ADDR_MASK;
 357             if (k->io_read) {
 358                 ret = k->io_read(ip, offset);
 359             }
 360             break;
 361         }
 362     }
 363
 364     return adjust_value(s->big_endian[1], &ret, size);
 365 }
 366
 367 static void tpci200_write_las1(void *opaque, hwaddr addr, uint64_t val,
 368                                unsigned size)
 369 {
 370     TPCI200State *s = opaque;
 371     IPackDevice *ip;
 372     unsigned ip_n, space;
 373     uint8_t offset;
 374
 375     adjust_addr(s->big_endian[1], &addr, size);
 376     adjust_value(s->big_endian[1], &val, size);
 377
 378     /*
 379      * The address is divided into the IP module number, the IP
 380      * address space (I/O, ID, INT) and the offset within that space.
 381      */
 382     ip_n = addr >> 8;
 383     space = (addr >> 6) & 3;
 384     ip = ipack_device_find(&s->bus, ip_n);
 385
 386     if (ip == NULL) {
 387         DPRINTF("Write LAS1: IP module %u not installed\n", ip_n);
 388     } else {
 389         IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
 390         switch (space) {
 391
 392         case IP_ID_SPACE:
 393             offset = addr & IP_ID_SPACE_ADDR_MASK;
 394             if (k->id_write) {
 395                 k->id_write(ip, offset, val);
 396             }
 397             break;
 398
 399         case IP_INT_SPACE:
 400             offset = addr & IP_INT_SPACE_ADDR_MASK;
 401             if (k->int_write) {
 402                 k->int_write(ip, offset, val);
 403             }
 404             break;
 405
 406         default:
 407             offset = addr & IP_IO_SPACE_ADDR_MASK;
 408             if (k->io_write) {
 409                 k->io_write(ip, offset, val);
 410             }
 411             break;
 412         }
 413     }
 414 }
 415
 416 static uint64_t tpci200_read_las2(void *opaque, hwaddr addr, unsigned size)
 417 {
 418     TPCI200State *s = opaque;
 419     IPackDevice *ip;
 420     uint64_t ret = 0;
 421     unsigned ip_n;
 422     uint32_t offset;
 423
 424     adjust_addr(s->big_endian[2], &addr, size);
 425
 426     /*
 427      * The address is divided into the IP module number and the offset
 428      * within the IP module MEM space.
 429      */
 430     ip_n = addr >> 23;
 431     offset = addr & 0x7fffff;
 432     ip = ipack_device_find(&s->bus, ip_n);
 433
 434     if (ip == NULL) {
 435         DPRINTF("Read LAS2: IP module %u not installed\n", ip_n);
 436     } else {
 437         IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
 438         if (k->mem_read16) {
 439             ret = k->mem_read16(ip, offset);
 440         }
 441     }
 442
 443     return adjust_value(s->big_endian[2], &ret, size);
 444 }
 445
 446 static void tpci200_write_las2(void *opaque, hwaddr addr, uint64_t val,
 447                                unsigned size)
 448 {
 449     TPCI200State *s = opaque;
 450     IPackDevice *ip;
 451     unsigned ip_n;
 452     uint32_t offset;
 453
 454     adjust_addr(s->big_endian[2], &addr, size);
 455     adjust_value(s->big_endian[2], &val, size);
 456
 457     /*
 458      * The address is divided into the IP module number and the offset
 459      * within the IP module MEM space.
 460      */
 461     ip_n = addr >> 23;
 462     offset = addr & 0x7fffff;
 463     ip = ipack_device_find(&s->bus, ip_n);
 464
 465     if (ip == NULL) {
 466         DPRINTF("Write LAS2: IP module %u not installed\n", ip_n);
 467     } else {
 468         IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
 469         if (k->mem_write16) {
 470             k->mem_write16(ip, offset, val);
 471         }
 472     }
 473 }
 474
 475 static uint64_t tpci200_read_las3(void *opaque, hwaddr addr, unsigned size)
 476 {
 477     TPCI200State *s = opaque;
 478     IPackDevice *ip;
 479     uint64_t ret = 0;
 480     /*
 481      * The address is divided into the IP module number and the offset
 482      * within the IP module MEM space.
 483      */
 484     unsigned ip_n = addr >> 22;
 485     uint32_t offset = addr & 0x3fffff;
 486
 487     ip = ipack_device_find(&s->bus, ip_n);
 488
 489     if (ip == NULL) {
 490         DPRINTF("Read LAS3: IP module %u not installed\n", ip_n);
 491     } else {
 492         IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
 493         if (k->mem_read8) {
 494             ret = k->mem_read8(ip, offset);
 495         }
 496     }
 497
 498     return ret;
 499 }
 500
 501 static void tpci200_write_las3(void *opaque, hwaddr addr, uint64_t val,
 502                                unsigned size)
 503 {
 504     TPCI200State *s = opaque;
 505     IPackDevice *ip;
 506     /*
 507      * The address is divided into the IP module number and the offset
 508      * within the IP module MEM space.
 509      */
 510     unsigned ip_n = addr >> 22;
 511     uint32_t offset = addr & 0x3fffff;
 512
 513     ip = ipack_device_find(&s->bus, ip_n);
 514
 515     if (ip == NULL) {
 516         DPRINTF("Write LAS3: IP module %u not installed\n", ip_n);
 517     } else {
 518         IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
 519         if (k->mem_write8) {
 520             k->mem_write8(ip, offset, val);
 521         }
 522     }
 523 }
 524
 525 static const MemoryRegionOps tpci200_cfg_ops = {
 526     .read = tpci200_read_cfg,
 527     .write = tpci200_write_cfg,
 528     .endianness = DEVICE_NATIVE_ENDIAN,
 529     .valid =  {
 530         .min_access_size = 1,
 531         .max_access_size = 4
 532     },
 533     .impl = {
 534         .min_access_size = 1,
 535         .max_access_size = 1
 536     }
 537 };
 538
 539 static const MemoryRegionOps tpci200_las0_ops = {
 540     .read = tpci200_read_las0,
 541     .write = tpci200_write_las0,
 542     .endianness = DEVICE_NATIVE_ENDIAN,
 543     .valid =  {
 544         .min_access_size = 2,
 545         .max_access_size = 2
 546     }
 547 };
 548
 549 static const MemoryRegionOps tpci200_las1_ops = {
 550     .read = tpci200_read_las1,
 551     .write = tpci200_write_las1,
 552     .endianness = DEVICE_NATIVE_ENDIAN,
 553     .valid =  {
 554         .min_access_size = 1,
 555         .max_access_size = 2
 556     }
 557 };
 558
 559 static const MemoryRegionOps tpci200_las2_ops = {
 560     .read = tpci200_read_las2,
 561     .write = tpci200_write_las2,
 562     .endianness = DEVICE_NATIVE_ENDIAN,
 563     .valid =  {
 564         .min_access_size = 1,
 565         .max_access_size = 2
 566     }
 567 };
 568
 569 static const MemoryRegionOps tpci200_las3_ops = {
 570     .read = tpci200_read_las3,
 571     .write = tpci200_write_las3,
 572     .endianness = DEVICE_NATIVE_ENDIAN,
 573     .valid =  {
 574         .min_access_size = 1,
 575         .max_access_size = 1
 576     }
 577 };
 578
 579 static void tpci200_realize(PCIDevice *pci_dev, Error **errp)
 580 {
 581     TPCI200State *s = TPCI200(pci_dev);
 582     uint8_t *c = s->dev.config;
 583
 584     pci_set_word(c + PCI_COMMAND, 0x0003);
 585     pci_set_word(c + PCI_STATUS,  0x0280);
 586
 587     pci_set_byte(c + PCI_INTERRUPT_PIN, 0x01); /* Interrupt pin A */
 588
 589     pci_set_byte(c + PCI_CAPABILITY_LIST, 0x40);
 590     pci_set_long(c + 0x40, 0x48014801);
 591     pci_set_long(c + 0x48, 0x00024C06);
 592     pci_set_long(c + 0x4C, 0x00000003);
 593
 594     memory_region_init_io(&s->mmio, OBJECT(s), &tpci200_cfg_ops,
 595                           s, "tpci200_mmio", 128);
 596     memory_region_init_io(&s->io, OBJECT(s),   &tpci200_cfg_ops,
 597                           s, "tpci200_io",   128);
 598     memory_region_init_io(&s->las0, OBJECT(s), &tpci200_las0_ops,
 599                           s, "tpci200_las0", 256);
 600     memory_region_init_io(&s->las1, OBJECT(s), &tpci200_las1_ops,
 601                           s, "tpci200_las1", 1024);
 602     memory_region_init_io(&s->las2, OBJECT(s), &tpci200_las2_ops,
 603                           s, "tpci200_las2", 32 * MiB);
 604     memory_region_init_io(&s->las3, OBJECT(s), &tpci200_las3_ops,
 605                           s, "tpci200_las3", 16 * MiB);
 606     pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
 607     pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO,     &s->io);
 608     pci_register_bar(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las0);
 609     pci_register_bar(&s->dev, 3, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las1);
 610     pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las2);
 611     pci_register_bar(&s->dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las3);
 612
 613     ipack_bus_new_inplace(&s->bus, sizeof(s->bus), DEVICE(pci_dev), NULL,
 614                           N_MODULES, tpci200_set_irq);
 615 }
 616
 617 static const VMStateDescription vmstate_tpci200 = {
 618     .name = "tpci200",
 619     .version_id = 1,
 620     .minimum_version_id = 1,
 621     .fields = (VMStateField[]) {
 622         VMSTATE_PCI_DEVICE(dev, TPCI200State),
 623         VMSTATE_BOOL_ARRAY(big_endian, TPCI200State, 3),
 624         VMSTATE_UINT8_ARRAY(ctrl, TPCI200State, N_MODULES),
 625         VMSTATE_UINT16(status, TPCI200State),
 626         VMSTATE_UINT8(int_set, TPCI200State),
 627         VMSTATE_END_OF_LIST()
 628     }
 629 };
 630
 631 static void tpci200_class_init(ObjectClass *klass, void *data)
 632 {
 633     DeviceClass *dc = DEVICE_CLASS(klass);
 634     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 635
 636     k->realize = tpci200_realize;
 637     k->vendor_id = PCI_VENDOR_ID_TEWS;
 638     k->device_id = PCI_DEVICE_ID_TEWS_TPCI200;
 639     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 640     k->subsystem_vendor_id = PCI_VENDOR_ID_TEWS;
 641     k->subsystem_id = 0x300A;
 642     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 643     dc->desc = "TEWS TPCI200 IndustryPack carrier";
 644     dc->vmsd = &vmstate_tpci200;
 645 }
 646
 647 static const TypeInfo tpci200_info = {
 648     .name          = TYPE_TPCI200,
 649     .parent        = TYPE_PCI_DEVICE,
 650     .instance_size = sizeof(TPCI200State),
 651     .class_init    = tpci200_class_init,
 652     .interfaces = (InterfaceInfo[]) {
 653         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 654         { },
 655     },
 656 };
 657
 658 static void tpci200_register_types(void)
 659 {
 660     type_register_static(&tpci200_info);
 661 }
 662
 663 type_init(tpci200_register_types)