2 * Motorola ColdFire MCF5206 SoC embedded peripheral emulation.
4 * Copyright (c) 2007 CodeSourcery.
6 * This code is licensed under the GPL
8 #include "qemu/osdep.h"
9 #include "qemu/error-report.h"
12 #include "hw/m68k/mcf.h"
13 #include "qemu/timer.h"
14 #include "hw/ptimer.h"
15 #include "sysemu/sysemu.h"
17 /* General purpose timer module. */
38 static void m5206_timer_update(m5206_timer_state
*s
)
40 if ((s
->tmr
& TMR_ORI
) != 0 && (s
->ter
& TER_REF
))
41 qemu_irq_raise(s
->irq
);
43 qemu_irq_lower(s
->irq
);
46 static void m5206_timer_reset(m5206_timer_state
*s
)
52 static void m5206_timer_recalibrate(m5206_timer_state
*s
)
57 ptimer_stop(s
->timer
);
59 if ((s
->tmr
& TMR_RST
) == 0)
62 prescale
= (s
->tmr
>> 8) + 1;
63 mode
= (s
->tmr
>> 1) & 3;
67 if (mode
== 3 || mode
== 0)
68 hw_error("m5206_timer: mode %d not implemented\n", mode
);
69 if ((s
->tmr
& TMR_FRR
) == 0)
70 hw_error("m5206_timer: free running mode not implemented\n");
72 /* Assume 66MHz system clock. */
73 ptimer_set_freq(s
->timer
, 66000000 / prescale
);
75 ptimer_set_limit(s
->timer
, s
->trr
, 0);
77 ptimer_run(s
->timer
, 0);
80 static void m5206_timer_trigger(void *opaque
)
82 m5206_timer_state
*s
= (m5206_timer_state
*)opaque
;
84 m5206_timer_update(s
);
87 static uint32_t m5206_timer_read(m5206_timer_state
*s
, uint32_t addr
)
97 return s
->trr
- ptimer_get_count(s
->timer
);
105 static void m5206_timer_write(m5206_timer_state
*s
, uint32_t addr
, uint32_t val
)
109 if ((s
->tmr
& TMR_RST
) != 0 && (val
& TMR_RST
) == 0) {
110 m5206_timer_reset(s
);
113 m5206_timer_recalibrate(s
);
117 m5206_timer_recalibrate(s
);
123 ptimer_set_count(s
->timer
, val
);
131 m5206_timer_update(s
);
134 static m5206_timer_state
*m5206_timer_init(qemu_irq irq
)
136 m5206_timer_state
*s
;
139 s
= g_new0(m5206_timer_state
, 1);
140 bh
= qemu_bh_new(m5206_timer_trigger
, s
);
141 s
->timer
= ptimer_init(bh
, PTIMER_POLICY_DEFAULT
);
143 m5206_timer_reset(s
);
147 /* System Integration Module. */
152 m5206_timer_state
*timer
[2];
156 uint16_t imr
; /* 1 == interrupt is masked. */
161 /* Include the UART vector registers here. */
165 /* Interrupt controller. */
167 static int m5206_find_pending_irq(m5206_mbar_state
*s
)
176 active
= s
->ipr
& ~s
->imr
;
180 for (i
= 1; i
< 14; i
++) {
181 if (active
& (1 << i
)) {
182 if ((s
->icr
[i
] & 0x1f) > level
) {
183 level
= s
->icr
[i
] & 0x1f;
195 static void m5206_mbar_update(m5206_mbar_state
*s
)
201 irq
= m5206_find_pending_irq(s
);
205 level
= (tmp
>> 2) & 7;
221 /* Unknown vector. */
222 error_report("Unhandled vector for IRQ %d", irq
);
231 m68k_set_irq_level(s
->cpu
, level
, vector
);
234 static void m5206_mbar_set_irq(void *opaque
, int irq
, int level
)
236 m5206_mbar_state
*s
= (m5206_mbar_state
*)opaque
;
240 s
->ipr
&= ~(1 << irq
);
242 m5206_mbar_update(s
);
245 /* System Integration Module. */
247 static void m5206_mbar_reset(m5206_mbar_state
*s
)
269 static uint64_t m5206_mbar_read(m5206_mbar_state
*s
,
270 uint64_t offset
, unsigned size
)
272 if (offset
>= 0x100 && offset
< 0x120) {
273 return m5206_timer_read(s
->timer
[0], offset
- 0x100);
274 } else if (offset
>= 0x120 && offset
< 0x140) {
275 return m5206_timer_read(s
->timer
[1], offset
- 0x120);
276 } else if (offset
>= 0x140 && offset
< 0x160) {
277 return mcf_uart_read(s
->uart
[0], offset
- 0x140, size
);
278 } else if (offset
>= 0x180 && offset
< 0x1a0) {
279 return mcf_uart_read(s
->uart
[1], offset
- 0x180, size
);
282 case 0x03: return s
->scr
;
283 case 0x14 ... 0x20: return s
->icr
[offset
- 0x13];
284 case 0x36: return s
->imr
;
285 case 0x3a: return s
->ipr
;
286 case 0x40: return s
->rsr
;
288 case 0x42: return s
->swivr
;
290 /* DRAM mask register. */
291 /* FIXME: currently hardcoded to 128Mb. */
294 while (mask
> ram_size
)
296 return mask
& 0x0ffe0000;
298 case 0x5c: return 1; /* DRAM bank 1 empty. */
299 case 0xcb: return s
->par
;
300 case 0x170: return s
->uivr
[0];
301 case 0x1b0: return s
->uivr
[1];
303 hw_error("Bad MBAR read offset 0x%x", (int)offset
);
307 static void m5206_mbar_write(m5206_mbar_state
*s
, uint32_t offset
,
308 uint64_t value
, unsigned size
)
310 if (offset
>= 0x100 && offset
< 0x120) {
311 m5206_timer_write(s
->timer
[0], offset
- 0x100, value
);
313 } else if (offset
>= 0x120 && offset
< 0x140) {
314 m5206_timer_write(s
->timer
[1], offset
- 0x120, value
);
316 } else if (offset
>= 0x140 && offset
< 0x160) {
317 mcf_uart_write(s
->uart
[0], offset
- 0x140, value
, size
);
319 } else if (offset
>= 0x180 && offset
< 0x1a0) {
320 mcf_uart_write(s
->uart
[1], offset
- 0x180, value
, size
);
328 s
->icr
[offset
- 0x13] = value
;
329 m5206_mbar_update(s
);
333 m5206_mbar_update(s
);
339 /* TODO: implement watchdog. */
350 case 0x178: case 0x17c: case 0x1c8: case 0x1bc:
351 /* Not implemented: UART Output port bits. */
357 hw_error("Bad MBAR write offset 0x%x", (int)offset
);
362 /* Internal peripherals use a variety of register widths.
363 This lookup table allows a single routine to handle all of them. */
364 static const uint8_t m5206_mbar_width
[] =
366 /* 000-040 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
367 /* 040-080 */ 1, 2, 2, 2, 4, 1, 2, 4, 1, 2, 4, 2, 2, 4, 2, 2,
368 /* 080-0c0 */ 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4, 2, 2, 4,
369 /* 0c0-100 */ 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
370 /* 100-140 */ 2, 2, 2, 2, 1, 0, 0, 0, 2, 2, 2, 2, 1, 0, 0, 0,
371 /* 140-180 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
372 /* 180-1c0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
373 /* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
376 static uint32_t m5206_mbar_readw(void *opaque
, hwaddr offset
);
377 static uint32_t m5206_mbar_readl(void *opaque
, hwaddr offset
);
379 static uint32_t m5206_mbar_readb(void *opaque
, hwaddr offset
)
381 m5206_mbar_state
*s
= (m5206_mbar_state
*)opaque
;
383 if (offset
>= 0x200) {
384 hw_error("Bad MBAR read offset 0x%x", (int)offset
);
386 if (m5206_mbar_width
[offset
>> 2] > 1) {
388 val
= m5206_mbar_readw(opaque
, offset
& ~1);
389 if ((offset
& 1) == 0) {
394 return m5206_mbar_read(s
, offset
, 1);
397 static uint32_t m5206_mbar_readw(void *opaque
, hwaddr offset
)
399 m5206_mbar_state
*s
= (m5206_mbar_state
*)opaque
;
402 if (offset
>= 0x200) {
403 hw_error("Bad MBAR read offset 0x%x", (int)offset
);
405 width
= m5206_mbar_width
[offset
>> 2];
408 val
= m5206_mbar_readl(opaque
, offset
& ~3);
409 if ((offset
& 3) == 0)
412 } else if (width
< 2) {
414 val
= m5206_mbar_readb(opaque
, offset
) << 8;
415 val
|= m5206_mbar_readb(opaque
, offset
+ 1);
418 return m5206_mbar_read(s
, offset
, 2);
421 static uint32_t m5206_mbar_readl(void *opaque
, hwaddr offset
)
423 m5206_mbar_state
*s
= (m5206_mbar_state
*)opaque
;
426 if (offset
>= 0x200) {
427 hw_error("Bad MBAR read offset 0x%x", (int)offset
);
429 width
= m5206_mbar_width
[offset
>> 2];
432 val
= m5206_mbar_readw(opaque
, offset
) << 16;
433 val
|= m5206_mbar_readw(opaque
, offset
+ 2);
436 return m5206_mbar_read(s
, offset
, 4);
439 static void m5206_mbar_writew(void *opaque
, hwaddr offset
,
441 static void m5206_mbar_writel(void *opaque
, hwaddr offset
,
444 static void m5206_mbar_writeb(void *opaque
, hwaddr offset
,
447 m5206_mbar_state
*s
= (m5206_mbar_state
*)opaque
;
450 if (offset
>= 0x200) {
451 hw_error("Bad MBAR write offset 0x%x", (int)offset
);
453 width
= m5206_mbar_width
[offset
>> 2];
456 tmp
= m5206_mbar_readw(opaque
, offset
& ~1);
458 tmp
= (tmp
& 0xff00) | value
;
460 tmp
= (tmp
& 0x00ff) | (value
<< 8);
462 m5206_mbar_writew(opaque
, offset
& ~1, tmp
);
465 m5206_mbar_write(s
, offset
, value
, 1);
468 static void m5206_mbar_writew(void *opaque
, hwaddr offset
,
471 m5206_mbar_state
*s
= (m5206_mbar_state
*)opaque
;
474 if (offset
>= 0x200) {
475 hw_error("Bad MBAR write offset 0x%x", (int)offset
);
477 width
= m5206_mbar_width
[offset
>> 2];
480 tmp
= m5206_mbar_readl(opaque
, offset
& ~3);
482 tmp
= (tmp
& 0xffff0000) | value
;
484 tmp
= (tmp
& 0x0000ffff) | (value
<< 16);
486 m5206_mbar_writel(opaque
, offset
& ~3, tmp
);
488 } else if (width
< 2) {
489 m5206_mbar_writeb(opaque
, offset
, value
>> 8);
490 m5206_mbar_writeb(opaque
, offset
+ 1, value
& 0xff);
493 m5206_mbar_write(s
, offset
, value
, 2);
496 static void m5206_mbar_writel(void *opaque
, hwaddr offset
,
499 m5206_mbar_state
*s
= (m5206_mbar_state
*)opaque
;
502 if (offset
>= 0x200) {
503 hw_error("Bad MBAR write offset 0x%x", (int)offset
);
505 width
= m5206_mbar_width
[offset
>> 2];
507 m5206_mbar_writew(opaque
, offset
, value
>> 16);
508 m5206_mbar_writew(opaque
, offset
+ 2, value
& 0xffff);
511 m5206_mbar_write(s
, offset
, value
, 4);
514 static uint64_t m5206_mbar_readfn(void *opaque
, hwaddr addr
, unsigned size
)
518 return m5206_mbar_readb(opaque
, addr
);
520 return m5206_mbar_readw(opaque
, addr
);
522 return m5206_mbar_readl(opaque
, addr
);
524 g_assert_not_reached();
528 static void m5206_mbar_writefn(void *opaque
, hwaddr addr
,
529 uint64_t value
, unsigned size
)
533 m5206_mbar_writeb(opaque
, addr
, value
);
536 m5206_mbar_writew(opaque
, addr
, value
);
539 m5206_mbar_writel(opaque
, addr
, value
);
542 g_assert_not_reached();
546 static const MemoryRegionOps m5206_mbar_ops
= {
547 .read
= m5206_mbar_readfn
,
548 .write
= m5206_mbar_writefn
,
549 .valid
.min_access_size
= 1,
550 .valid
.max_access_size
= 4,
551 .endianness
= DEVICE_NATIVE_ENDIAN
,
554 qemu_irq
*mcf5206_init(MemoryRegion
*sysmem
, uint32_t base
, M68kCPU
*cpu
)
559 s
= g_new0(m5206_mbar_state
, 1);
561 memory_region_init_io(&s
->iomem
, NULL
, &m5206_mbar_ops
, s
,
563 memory_region_add_subregion(sysmem
, base
, &s
->iomem
);
565 pic
= qemu_allocate_irqs(m5206_mbar_set_irq
, s
, 14);
566 s
->timer
[0] = m5206_timer_init(pic
[9]);
567 s
->timer
[1] = m5206_timer_init(pic
[10]);
568 s
->uart
[0] = mcf_uart_init(pic
[12], serial_hd(0));
569 s
->uart
[1] = mcf_uart_init(pic
[13], serial_hd(1));