hw/m68k/mcf_intc.c

   1 /*
   2  * ColdFire Interrupt Controller emulation.
   3  *
   4  * Copyright (c) 2007 CodeSourcery.
   5  *
   6  * This code is licensed under the GPL
   7  */
   8
   9 #include "qemu/osdep.h"
  10 #include "qapi/error.h"
  11 #include "qemu/module.h"
  12 #include "qemu/log.h"
  13 #include "cpu.h"
  14 #include "hw/hw.h"
  15 #include "hw/irq.h"
  16 #include "hw/sysbus.h"
  17 #include "hw/m68k/mcf.h"
  18 #include "qom/object.h"
  19
  20 #define TYPE_MCF_INTC "mcf-intc"
  21 typedef struct mcf_intc_state mcf_intc_state;
  22 DECLARE_INSTANCE_CHECKER(mcf_intc_state, MCF_INTC,
  23                          TYPE_MCF_INTC)
  24
  25 struct mcf_intc_state {
  26     SysBusDevice parent_obj;
  27
  28     MemoryRegion iomem;
  29     uint64_t ipr;
  30     uint64_t imr;
  31     uint64_t ifr;
  32     uint64_t enabled;
  33     uint8_t icr[64];
  34     M68kCPU *cpu;
  35     int active_vector;
  36 };
  37
  38 static void mcf_intc_update(mcf_intc_state *s)
  39 {
  40     uint64_t active;
  41     int i;
  42     int best;
  43     int best_level;
  44
  45     active = (s->ipr | s->ifr) & s->enabled & ~s->imr;
  46     best_level = 0;
  47     best = 64;
  48     if (active) {
  49         for (i = 0; i < 64; i++) {
  50             if ((active & 1) != 0 && s->icr[i] >= best_level) {
  51                 best_level = s->icr[i];
  52                 best = i;
  53             }
  54             active >>= 1;
  55         }
  56     }
  57     s->active_vector = ((best == 64) ? 24 : (best + 64));
  58     m68k_set_irq_level(s->cpu, best_level, s->active_vector);
  59 }
  60
  61 static uint64_t mcf_intc_read(void *opaque, hwaddr addr,
  62                               unsigned size)
  63 {
  64     int offset;
  65     mcf_intc_state *s = (mcf_intc_state *)opaque;
  66     offset = addr & 0xff;
  67     if (offset >= 0x40 && offset < 0x80) {
  68         return s->icr[offset - 0x40];
  69     }
  70     switch (offset) {
  71     case 0x00:
  72         return (uint32_t)(s->ipr >> 32);
  73     case 0x04:
  74         return (uint32_t)s->ipr;
  75     case 0x08:
  76         return (uint32_t)(s->imr >> 32);
  77     case 0x0c:
  78         return (uint32_t)s->imr;
  79     case 0x10:
  80         return (uint32_t)(s->ifr >> 32);
  81     case 0x14:
  82         return (uint32_t)s->ifr;
  83     case 0xe0: /* SWIACK.  */
  84         return s->active_vector;
  85     case 0xe1: case 0xe2: case 0xe3: case 0xe4:
  86     case 0xe5: case 0xe6: case 0xe7:
  87         /* LnIACK */
  88         qemu_log_mask(LOG_UNIMP, "%s: LnIACK not implemented (offset 0x%02x)\n",
  89                       __func__, offset);
  90         /* fallthru */
  91     default:
  92         return 0;
  93     }
  94 }
  95
  96 static void mcf_intc_write(void *opaque, hwaddr addr,
  97                            uint64_t val, unsigned size)
  98 {
  99     int offset;
 100     mcf_intc_state *s = (mcf_intc_state *)opaque;
 101     offset = addr & 0xff;
 102     if (offset >= 0x40 && offset < 0x80) {
 103         int n = offset - 0x40;
 104         s->icr[n] = val;
 105         if (val == 0)
 106             s->enabled &= ~(1ull << n);
 107         else
 108             s->enabled |= (1ull << n);
 109         mcf_intc_update(s);
 110         return;
 111     }
 112     switch (offset) {
 113     case 0x00: case 0x04:
 114         /* Ignore IPR writes.  */
 115         return;
 116     case 0x08:
 117         s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32);
 118         break;
 119     case 0x0c:
 120         s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;
 121         break;
 122     case 0x1c:
 123         if (val & 0x40) {
 124             s->imr = ~0ull;
 125         } else {
 126             s->imr |= (0x1ull << (val & 0x3f));
 127         }
 128         break;
 129     case 0x1d:
 130         if (val & 0x40) {
 131             s->imr = 0ull;
 132         } else {
 133             s->imr &= ~(0x1ull << (val & 0x3f));
 134         }
 135         break;
 136     default:
 137         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n",
 138                       __func__, offset);
 139         return;
 140     }
 141     mcf_intc_update(s);
 142 }
 143
 144 static void mcf_intc_set_irq(void *opaque, int irq, int level)
 145 {
 146     mcf_intc_state *s = (mcf_intc_state *)opaque;
 147     if (irq >= 64)
 148         return;
 149     if (level)
 150         s->ipr |= 1ull << irq;
 151     else
 152         s->ipr &= ~(1ull << irq);
 153     mcf_intc_update(s);
 154 }
 155
 156 static void mcf_intc_reset(DeviceState *dev)
 157 {
 158     mcf_intc_state *s = MCF_INTC(dev);
 159
 160     s->imr = ~0ull;
 161     s->ipr = 0;
 162     s->ifr = 0;
 163     s->enabled = 0;
 164     memset(s->icr, 0, 64);
 165     s->active_vector = 24;
 166 }
 167
 168 static const MemoryRegionOps mcf_intc_ops = {
 169     .read = mcf_intc_read,
 170     .write = mcf_intc_write,
 171     .endianness = DEVICE_NATIVE_ENDIAN,
 172 };
 173
 174 static void mcf_intc_instance_init(Object *obj)
 175 {
 176     mcf_intc_state *s = MCF_INTC(obj);
 177
 178     memory_region_init_io(&s->iomem, obj, &mcf_intc_ops, s, "mcf", 0x100);
 179 }
 180
 181 static void mcf_intc_class_init(ObjectClass *oc, void *data)
 182 {
 183     DeviceClass *dc = DEVICE_CLASS(oc);
 184
 185     set_bit(DEVICE_CATEGORY_MISC, dc->categories);
 186     dc->reset = mcf_intc_reset;
 187 }
 188
 189 static const TypeInfo mcf_intc_gate_info = {
 190     .name          = TYPE_MCF_INTC,
 191     .parent        = TYPE_SYS_BUS_DEVICE,
 192     .instance_size = sizeof(mcf_intc_state),
 193     .instance_init = mcf_intc_instance_init,
 194     .class_init    = mcf_intc_class_init,
 195 };
 196
 197 static void mcf_intc_register_types(void)
 198 {
 199     type_register_static(&mcf_intc_gate_info);
 200 }
 201
 202 type_init(mcf_intc_register_types)
 203
 204 qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
 205                         hwaddr base,
 206                         M68kCPU *cpu)
 207 {
 208     DeviceState  *dev;
 209     mcf_intc_state *s;
 210
 211     dev = qdev_new(TYPE_MCF_INTC);
 212     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 213
 214     s = MCF_INTC(dev);
 215     s->cpu = cpu;
 216
 217     memory_region_add_subregion(sysmem, base, &s->iomem);
 218
 219     return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
 220 }