hw/mips/boston.c

   1 /*
   2  * MIPS Boston development board emulation.
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/units.h"
  22
  23 #include "exec/address-spaces.h"
  24 #include "hw/boards.h"
  25 #include "hw/char/serial.h"
  26 #include "hw/ide/pci.h"
  27 #include "hw/ide/ahci.h"
  28 #include "hw/loader.h"
  29 #include "hw/loader-fit.h"
  30 #include "hw/mips/cps.h"
  31 #include "hw/mips/cpudevs.h"
  32 #include "hw/pci-host/xilinx-pcie.h"
  33 #include "hw/qdev-properties.h"
  34 #include "qapi/error.h"
  35 #include "qemu/error-report.h"
  36 #include "qemu/log.h"
  37 #include "chardev/char.h"
  38 #include "sysemu/device_tree.h"
  39 #include "sysemu/sysemu.h"
  40 #include "sysemu/qtest.h"
  41 #include "sysemu/runstate.h"
  42
  43 #include <libfdt.h>
  44 #include "qom/object.h"
  45
  46 #define TYPE_MIPS_BOSTON "mips-boston"
  47 typedef struct BostonState BostonState;
  48 #define BOSTON(obj) OBJECT_CHECK(BostonState, (obj), TYPE_MIPS_BOSTON)
  49
  50 struct BostonState {
  51     SysBusDevice parent_obj;
  52
  53     MachineState *mach;
  54     MIPSCPSState cps;
  55     SerialMM *uart;
  56
  57     CharBackend lcd_display;
  58     char lcd_content[8];
  59     bool lcd_inited;
  60
  61     hwaddr kernel_entry;
  62     hwaddr fdt_base;
  63 };
  64
  65 enum boston_plat_reg {
  66     PLAT_FPGA_BUILD     = 0x00,
  67     PLAT_CORE_CL        = 0x04,
  68     PLAT_WRAPPER_CL     = 0x08,
  69     PLAT_SYSCLK_STATUS  = 0x0c,
  70     PLAT_SOFTRST_CTL    = 0x10,
  71 #define PLAT_SOFTRST_CTL_SYSRESET       (1 << 4)
  72     PLAT_DDR3_STATUS    = 0x14,
  73 #define PLAT_DDR3_STATUS_LOCKED         (1 << 0)
  74 #define PLAT_DDR3_STATUS_CALIBRATED     (1 << 2)
  75     PLAT_PCIE_STATUS    = 0x18,
  76 #define PLAT_PCIE_STATUS_PCIE0_LOCKED   (1 << 0)
  77 #define PLAT_PCIE_STATUS_PCIE1_LOCKED   (1 << 8)
  78 #define PLAT_PCIE_STATUS_PCIE2_LOCKED   (1 << 16)
  79     PLAT_FLASH_CTL      = 0x1c,
  80     PLAT_SPARE0         = 0x20,
  81     PLAT_SPARE1         = 0x24,
  82     PLAT_SPARE2         = 0x28,
  83     PLAT_SPARE3         = 0x2c,
  84     PLAT_MMCM_DIV       = 0x30,
  85 #define PLAT_MMCM_DIV_CLK0DIV_SHIFT     0
  86 #define PLAT_MMCM_DIV_INPUT_SHIFT       8
  87 #define PLAT_MMCM_DIV_MUL_SHIFT         16
  88 #define PLAT_MMCM_DIV_CLK1DIV_SHIFT     24
  89     PLAT_BUILD_CFG      = 0x34,
  90 #define PLAT_BUILD_CFG_IOCU_EN          (1 << 0)
  91 #define PLAT_BUILD_CFG_PCIE0_EN         (1 << 1)
  92 #define PLAT_BUILD_CFG_PCIE1_EN         (1 << 2)
  93 #define PLAT_BUILD_CFG_PCIE2_EN         (1 << 3)
  94     PLAT_DDR_CFG        = 0x38,
  95 #define PLAT_DDR_CFG_SIZE               (0xf << 0)
  96 #define PLAT_DDR_CFG_MHZ                (0xfff << 4)
  97     PLAT_NOC_PCIE0_ADDR = 0x3c,
  98     PLAT_NOC_PCIE1_ADDR = 0x40,
  99     PLAT_NOC_PCIE2_ADDR = 0x44,
 100     PLAT_SYS_CTL        = 0x48,
 101 };
 102
 103 static void boston_lcd_event(void *opaque, QEMUChrEvent event)
 104 {
 105     BostonState *s = opaque;
 106     if (event == CHR_EVENT_OPENED && !s->lcd_inited) {
 107         qemu_chr_fe_printf(&s->lcd_display, "        ");
 108         s->lcd_inited = true;
 109     }
 110 }
 111
 112 static uint64_t boston_lcd_read(void *opaque, hwaddr addr,
 113                                 unsigned size)
 114 {
 115     BostonState *s = opaque;
 116     uint64_t val = 0;
 117
 118     switch (size) {
 119     case 8:
 120         val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56;
 121         val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48;
 122         val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40;
 123         val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32;
 124         /* fall through */
 125     case 4:
 126         val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24;
 127         val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16;
 128         /* fall through */
 129     case 2:
 130         val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8;
 131         /* fall through */
 132     case 1:
 133         val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7];
 134         break;
 135     }
 136
 137     return val;
 138 }
 139
 140 static void boston_lcd_write(void *opaque, hwaddr addr,
 141                              uint64_t val, unsigned size)
 142 {
 143     BostonState *s = opaque;
 144
 145     switch (size) {
 146     case 8:
 147         s->lcd_content[(addr + 7) & 0x7] = val >> 56;
 148         s->lcd_content[(addr + 6) & 0x7] = val >> 48;
 149         s->lcd_content[(addr + 5) & 0x7] = val >> 40;
 150         s->lcd_content[(addr + 4) & 0x7] = val >> 32;
 151         /* fall through */
 152     case 4:
 153         s->lcd_content[(addr + 3) & 0x7] = val >> 24;
 154         s->lcd_content[(addr + 2) & 0x7] = val >> 16;
 155         /* fall through */
 156     case 2:
 157         s->lcd_content[(addr + 1) & 0x7] = val >> 8;
 158         /* fall through */
 159     case 1:
 160         s->lcd_content[(addr + 0) & 0x7] = val;
 161         break;
 162     }
 163
 164     qemu_chr_fe_printf(&s->lcd_display,
 165                        "\r%-8.8s", s->lcd_content);
 166 }
 167
 168 static const MemoryRegionOps boston_lcd_ops = {
 169     .read = boston_lcd_read,
 170     .write = boston_lcd_write,
 171     .endianness = DEVICE_NATIVE_ENDIAN,
 172 };
 173
 174 static uint64_t boston_platreg_read(void *opaque, hwaddr addr,
 175                                     unsigned size)
 176 {
 177     BostonState *s = opaque;
 178     uint32_t gic_freq, val;
 179
 180     if (size != 4) {
 181         qemu_log_mask(LOG_UNIMP, "%uB platform register read\n", size);
 182         return 0;
 183     }
 184
 185     switch (addr & 0xffff) {
 186     case PLAT_FPGA_BUILD:
 187     case PLAT_CORE_CL:
 188     case PLAT_WRAPPER_CL:
 189         return 0;
 190     case PLAT_DDR3_STATUS:
 191         return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED;
 192     case PLAT_MMCM_DIV:
 193         gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000;
 194         val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT;
 195         val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT;
 196         val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT;
 197         val |= 1 << PLAT_MMCM_DIV_CLK1DIV_SHIFT;
 198         return val;
 199     case PLAT_BUILD_CFG:
 200         val = PLAT_BUILD_CFG_PCIE0_EN;
 201         val |= PLAT_BUILD_CFG_PCIE1_EN;
 202         val |= PLAT_BUILD_CFG_PCIE2_EN;
 203         return val;
 204     case PLAT_DDR_CFG:
 205         val = s->mach->ram_size / GiB;
 206         assert(!(val & ~PLAT_DDR_CFG_SIZE));
 207         val |= PLAT_DDR_CFG_MHZ;
 208         return val;
 209     default:
 210         qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx "\n",
 211                       addr & 0xffff);
 212         return 0;
 213     }
 214 }
 215
 216 static void boston_platreg_write(void *opaque, hwaddr addr,
 217                                  uint64_t val, unsigned size)
 218 {
 219     if (size != 4) {
 220         qemu_log_mask(LOG_UNIMP, "%uB platform register write\n", size);
 221         return;
 222     }
 223
 224     switch (addr & 0xffff) {
 225     case PLAT_FPGA_BUILD:
 226     case PLAT_CORE_CL:
 227     case PLAT_WRAPPER_CL:
 228     case PLAT_DDR3_STATUS:
 229     case PLAT_PCIE_STATUS:
 230     case PLAT_MMCM_DIV:
 231     case PLAT_BUILD_CFG:
 232     case PLAT_DDR_CFG:
 233         /* read only */
 234         break;
 235     case PLAT_SOFTRST_CTL:
 236         if (val & PLAT_SOFTRST_CTL_SYSRESET) {
 237             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 238         }
 239         break;
 240     default:
 241         qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx
 242                       " = 0x%" PRIx64 "\n", addr & 0xffff, val);
 243         break;
 244     }
 245 }
 246
 247 static const MemoryRegionOps boston_platreg_ops = {
 248     .read = boston_platreg_read,
 249     .write = boston_platreg_write,
 250     .endianness = DEVICE_NATIVE_ENDIAN,
 251 };
 252
 253 static const TypeInfo boston_device = {
 254     .name          = TYPE_MIPS_BOSTON,
 255     .parent        = TYPE_SYS_BUS_DEVICE,
 256     .instance_size = sizeof(BostonState),
 257 };
 258
 259 static void boston_register_types(void)
 260 {
 261     type_register_static(&boston_device);
 262 }
 263 type_init(boston_register_types)
 264
 265 static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr,
 266                          bool is_64b)
 267 {
 268     const uint32_t cm_base = 0x16100000;
 269     const uint32_t gic_base = 0x16120000;
 270     const uint32_t cpc_base = 0x16200000;
 271
 272     /* Move CM GCRs */
 273     if (is_64b) {
 274         stl_p(p++, 0x40287803);                 /* dmfc0 $8, CMGCRBase */
 275         stl_p(p++, 0x00084138);                 /* dsll $8, $8, 4 */
 276     } else {
 277         stl_p(p++, 0x40087803);                 /* mfc0 $8, CMGCRBase */
 278         stl_p(p++, 0x00084100);                 /* sll  $8, $8, 4 */
 279     }
 280     stl_p(p++, 0x3c09a000);                     /* lui  $9, 0xa000 */
 281     stl_p(p++, 0x01094025);                     /* or   $8, $9 */
 282     stl_p(p++, 0x3c0a0000 | (cm_base >> 16));   /* lui  $10, cm_base >> 16 */
 283     if (is_64b) {
 284         stl_p(p++, 0xfd0a0008);                 /* sd   $10, 0x8($8) */
 285     } else {
 286         stl_p(p++, 0xad0a0008);                 /* sw   $10, 0x8($8) */
 287     }
 288     stl_p(p++, 0x012a4025);                     /* or   $8, $10 */
 289
 290     /* Move & enable GIC GCRs */
 291     stl_p(p++, 0x3c090000 | (gic_base >> 16));  /* lui  $9, gic_base >> 16 */
 292     stl_p(p++, 0x35290001);                     /* ori  $9, 0x1 */
 293     if (is_64b) {
 294         stl_p(p++, 0xfd090080);                 /* sd   $9, 0x80($8) */
 295     } else {
 296         stl_p(p++, 0xad090080);                 /* sw   $9, 0x80($8) */
 297     }
 298
 299     /* Move & enable CPC GCRs */
 300     stl_p(p++, 0x3c090000 | (cpc_base >> 16));  /* lui  $9, cpc_base >> 16 */
 301     stl_p(p++, 0x35290001);                     /* ori  $9, 0x1 */
 302     if (is_64b) {
 303         stl_p(p++, 0xfd090088);                 /* sd   $9, 0x88($8) */
 304     } else {
 305         stl_p(p++, 0xad090088);                 /* sw   $9, 0x88($8) */
 306     }
 307
 308     /*
 309      * Setup argument registers to follow the UHI boot protocol:
 310      *
 311      * a0/$4 = -2
 312      * a1/$5 = virtual address of FDT
 313      * a2/$6 = 0
 314      * a3/$7 = 0
 315      */
 316     stl_p(p++, 0x2404fffe);                     /* li   $4, -2 */
 317                                                 /* lui  $5, hi(fdt_addr) */
 318     stl_p(p++, 0x3c050000 | ((fdt_addr >> 16) & 0xffff));
 319     if (fdt_addr & 0xffff) {                    /* ori  $5, lo(fdt_addr) */
 320         stl_p(p++, 0x34a50000 | (fdt_addr & 0xffff));
 321     }
 322     stl_p(p++, 0x34060000);                     /* li   $6, 0 */
 323     stl_p(p++, 0x34070000);                     /* li   $7, 0 */
 324
 325     /* Load kernel entry address & jump to it */
 326                                                 /* lui  $25, hi(kernel_entry) */
 327     stl_p(p++, 0x3c190000 | ((kernel_entry >> 16) & 0xffff));
 328                                                 /* ori  $25, lo(kernel_entry) */
 329     stl_p(p++, 0x37390000 | (kernel_entry & 0xffff));
 330     stl_p(p++, 0x03200009);                     /* jr   $25 */
 331 }
 332
 333 static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
 334                                      const void *match_data, hwaddr *load_addr)
 335 {
 336     BostonState *s = BOSTON(opaque);
 337     MachineState *machine = s->mach;
 338     const char *cmdline;
 339     int err;
 340     void *fdt;
 341     size_t fdt_sz, ram_low_sz, ram_high_sz;
 342
 343     fdt_sz = fdt_totalsize(fdt_orig) * 2;
 344     fdt = g_malloc0(fdt_sz);
 345
 346     err = fdt_open_into(fdt_orig, fdt, fdt_sz);
 347     if (err) {
 348         fprintf(stderr, "unable to open FDT\n");
 349         return NULL;
 350     }
 351
 352     cmdline = (machine->kernel_cmdline && machine->kernel_cmdline[0])
 353             ? machine->kernel_cmdline : " ";
 354     err = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 355     if (err < 0) {
 356         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 357         return NULL;
 358     }
 359
 360     ram_low_sz = MIN(256 * MiB, machine->ram_size);
 361     ram_high_sz = machine->ram_size - ram_low_sz;
 362     qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg",
 363                                  1, 0x00000000, 1, ram_low_sz,
 364                                  1, 0x90000000, 1, ram_high_sz);
 365
 366     fdt = g_realloc(fdt, fdt_totalsize(fdt));
 367     qemu_fdt_dumpdtb(fdt, fdt_sz);
 368
 369     s->fdt_base = *load_addr;
 370
 371     return fdt;
 372 }
 373
 374 static const void *boston_kernel_filter(void *opaque, const void *kernel,
 375                                         hwaddr *load_addr, hwaddr *entry_addr)
 376 {
 377     BostonState *s = BOSTON(opaque);
 378
 379     s->kernel_entry = *entry_addr;
 380
 381     return kernel;
 382 }
 383
 384 static const struct fit_loader_match boston_matches[] = {
 385     { "img,boston" },
 386     { NULL },
 387 };
 388
 389 static const struct fit_loader boston_fit_loader = {
 390     .matches = boston_matches,
 391     .addr_to_phys = cpu_mips_kseg0_to_phys,
 392     .fdt_filter = boston_fdt_filter,
 393     .kernel_filter = boston_kernel_filter,
 394 };
 395
 396 static inline XilinxPCIEHost *
 397 xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,
 398                  hwaddr cfg_base, uint64_t cfg_size,
 399                  hwaddr mmio_base, uint64_t mmio_size,
 400                  qemu_irq irq, bool link_up)
 401 {
 402     DeviceState *dev;
 403     MemoryRegion *cfg, *mmio;
 404
 405     dev = qdev_new(TYPE_XILINX_PCIE_HOST);
 406
 407     qdev_prop_set_uint32(dev, "bus_nr", bus_nr);
 408     qdev_prop_set_uint64(dev, "cfg_base", cfg_base);
 409     qdev_prop_set_uint64(dev, "cfg_size", cfg_size);
 410     qdev_prop_set_uint64(dev, "mmio_base", mmio_base);
 411     qdev_prop_set_uint64(dev, "mmio_size", mmio_size);
 412     qdev_prop_set_bit(dev, "link_up", link_up);
 413
 414     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 415
 416     cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 417     memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);
 418
 419     mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
 420     memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);
 421
 422     qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq);
 423
 424     return XILINX_PCIE_HOST(dev);
 425 }
 426
 427 static void boston_mach_init(MachineState *machine)
 428 {
 429     DeviceState *dev;
 430     BostonState *s;
 431     MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg;
 432     MemoryRegion *sys_mem = get_system_memory();
 433     XilinxPCIEHost *pcie2;
 434     PCIDevice *ahci;
 435     DriveInfo *hd[6];
 436     Chardev *chr;
 437     int fw_size, fit_err;
 438     bool is_64b;
 439
 440     if ((machine->ram_size % GiB) ||
 441         (machine->ram_size > (2 * GiB))) {
 442         error_report("Memory size must be 1GB or 2GB");
 443         exit(1);
 444     }
 445
 446     dev = qdev_new(TYPE_MIPS_BOSTON);
 447     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 448
 449     s = BOSTON(dev);
 450     s->mach = machine;
 451
 452     if (!cpu_supports_cps_smp(machine->cpu_type)) {
 453         error_report("Boston requires CPUs which support CPS");
 454         exit(1);
 455     }
 456
 457     is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64);
 458
 459     object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS);
 460     object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type,
 461                             &error_fatal);
 462     object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus,
 463                             &error_fatal);
 464     sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
 465
 466     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
 467
 468     flash =  g_new(MemoryRegion, 1);
 469     memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB,
 470                            &error_fatal);
 471     memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);
 472
 473     memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0);
 474
 475     ddr_low_alias = g_new(MemoryRegion, 1);
 476     memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr",
 477                              machine->ram, 0,
 478                              MIN(machine->ram_size, (256 * MiB)));
 479     memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0);
 480
 481     xilinx_pcie_init(sys_mem, 0,
 482                      0x10000000, 32 * MiB,
 483                      0x40000000, 1 * GiB,
 484                      get_cps_irq(&s->cps, 2), false);
 485
 486     xilinx_pcie_init(sys_mem, 1,
 487                      0x12000000, 32 * MiB,
 488                      0x20000000, 512 * MiB,
 489                      get_cps_irq(&s->cps, 1), false);
 490
 491     pcie2 = xilinx_pcie_init(sys_mem, 2,
 492                              0x14000000, 32 * MiB,
 493                              0x16000000, 1 * MiB,
 494                              get_cps_irq(&s->cps, 0), true);
 495
 496     platreg = g_new(MemoryRegion, 1);
 497     memory_region_init_io(platreg, NULL, &boston_platreg_ops, s,
 498                           "boston-platregs", 0x1000);
 499     memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0);
 500
 501     s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2,
 502                              get_cps_irq(&s->cps, 3), 10000000,
 503                              serial_hd(0), DEVICE_NATIVE_ENDIAN);
 504
 505     lcd = g_new(MemoryRegion, 1);
 506     memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8);
 507     memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0);
 508
 509     chr = qemu_chr_new("lcd", "vc:320x240", NULL);
 510     qemu_chr_fe_init(&s->lcd_display, chr, NULL);
 511     qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL,
 512                              boston_lcd_event, NULL, s, NULL, true);
 513
 514     ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus,
 515                                            PCI_DEVFN(0, 0),
 516                                            true, TYPE_ICH9_AHCI);
 517     g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci));
 518     ide_drive_get(hd, ahci_get_num_ports(ahci));
 519     ahci_ide_create_devs(ahci, hd);
 520
 521     if (machine->firmware) {
 522         fw_size = load_image_targphys(machine->firmware,
 523                                       0x1fc00000, 4 * MiB);
 524         if (fw_size == -1) {
 525             error_report("unable to load firmware image '%s'",
 526                           machine->firmware);
 527             exit(1);
 528         }
 529     } else if (machine->kernel_filename) {
 530         fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s);
 531         if (fit_err) {
 532             error_report("unable to load FIT image");
 533             exit(1);
 534         }
 535
 536         gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000,
 537                      s->kernel_entry, s->fdt_base, is_64b);
 538     } else if (!qtest_enabled()) {
 539         error_report("Please provide either a -kernel or -bios argument");
 540         exit(1);
 541     }
 542 }
 543
 544 static void boston_mach_class_init(MachineClass *mc)
 545 {
 546     mc->desc = "MIPS Boston";
 547     mc->init = boston_mach_init;
 548     mc->block_default_type = IF_IDE;
 549     mc->default_ram_size = 1 * GiB;
 550     mc->default_ram_id = "boston.ddr";
 551     mc->max_cpus = 16;
 552     mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400");
 553 }
 554
 555 DEFINE_MACHINE("boston", boston_mach_class_init)