hw/nvram/spapr_nvram.c

   1 /*
   2  * QEMU sPAPR NVRAM emulation
   3  *
   4  * Copyright (C) 2012 David Gibson, IBM Corporation.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/module.h"
  27 #include "qemu/units.h"
  28 #include "qapi/error.h"
  29 #include "cpu.h"
  30 #include <libfdt.h>
  31
  32 #include "sysemu/block-backend.h"
  33 #include "sysemu/device_tree.h"
  34 #include "hw/sysbus.h"
  35 #include "migration/vmstate.h"
  36 #include "hw/nvram/chrp_nvram.h"
  37 #include "hw/ppc/spapr.h"
  38 #include "hw/ppc/spapr_vio.h"
  39 #include "hw/qdev-properties.h"
  40
  41 typedef struct SpaprNvram {
  42     SpaprVioDevice sdev;
  43     uint32_t size;
  44     uint8_t *buf;
  45     BlockBackend *blk;
  46     VMChangeStateEntry *vmstate;
  47 } SpaprNvram;
  48
  49 #define TYPE_VIO_SPAPR_NVRAM "spapr-nvram"
  50 #define VIO_SPAPR_NVRAM(obj) \
  51      OBJECT_CHECK(SpaprNvram, (obj), TYPE_VIO_SPAPR_NVRAM)
  52
  53 #define MIN_NVRAM_SIZE      (8 * KiB)
  54 #define DEFAULT_NVRAM_SIZE  (64 * KiB)
  55 #define MAX_NVRAM_SIZE      (1 * MiB)
  56
  57 static void rtas_nvram_fetch(PowerPCCPU *cpu, SpaprMachineState *spapr,
  58                              uint32_t token, uint32_t nargs,
  59                              target_ulong args,
  60                              uint32_t nret, target_ulong rets)
  61 {
  62     SpaprNvram *nvram = spapr->nvram;
  63     hwaddr offset, buffer, len;
  64     void *membuf;
  65
  66     if ((nargs != 3) || (nret != 2)) {
  67         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
  68         return;
  69     }
  70
  71     if (!nvram) {
  72         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
  73         rtas_st(rets, 1, 0);
  74         return;
  75     }
  76
  77     offset = rtas_ld(args, 0);
  78     buffer = rtas_ld(args, 1);
  79     len = rtas_ld(args, 2);
  80
  81     if (((offset + len) < offset)
  82         || ((offset + len) > nvram->size)) {
  83         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
  84         rtas_st(rets, 1, 0);
  85         return;
  86     }
  87
  88     assert(nvram->buf);
  89
  90     membuf = cpu_physical_memory_map(buffer, &len, 1);
  91     memcpy(membuf, nvram->buf + offset, len);
  92     cpu_physical_memory_unmap(membuf, len, 1, len);
  93
  94     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
  95     rtas_st(rets, 1, len);
  96 }
  97
  98 static void rtas_nvram_store(PowerPCCPU *cpu, SpaprMachineState *spapr,
  99                              uint32_t token, uint32_t nargs,
 100                              target_ulong args,
 101                              uint32_t nret, target_ulong rets)
 102 {
 103     SpaprNvram *nvram = spapr->nvram;
 104     hwaddr offset, buffer, len;
 105     int alen;
 106     void *membuf;
 107
 108     if ((nargs != 3) || (nret != 2)) {
 109         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 110         return;
 111     }
 112
 113     if (!nvram) {
 114         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 115         return;
 116     }
 117
 118     offset = rtas_ld(args, 0);
 119     buffer = rtas_ld(args, 1);
 120     len = rtas_ld(args, 2);
 121
 122     if (((offset + len) < offset)
 123         || ((offset + len) > nvram->size)) {
 124         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 125         return;
 126     }
 127
 128     membuf = cpu_physical_memory_map(buffer, &len, 0);
 129
 130     alen = len;
 131     if (nvram->blk) {
 132         alen = blk_pwrite(nvram->blk, offset, membuf, len, 0);
 133     }
 134
 135     assert(nvram->buf);
 136     memcpy(nvram->buf + offset, membuf, len);
 137
 138     cpu_physical_memory_unmap(membuf, len, 0, len);
 139
 140     rtas_st(rets, 0, (alen < len) ? RTAS_OUT_HW_ERROR : RTAS_OUT_SUCCESS);
 141     rtas_st(rets, 1, (alen < 0) ? 0 : alen);
 142 }
 143
 144 static void spapr_nvram_realize(SpaprVioDevice *dev, Error **errp)
 145 {
 146     SpaprNvram *nvram = VIO_SPAPR_NVRAM(dev);
 147     int ret;
 148
 149     if (nvram->blk) {
 150         int64_t len = blk_getlength(nvram->blk);
 151
 152         if (len < 0) {
 153             error_setg_errno(errp, -len,
 154                              "could not get length of backing image");
 155             return;
 156         }
 157
 158         nvram->size = len;
 159
 160         ret = blk_set_perm(nvram->blk,
 161                            BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
 162                            BLK_PERM_ALL, errp);
 163         if (ret < 0) {
 164             return;
 165         }
 166     } else {
 167         nvram->size = DEFAULT_NVRAM_SIZE;
 168     }
 169
 170     nvram->buf = g_malloc0(nvram->size);
 171
 172     if ((nvram->size < MIN_NVRAM_SIZE) || (nvram->size > MAX_NVRAM_SIZE)) {
 173         error_setg(errp,
 174                    "spapr-nvram must be between %" PRId64
 175                    " and %" PRId64 " bytes in size",
 176                    MIN_NVRAM_SIZE, MAX_NVRAM_SIZE);
 177         return;
 178     }
 179
 180     if (nvram->blk) {
 181         int alen = blk_pread(nvram->blk, 0, nvram->buf, nvram->size);
 182
 183         if (alen != nvram->size) {
 184             error_setg(errp, "can't read spapr-nvram contents");
 185             return;
 186         }
 187     } else if (nb_prom_envs > 0) {
 188         /* Create a system partition to pass the -prom-env variables */
 189         chrp_nvram_create_system_partition(nvram->buf, MIN_NVRAM_SIZE / 4);
 190         chrp_nvram_create_free_partition(&nvram->buf[MIN_NVRAM_SIZE / 4],
 191                                          nvram->size - MIN_NVRAM_SIZE / 4);
 192     }
 193
 194     spapr_rtas_register(RTAS_NVRAM_FETCH, "nvram-fetch", rtas_nvram_fetch);
 195     spapr_rtas_register(RTAS_NVRAM_STORE, "nvram-store", rtas_nvram_store);
 196 }
 197
 198 static int spapr_nvram_devnode(SpaprVioDevice *dev, void *fdt, int node_off)
 199 {
 200     SpaprNvram *nvram = VIO_SPAPR_NVRAM(dev);
 201
 202     return fdt_setprop_cell(fdt, node_off, "#bytes", nvram->size);
 203 }
 204
 205 static int spapr_nvram_pre_load(void *opaque)
 206 {
 207     SpaprNvram *nvram = VIO_SPAPR_NVRAM(opaque);
 208
 209     g_free(nvram->buf);
 210     nvram->buf = NULL;
 211     nvram->size = 0;
 212
 213     return 0;
 214 }
 215
 216 static void postload_update_cb(void *opaque, int running, RunState state)
 217 {
 218     SpaprNvram *nvram = opaque;
 219
 220     /* This is called after bdrv_invalidate_cache_all.  */
 221
 222     qemu_del_vm_change_state_handler(nvram->vmstate);
 223     nvram->vmstate = NULL;
 224
 225     blk_pwrite(nvram->blk, 0, nvram->buf, nvram->size, 0);
 226 }
 227
 228 static int spapr_nvram_post_load(void *opaque, int version_id)
 229 {
 230     SpaprNvram *nvram = VIO_SPAPR_NVRAM(opaque);
 231
 232     if (nvram->blk) {
 233         nvram->vmstate = qemu_add_vm_change_state_handler(postload_update_cb,
 234                                                           nvram);
 235     }
 236
 237     return 0;
 238 }
 239
 240 static const VMStateDescription vmstate_spapr_nvram = {
 241     .name = "spapr_nvram",
 242     .version_id = 1,
 243     .minimum_version_id = 1,
 244     .pre_load = spapr_nvram_pre_load,
 245     .post_load = spapr_nvram_post_load,
 246     .fields = (VMStateField[]) {
 247         VMSTATE_UINT32(size, SpaprNvram),
 248         VMSTATE_VBUFFER_ALLOC_UINT32(buf, SpaprNvram, 1, NULL, size),
 249         VMSTATE_END_OF_LIST()
 250     },
 251 };
 252
 253 static Property spapr_nvram_properties[] = {
 254     DEFINE_SPAPR_PROPERTIES(SpaprNvram, sdev),
 255     DEFINE_PROP_DRIVE("drive", SpaprNvram, blk),
 256     DEFINE_PROP_END_OF_LIST(),
 257 };
 258
 259 static void spapr_nvram_class_init(ObjectClass *klass, void *data)
 260 {
 261     DeviceClass *dc = DEVICE_CLASS(klass);
 262     SpaprVioDeviceClass *k = VIO_SPAPR_DEVICE_CLASS(klass);
 263
 264     k->realize = spapr_nvram_realize;
 265     k->devnode = spapr_nvram_devnode;
 266     k->dt_name = "nvram";
 267     k->dt_type = "nvram";
 268     k->dt_compatible = "qemu,spapr-nvram";
 269     set_bit(DEVICE_CATEGORY_MISC, dc->categories);
 270     dc->props = spapr_nvram_properties;
 271     dc->vmsd = &vmstate_spapr_nvram;
 272     /* Reason: Internal device only, uses spapr_rtas_register() in realize() */
 273     dc->user_creatable = false;
 274 }
 275
 276 static const TypeInfo spapr_nvram_type_info = {
 277     .name          = TYPE_VIO_SPAPR_NVRAM,
 278     .parent        = TYPE_VIO_SPAPR_DEVICE,
 279     .instance_size = sizeof(SpaprNvram),
 280     .class_init    = spapr_nvram_class_init,
 281 };
 282
 283 static void spapr_nvram_register_types(void)
 284 {
 285     type_register_static(&spapr_nvram_type_info);
 286 }
 287
 288 type_init(spapr_nvram_register_types)