hw/sh4/r2d.c

   1 /*
   2  * Renesas SH7751R R2D-PLUS emulation
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Copyright (c) 2008 Paul Mundt
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qemu/units.h"
  28 #include "qapi/error.h"
  29 #include "cpu.h"
  30 #include "hw/sysbus.h"
  31 #include "hw/sh4/sh.h"
  32 #include "sysemu/reset.h"
  33 #include "sysemu/sysemu.h"
  34 #include "hw/boards.h"
  35 #include "hw/pci/pci.h"
  36 #include "net/net.h"
  37 #include "sh7750_regs.h"
  38 #include "hw/ide.h"
  39 #include "hw/irq.h"
  40 #include "hw/loader.h"
  41 #include "hw/usb.h"
  42 #include "hw/block/flash.h"
  43 #include "exec/address-spaces.h"
  44
  45 #define FLASH_BASE 0x00000000
  46 #define FLASH_SIZE (16 * MiB)
  47
  48 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
  49 #define SDRAM_SIZE 0x04000000
  50
  51 #define SM501_VRAM_SIZE 0x800000
  52
  53 #define BOOT_PARAMS_OFFSET 0x0010000
  54 /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
  55 #define LINUX_LOAD_OFFSET  0x0800000
  56 #define INITRD_LOAD_OFFSET 0x1800000
  57
  58 #define PA_IRLMSK       0x00
  59 #define PA_POWOFF       0x30
  60 #define PA_VERREG       0x32
  61 #define PA_OUTPORT      0x36
  62
  63 typedef struct {
  64     uint16_t bcr;
  65     uint16_t irlmsk;
  66     uint16_t irlmon;
  67     uint16_t cfctl;
  68     uint16_t cfpow;
  69     uint16_t dispctl;
  70     uint16_t sdmpow;
  71     uint16_t rtcce;
  72     uint16_t pcicd;
  73     uint16_t voyagerrts;
  74     uint16_t cfrst;
  75     uint16_t admrts;
  76     uint16_t extrst;
  77     uint16_t cfcdintclr;
  78     uint16_t keyctlclr;
  79     uint16_t pad0;
  80     uint16_t pad1;
  81     uint16_t verreg;
  82     uint16_t inport;
  83     uint16_t outport;
  84     uint16_t bverreg;
  85
  86 /* output pin */
  87     qemu_irq irl;
  88     MemoryRegion iomem;
  89 } r2d_fpga_t;
  90
  91 enum r2d_fpga_irq {
  92     PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
  93     SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
  94     NR_IRQS
  95 };
  96
  97 static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
  98     [CF_IDE]    = {  1, 1<<9 },
  99     [CF_CD]     = {  2, 1<<8 },
 100     [PCI_INTA]  = {  9, 1<<14 },
 101     [PCI_INTB]  = { 10, 1<<13 },
 102     [PCI_INTC]  = {  3, 1<<12 },
 103     [PCI_INTD]  = {  0, 1<<11 },
 104     [SM501]     = {  4, 1<<10 },
 105     [KEY]       = {  5, 1<<6 },
 106     [RTC_A]     = {  6, 1<<5 },
 107     [RTC_T]     = {  7, 1<<4 },
 108     [SDCARD]    = {  8, 1<<7 },
 109     [EXT]       = { 11, 1<<0 },
 110     [TP]        = { 12, 1<<15 },
 111 };
 112
 113 static void update_irl(r2d_fpga_t *fpga)
 114 {
 115     int i, irl = 15;
 116     for (i = 0; i < NR_IRQS; i++)
 117         if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
 118             if (irqtab[i].irl < irl)
 119                 irl = irqtab[i].irl;
 120     qemu_set_irq(fpga->irl, irl ^ 15);
 121 }
 122
 123 static void r2d_fpga_irq_set(void *opaque, int n, int level)
 124 {
 125     r2d_fpga_t *fpga = opaque;
 126     if (level)
 127         fpga->irlmon |= irqtab[n].msk;
 128     else
 129         fpga->irlmon &= ~irqtab[n].msk;
 130     update_irl(fpga);
 131 }
 132
 133 static uint64_t r2d_fpga_read(void *opaque, hwaddr addr, unsigned int size)
 134 {
 135     r2d_fpga_t *s = opaque;
 136
 137     switch (addr) {
 138     case PA_IRLMSK:
 139         return s->irlmsk;
 140     case PA_OUTPORT:
 141         return s->outport;
 142     case PA_POWOFF:
 143         return 0x00;
 144     case PA_VERREG:
 145         return 0x10;
 146     }
 147
 148     return 0;
 149 }
 150
 151 static void
 152 r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size)
 153 {
 154     r2d_fpga_t *s = opaque;
 155
 156     switch (addr) {
 157     case PA_IRLMSK:
 158         s->irlmsk = value;
 159         update_irl(s);
 160         break;
 161     case PA_OUTPORT:
 162         s->outport = value;
 163         break;
 164     case PA_POWOFF:
 165         if (value & 1) {
 166             qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 167         }
 168         break;
 169     case PA_VERREG:
 170         /* Discard writes */
 171         break;
 172     }
 173 }
 174
 175 static const MemoryRegionOps r2d_fpga_ops = {
 176     .read = r2d_fpga_read,
 177     .write = r2d_fpga_write,
 178     .impl.min_access_size = 2,
 179     .impl.max_access_size = 2,
 180     .endianness = DEVICE_NATIVE_ENDIAN,
 181 };
 182
 183 static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
 184                                hwaddr base, qemu_irq irl)
 185 {
 186     r2d_fpga_t *s;
 187
 188     s = g_malloc0(sizeof(r2d_fpga_t));
 189
 190     s->irl = irl;
 191
 192     memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40);
 193     memory_region_add_subregion(sysmem, base, &s->iomem);
 194     return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
 195 }
 196
 197 typedef struct ResetData {
 198     SuperHCPU *cpu;
 199     uint32_t vector;
 200 } ResetData;
 201
 202 static void main_cpu_reset(void *opaque)
 203 {
 204     ResetData *s = (ResetData *)opaque;
 205     CPUSH4State *env = &s->cpu->env;
 206
 207     cpu_reset(CPU(s->cpu));
 208     env->pc = s->vector;
 209 }
 210
 211 static struct QEMU_PACKED
 212 {
 213     int mount_root_rdonly;
 214     int ramdisk_flags;
 215     int orig_root_dev;
 216     int loader_type;
 217     int initrd_start;
 218     int initrd_size;
 219
 220     char pad[232];
 221
 222     char kernel_cmdline[256] QEMU_NONSTRING;
 223 } boot_params;
 224
 225 static void r2d_init(MachineState *machine)
 226 {
 227     const char *kernel_filename = machine->kernel_filename;
 228     const char *kernel_cmdline = machine->kernel_cmdline;
 229     const char *initrd_filename = machine->initrd_filename;
 230     SuperHCPU *cpu;
 231     CPUSH4State *env;
 232     ResetData *reset_info;
 233     struct SH7750State *s;
 234     MemoryRegion *sdram = g_new(MemoryRegion, 1);
 235     qemu_irq *irq;
 236     DriveInfo *dinfo;
 237     int i;
 238     DeviceState *dev;
 239     SysBusDevice *busdev;
 240     MemoryRegion *address_space_mem = get_system_memory();
 241     PCIBus *pci_bus;
 242
 243     cpu = SUPERH_CPU(cpu_create(machine->cpu_type));
 244     env = &cpu->env;
 245
 246     reset_info = g_malloc0(sizeof(ResetData));
 247     reset_info->cpu = cpu;
 248     reset_info->vector = env->pc;
 249     qemu_register_reset(main_cpu_reset, reset_info);
 250
 251     /* Allocate memory space */
 252     memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE, &error_fatal);
 253     memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
 254     /* Register peripherals */
 255     s = sh7750_init(cpu, address_space_mem);
 256     irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
 257
 258     dev = qdev_create(NULL, "sh_pci");
 259     busdev = SYS_BUS_DEVICE(dev);
 260     qdev_init_nofail(dev);
 261     pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
 262     sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
 263     sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
 264     sysbus_connect_irq(busdev, 0, irq[PCI_INTA]);
 265     sysbus_connect_irq(busdev, 1, irq[PCI_INTB]);
 266     sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
 267     sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);
 268
 269     dev = qdev_create(NULL, "sysbus-sm501");
 270     busdev = SYS_BUS_DEVICE(dev);
 271     qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE);
 272     qdev_prop_set_uint32(dev, "base", 0x10000000);
 273     qdev_prop_set_ptr(dev, "chr-state", serial_hd(2));
 274     qdev_init_nofail(dev);
 275     sysbus_mmio_map(busdev, 0, 0x10000000);
 276     sysbus_mmio_map(busdev, 1, 0x13e00000);
 277     sysbus_connect_irq(busdev, 0, irq[SM501]);
 278
 279     /* onboard CF (True IDE mode, Master only). */
 280     dinfo = drive_get(IF_IDE, 0, 0);
 281     dev = qdev_create(NULL, "mmio-ide");
 282     busdev = SYS_BUS_DEVICE(dev);
 283     sysbus_connect_irq(busdev, 0, irq[CF_IDE]);
 284     qdev_prop_set_uint32(dev, "shift", 1);
 285     qdev_init_nofail(dev);
 286     sysbus_mmio_map(busdev, 0, 0x14001000);
 287     sysbus_mmio_map(busdev, 1, 0x1400080c);
 288     mmio_ide_init_drives(dev, dinfo, NULL);
 289
 290     /*
 291      * Onboard flash memory
 292      * According to the old board user document in Japanese (under
 293      * NDA) what is referred to as FROM (Area0) is connected via a
 294      * 32-bit bus and CS0 to CN8. The docs mention a Cypress
 295      * S29PL127J60TFI130 chipsset.  Per the 'S29PL-J 002-00615
 296      * Rev. *E' datasheet, it is a 128Mbit NOR parallel flash
 297      * addressable in words of 16bit.
 298      */
 299     dinfo = drive_get(IF_PFLASH, 0, 0);
 300     pflash_cfi02_register(0x0, "r2d.flash", FLASH_SIZE,
 301                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 302                           64 * KiB, 1, 2, 0x0001, 0x227e, 0x2220, 0x2200,
 303                           0x555, 0x2aa, 0);
 304
 305     /* NIC: rtl8139 on-board, and 2 slots. */
 306     for (i = 0; i < nb_nics; i++)
 307         pci_nic_init_nofail(&nd_table[i], pci_bus,
 308                             "rtl8139", i==0 ? "2" : NULL);
 309
 310     /* USB keyboard */
 311     usb_create_simple(usb_bus_find(-1), "usb-kbd");
 312
 313     /* Todo: register on board registers */
 314     memset(&boot_params, 0, sizeof(boot_params));
 315
 316     if (kernel_filename) {
 317         int kernel_size;
 318
 319         kernel_size = load_image_targphys(kernel_filename,
 320                                           SDRAM_BASE + LINUX_LOAD_OFFSET,
 321                                           INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
 322         if (kernel_size < 0) {
 323           fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
 324           exit(1);
 325         }
 326
 327         /* initialization which should be done by firmware */
 328         address_space_stl(&address_space_memory, SH7750_BCR1, 1 << 3,
 329                           MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 SDRAM */
 330         address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2),
 331                           MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 32bit */
 332         reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
 333     }
 334
 335     if (initrd_filename) {
 336         int initrd_size;
 337
 338         initrd_size = load_image_targphys(initrd_filename,
 339                                           SDRAM_BASE + INITRD_LOAD_OFFSET,
 340                                           SDRAM_SIZE - INITRD_LOAD_OFFSET);
 341
 342         if (initrd_size < 0) {
 343           fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
 344           exit(1);
 345         }
 346
 347         /* initialization which should be done by firmware */
 348         boot_params.loader_type = tswap32(1);
 349         boot_params.initrd_start = tswap32(INITRD_LOAD_OFFSET);
 350         boot_params.initrd_size = tswap32(initrd_size);
 351     }
 352
 353     if (kernel_cmdline) {
 354         /* I see no evidence that this .kernel_cmdline buffer requires
 355            NUL-termination, so using strncpy should be ok. */
 356         strncpy(boot_params.kernel_cmdline, kernel_cmdline,
 357                 sizeof(boot_params.kernel_cmdline));
 358     }
 359
 360     rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
 361                        SDRAM_BASE + BOOT_PARAMS_OFFSET);
 362 }
 363
 364 static void r2d_machine_init(MachineClass *mc)
 365 {
 366     mc->desc = "r2d-plus board";
 367     mc->init = r2d_init;
 368     mc->block_default_type = IF_IDE;
 369     mc->default_cpu_type = TYPE_SH7751R_CPU;
 370 }
 371
 372 DEFINE_MACHINE("r2d", r2d_machine_init)