hw/sh4/sh_pci.c

   1 /*
   2  * SuperH on-chip PCIC emulation.
   3  *
   4  * Copyright (c) 2008 Takashi YOSHII
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sysbus.h"
  27 #include "hw/sh4/sh.h"
  28 #include "hw/irq.h"
  29 #include "hw/pci/pci.h"
  30 #include "hw/pci/pci_host.h"
  31 #include "qemu/bswap.h"
  32 #include "qemu/module.h"
  33 #include "exec/address-spaces.h"
  34 #include "qom/object.h"
  35
  36 #define TYPE_SH_PCI_HOST_BRIDGE "sh_pci"
  37
  38 typedef struct SHPCIState SHPCIState;
  39 #define SH_PCI_HOST_BRIDGE(obj) \
  40     OBJECT_CHECK(SHPCIState, (obj), TYPE_SH_PCI_HOST_BRIDGE)
  41
  42 struct SHPCIState {
  43     PCIHostState parent_obj;
  44
  45     PCIDevice *dev;
  46     qemu_irq irq[4];
  47     MemoryRegion memconfig_p4;
  48     MemoryRegion memconfig_a7;
  49     MemoryRegion isa;
  50     uint32_t par;
  51     uint32_t mbr;
  52     uint32_t iobr;
  53 };
  54
  55 static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val,
  56                               unsigned size)
  57 {
  58     SHPCIState *pcic = p;
  59     PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
  60
  61     switch(addr) {
  62     case 0 ... 0xfc:
  63         stl_le_p(pcic->dev->config + addr, val);
  64         break;
  65     case 0x1c0:
  66         pcic->par = val;
  67         break;
  68     case 0x1c4:
  69         pcic->mbr = val & 0xff000001;
  70         break;
  71     case 0x1c8:
  72         pcic->iobr = val & 0xfffc0001;
  73         memory_region_set_alias_offset(&pcic->isa, val & 0xfffc0000);
  74         break;
  75     case 0x220:
  76         pci_data_write(phb->bus, pcic->par, val, 4);
  77         break;
  78     }
  79 }
  80
  81 static uint64_t sh_pci_reg_read (void *p, hwaddr addr,
  82                                  unsigned size)
  83 {
  84     SHPCIState *pcic = p;
  85     PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
  86
  87     switch(addr) {
  88     case 0 ... 0xfc:
  89         return ldl_le_p(pcic->dev->config + addr);
  90     case 0x1c0:
  91         return pcic->par;
  92     case 0x1c4:
  93         return pcic->mbr;
  94     case 0x1c8:
  95         return pcic->iobr;
  96     case 0x220:
  97         return pci_data_read(phb->bus, pcic->par, 4);
  98     }
  99     return 0;
 100 }
 101
 102 static const MemoryRegionOps sh_pci_reg_ops = {
 103     .read = sh_pci_reg_read,
 104     .write = sh_pci_reg_write,
 105     .endianness = DEVICE_NATIVE_ENDIAN,
 106     .valid = {
 107         .min_access_size = 4,
 108         .max_access_size = 4,
 109     },
 110 };
 111
 112 static int sh_pci_map_irq(PCIDevice *d, int irq_num)
 113 {
 114     return (d->devfn >> 3);
 115 }
 116
 117 static void sh_pci_set_irq(void *opaque, int irq_num, int level)
 118 {
 119     qemu_irq *pic = opaque;
 120
 121     qemu_set_irq(pic[irq_num], level);
 122 }
 123
 124 static void sh_pci_device_realize(DeviceState *dev, Error **errp)
 125 {
 126     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 127     SHPCIState *s = SH_PCI_HOST_BRIDGE(dev);
 128     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 129     int i;
 130
 131     for (i = 0; i < 4; i++) {
 132         sysbus_init_irq(sbd, &s->irq[i]);
 133     }
 134     phb->bus = pci_register_root_bus(dev, "pci",
 135                                      sh_pci_set_irq, sh_pci_map_irq,
 136                                      s->irq,
 137                                      get_system_memory(),
 138                                      get_system_io(),
 139                                      PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS);
 140     memory_region_init_io(&s->memconfig_p4, OBJECT(s), &sh_pci_reg_ops, s,
 141                           "sh_pci", 0x224);
 142     memory_region_init_alias(&s->memconfig_a7, OBJECT(s), "sh_pci.2",
 143                              &s->memconfig_p4, 0, 0x224);
 144     memory_region_init_alias(&s->isa, OBJECT(s), "sh_pci.isa",
 145                              get_system_io(), 0, 0x40000);
 146     sysbus_init_mmio(sbd, &s->memconfig_p4);
 147     sysbus_init_mmio(sbd, &s->memconfig_a7);
 148     memory_region_add_subregion(get_system_memory(), 0xfe240000, &s->isa);
 149
 150     s->dev = pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "sh_pci_host");
 151 }
 152
 153 static void sh_pci_host_realize(PCIDevice *d, Error **errp)
 154 {
 155     pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT);
 156     pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST |
 157                  PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
 158 }
 159
 160 static void sh_pci_host_class_init(ObjectClass *klass, void *data)
 161 {
 162     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 163     DeviceClass *dc = DEVICE_CLASS(klass);
 164
 165     k->realize = sh_pci_host_realize;
 166     k->vendor_id = PCI_VENDOR_ID_HITACHI;
 167     k->device_id = PCI_DEVICE_ID_HITACHI_SH7751R;
 168     /*
 169      * PCI-facing part of the host bridge, not usable without the
 170      * host-facing part, which can't be device_add'ed, yet.
 171      */
 172     dc->user_creatable = false;
 173 }
 174
 175 static const TypeInfo sh_pci_host_info = {
 176     .name          = "sh_pci_host",
 177     .parent        = TYPE_PCI_DEVICE,
 178     .instance_size = sizeof(PCIDevice),
 179     .class_init    = sh_pci_host_class_init,
 180     .interfaces = (InterfaceInfo[]) {
 181         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 182         { },
 183     },
 184 };
 185
 186 static void sh_pci_device_class_init(ObjectClass *klass, void *data)
 187 {
 188     DeviceClass *dc = DEVICE_CLASS(klass);
 189
 190     dc->realize = sh_pci_device_realize;
 191 }
 192
 193 static const TypeInfo sh_pci_device_info = {
 194     .name          = TYPE_SH_PCI_HOST_BRIDGE,
 195     .parent        = TYPE_PCI_HOST_BRIDGE,
 196     .instance_size = sizeof(SHPCIState),
 197     .class_init    = sh_pci_device_class_init,
 198 };
 199
 200 static void sh_pci_register_types(void)
 201 {
 202     type_register_static(&sh_pci_device_info);
 203     type_register_static(&sh_pci_host_info);
 204 }
 205
 206 type_init(sh_pci_register_types)