hw/timer/altera_timer.c

   1 /*
   2  * QEMU model of the Altera timer.
   3  *
   4  * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/module.h"
  23 #include "qapi/error.h"
  24
  25 #include "hw/sysbus.h"
  26 #include "hw/irq.h"
  27 #include "hw/ptimer.h"
  28 #include "hw/qdev-properties.h"
  29 #include "qom/object.h"
  30
  31 #define R_STATUS      0
  32 #define R_CONTROL     1
  33 #define R_PERIODL     2
  34 #define R_PERIODH     3
  35 #define R_SNAPL       4
  36 #define R_SNAPH       5
  37 #define R_MAX         6
  38
  39 #define STATUS_TO     0x0001
  40 #define STATUS_RUN    0x0002
  41
  42 #define CONTROL_ITO   0x0001
  43 #define CONTROL_CONT  0x0002
  44 #define CONTROL_START 0x0004
  45 #define CONTROL_STOP  0x0008
  46
  47 #define TYPE_ALTERA_TIMER "ALTR.timer"
  48 typedef struct AlteraTimer AlteraTimer;
  49 #define ALTERA_TIMER(obj) \
  50     OBJECT_CHECK(AlteraTimer, (obj), TYPE_ALTERA_TIMER)
  51
  52 struct AlteraTimer {
  53     SysBusDevice  busdev;
  54     MemoryRegion  mmio;
  55     qemu_irq      irq;
  56     uint32_t      freq_hz;
  57     ptimer_state *ptimer;
  58     uint32_t      regs[R_MAX];
  59 };
  60
  61 static int timer_irq_state(AlteraTimer *t)
  62 {
  63     bool irq = (t->regs[R_STATUS] & STATUS_TO) &&
  64                (t->regs[R_CONTROL] & CONTROL_ITO);
  65     return irq;
  66 }
  67
  68 static uint64_t timer_read(void *opaque, hwaddr addr,
  69                            unsigned int size)
  70 {
  71     AlteraTimer *t = opaque;
  72     uint64_t r = 0;
  73
  74     addr >>= 2;
  75
  76     switch (addr) {
  77     case R_CONTROL:
  78         r = t->regs[R_CONTROL] & (CONTROL_ITO | CONTROL_CONT);
  79         break;
  80
  81     default:
  82         if (addr < ARRAY_SIZE(t->regs)) {
  83             r = t->regs[addr];
  84         }
  85         break;
  86     }
  87
  88     return r;
  89 }
  90
  91 static void timer_write(void *opaque, hwaddr addr,
  92                         uint64_t value, unsigned int size)
  93 {
  94     AlteraTimer *t = opaque;
  95     uint64_t tvalue;
  96     uint32_t count = 0;
  97     int irqState = timer_irq_state(t);
  98
  99     addr >>= 2;
 100
 101     switch (addr) {
 102     case R_STATUS:
 103         /* The timeout bit is cleared by writing the status register. */
 104         t->regs[R_STATUS] &= ~STATUS_TO;
 105         break;
 106
 107     case R_CONTROL:
 108         ptimer_transaction_begin(t->ptimer);
 109         t->regs[R_CONTROL] = value & (CONTROL_ITO | CONTROL_CONT);
 110         if ((value & CONTROL_START) &&
 111             !(t->regs[R_STATUS] & STATUS_RUN)) {
 112             ptimer_run(t->ptimer, 1);
 113             t->regs[R_STATUS] |= STATUS_RUN;
 114         }
 115         if ((value & CONTROL_STOP) && (t->regs[R_STATUS] & STATUS_RUN)) {
 116             ptimer_stop(t->ptimer);
 117             t->regs[R_STATUS] &= ~STATUS_RUN;
 118         }
 119         ptimer_transaction_commit(t->ptimer);
 120         break;
 121
 122     case R_PERIODL:
 123     case R_PERIODH:
 124         ptimer_transaction_begin(t->ptimer);
 125         t->regs[addr] = value & 0xFFFF;
 126         if (t->regs[R_STATUS] & STATUS_RUN) {
 127             ptimer_stop(t->ptimer);
 128             t->regs[R_STATUS] &= ~STATUS_RUN;
 129         }
 130         tvalue = (t->regs[R_PERIODH] << 16) | t->regs[R_PERIODL];
 131         ptimer_set_limit(t->ptimer, tvalue + 1, 1);
 132         ptimer_transaction_commit(t->ptimer);
 133         break;
 134
 135     case R_SNAPL:
 136     case R_SNAPH:
 137         count = ptimer_get_count(t->ptimer);
 138         t->regs[R_SNAPL] = count & 0xFFFF;
 139         t->regs[R_SNAPH] = count >> 16;
 140         break;
 141
 142     default:
 143         break;
 144     }
 145
 146     if (irqState != timer_irq_state(t)) {
 147         qemu_set_irq(t->irq, timer_irq_state(t));
 148     }
 149 }
 150
 151 static const MemoryRegionOps timer_ops = {
 152     .read = timer_read,
 153     .write = timer_write,
 154     .endianness = DEVICE_NATIVE_ENDIAN,
 155     .valid = {
 156         .min_access_size = 1,
 157         .max_access_size = 4
 158     }
 159 };
 160
 161 static void timer_hit(void *opaque)
 162 {
 163     AlteraTimer *t = opaque;
 164     const uint64_t tvalue = (t->regs[R_PERIODH] << 16) | t->regs[R_PERIODL];
 165
 166     t->regs[R_STATUS] |= STATUS_TO;
 167
 168     ptimer_set_limit(t->ptimer, tvalue + 1, 1);
 169
 170     if (!(t->regs[R_CONTROL] & CONTROL_CONT)) {
 171         t->regs[R_STATUS] &= ~STATUS_RUN;
 172         ptimer_set_count(t->ptimer, tvalue);
 173     } else {
 174         ptimer_run(t->ptimer, 1);
 175     }
 176
 177     qemu_set_irq(t->irq, timer_irq_state(t));
 178 }
 179
 180 static void altera_timer_realize(DeviceState *dev, Error **errp)
 181 {
 182     AlteraTimer *t = ALTERA_TIMER(dev);
 183     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 184
 185     if (t->freq_hz == 0) {
 186         error_setg(errp, "\"clock-frequency\" property must be provided.");
 187         return;
 188     }
 189
 190     t->ptimer = ptimer_init(timer_hit, t, PTIMER_POLICY_DEFAULT);
 191     ptimer_transaction_begin(t->ptimer);
 192     ptimer_set_freq(t->ptimer, t->freq_hz);
 193     ptimer_transaction_commit(t->ptimer);
 194
 195     memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
 196                           TYPE_ALTERA_TIMER, R_MAX * sizeof(uint32_t));
 197     sysbus_init_mmio(sbd, &t->mmio);
 198 }
 199
 200 static void altera_timer_init(Object *obj)
 201 {
 202     AlteraTimer *t = ALTERA_TIMER(obj);
 203     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 204
 205     sysbus_init_irq(sbd, &t->irq);
 206 }
 207
 208 static void altera_timer_reset(DeviceState *dev)
 209 {
 210     AlteraTimer *t = ALTERA_TIMER(dev);
 211
 212     ptimer_transaction_begin(t->ptimer);
 213     ptimer_stop(t->ptimer);
 214     ptimer_set_limit(t->ptimer, 0xffffffff, 1);
 215     ptimer_transaction_commit(t->ptimer);
 216     memset(t->regs, 0, sizeof(t->regs));
 217 }
 218
 219 static Property altera_timer_properties[] = {
 220     DEFINE_PROP_UINT32("clock-frequency", AlteraTimer, freq_hz, 0),
 221     DEFINE_PROP_END_OF_LIST(),
 222 };
 223
 224 static void altera_timer_class_init(ObjectClass *klass, void *data)
 225 {
 226     DeviceClass *dc = DEVICE_CLASS(klass);
 227
 228     dc->realize = altera_timer_realize;
 229     device_class_set_props(dc, altera_timer_properties);
 230     dc->reset = altera_timer_reset;
 231 }
 232
 233 static const TypeInfo altera_timer_info = {
 234     .name          = TYPE_ALTERA_TIMER,
 235     .parent        = TYPE_SYS_BUS_DEVICE,
 236     .instance_size = sizeof(AlteraTimer),
 237     .instance_init = altera_timer_init,
 238     .class_init    = altera_timer_class_init,
 239 };
 240
 241 static void altera_timer_register(void)
 242 {
 243     type_register_static(&altera_timer_info);
 244 }
 245
 246 type_init(altera_timer_register)