hw/timer/lm32_timer.c

   1 /*
   2  *  QEMU model of the LatticeMico32 timer block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.latticesemi.com/documents/mico32timer.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "hw/irq.h"
  26 #include "hw/sysbus.h"
  27 #include "migration/vmstate.h"
  28 #include "trace.h"
  29 #include "qemu/timer.h"
  30 #include "hw/ptimer.h"
  31 #include "hw/qdev-properties.h"
  32 #include "qemu/error-report.h"
  33 #include "qemu/module.h"
  34 #include "qom/object.h"
  35
  36 #define DEFAULT_FREQUENCY (50*1000000)
  37
  38 enum {
  39     R_SR = 0,
  40     R_CR,
  41     R_PERIOD,
  42     R_SNAPSHOT,
  43     R_MAX
  44 };
  45
  46 enum {
  47     SR_TO    = (1 << 0),
  48     SR_RUN   = (1 << 1),
  49 };
  50
  51 enum {
  52     CR_ITO   = (1 << 0),
  53     CR_CONT  = (1 << 1),
  54     CR_START = (1 << 2),
  55     CR_STOP  = (1 << 3),
  56 };
  57
  58 #define TYPE_LM32_TIMER "lm32-timer"
  59 typedef struct LM32TimerState LM32TimerState;
  60 #define LM32_TIMER(obj) OBJECT_CHECK(LM32TimerState, (obj), TYPE_LM32_TIMER)
  61
  62 struct LM32TimerState {
  63     SysBusDevice parent_obj;
  64
  65     MemoryRegion iomem;
  66
  67     ptimer_state *ptimer;
  68
  69     qemu_irq irq;
  70     uint32_t freq_hz;
  71
  72     uint32_t regs[R_MAX];
  73 };
  74
  75 static void timer_update_irq(LM32TimerState *s)
  76 {
  77     int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO);
  78
  79     trace_lm32_timer_irq_state(state);
  80     qemu_set_irq(s->irq, state);
  81 }
  82
  83 static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
  84 {
  85     LM32TimerState *s = opaque;
  86     uint32_t r = 0;
  87
  88     addr >>= 2;
  89     switch (addr) {
  90     case R_SR:
  91     case R_CR:
  92     case R_PERIOD:
  93         r = s->regs[addr];
  94         break;
  95     case R_SNAPSHOT:
  96         r = (uint32_t)ptimer_get_count(s->ptimer);
  97         break;
  98     default:
  99         error_report("lm32_timer: read access to unknown register 0x"
 100                 TARGET_FMT_plx, addr << 2);
 101         break;
 102     }
 103
 104     trace_lm32_timer_memory_read(addr << 2, r);
 105     return r;
 106 }
 107
 108 static void timer_write(void *opaque, hwaddr addr,
 109                         uint64_t value, unsigned size)
 110 {
 111     LM32TimerState *s = opaque;
 112
 113     trace_lm32_timer_memory_write(addr, value);
 114
 115     addr >>= 2;
 116     switch (addr) {
 117     case R_SR:
 118         s->regs[R_SR] &= ~SR_TO;
 119         break;
 120     case R_CR:
 121         ptimer_transaction_begin(s->ptimer);
 122         s->regs[R_CR] = value;
 123         if (s->regs[R_CR] & CR_START) {
 124             ptimer_run(s->ptimer, 1);
 125         }
 126         if (s->regs[R_CR] & CR_STOP) {
 127             ptimer_stop(s->ptimer);
 128         }
 129         ptimer_transaction_commit(s->ptimer);
 130         break;
 131     case R_PERIOD:
 132         s->regs[R_PERIOD] = value;
 133         ptimer_transaction_begin(s->ptimer);
 134         ptimer_set_count(s->ptimer, value);
 135         ptimer_transaction_commit(s->ptimer);
 136         break;
 137     case R_SNAPSHOT:
 138         error_report("lm32_timer: write access to read only register 0x"
 139                 TARGET_FMT_plx, addr << 2);
 140         break;
 141     default:
 142         error_report("lm32_timer: write access to unknown register 0x"
 143                 TARGET_FMT_plx, addr << 2);
 144         break;
 145     }
 146     timer_update_irq(s);
 147 }
 148
 149 static const MemoryRegionOps timer_ops = {
 150     .read = timer_read,
 151     .write = timer_write,
 152     .endianness = DEVICE_NATIVE_ENDIAN,
 153     .valid = {
 154         .min_access_size = 4,
 155         .max_access_size = 4,
 156     },
 157 };
 158
 159 static void timer_hit(void *opaque)
 160 {
 161     LM32TimerState *s = opaque;
 162
 163     trace_lm32_timer_hit();
 164
 165     s->regs[R_SR] |= SR_TO;
 166
 167     if (s->regs[R_CR] & CR_CONT) {
 168         ptimer_set_count(s->ptimer, s->regs[R_PERIOD]);
 169         ptimer_run(s->ptimer, 1);
 170     }
 171     timer_update_irq(s);
 172 }
 173
 174 static void timer_reset(DeviceState *d)
 175 {
 176     LM32TimerState *s = LM32_TIMER(d);
 177     int i;
 178
 179     for (i = 0; i < R_MAX; i++) {
 180         s->regs[i] = 0;
 181     }
 182     ptimer_transaction_begin(s->ptimer);
 183     ptimer_stop(s->ptimer);
 184     ptimer_transaction_commit(s->ptimer);
 185 }
 186
 187 static void lm32_timer_init(Object *obj)
 188 {
 189     LM32TimerState *s = LM32_TIMER(obj);
 190     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 191
 192     sysbus_init_irq(dev, &s->irq);
 193
 194     memory_region_init_io(&s->iomem, obj, &timer_ops, s,
 195                           "timer", R_MAX * 4);
 196     sysbus_init_mmio(dev, &s->iomem);
 197 }
 198
 199 static void lm32_timer_realize(DeviceState *dev, Error **errp)
 200 {
 201     LM32TimerState *s = LM32_TIMER(dev);
 202
 203     s->ptimer = ptimer_init(timer_hit, s, PTIMER_POLICY_DEFAULT);
 204
 205     ptimer_transaction_begin(s->ptimer);
 206     ptimer_set_freq(s->ptimer, s->freq_hz);
 207     ptimer_transaction_commit(s->ptimer);
 208 }
 209
 210 static const VMStateDescription vmstate_lm32_timer = {
 211     .name = "lm32-timer",
 212     .version_id = 1,
 213     .minimum_version_id = 1,
 214     .fields = (VMStateField[]) {
 215         VMSTATE_PTIMER(ptimer, LM32TimerState),
 216         VMSTATE_UINT32(freq_hz, LM32TimerState),
 217         VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX),
 218         VMSTATE_END_OF_LIST()
 219     }
 220 };
 221
 222 static Property lm32_timer_properties[] = {
 223     DEFINE_PROP_UINT32("frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY),
 224     DEFINE_PROP_END_OF_LIST(),
 225 };
 226
 227 static void lm32_timer_class_init(ObjectClass *klass, void *data)
 228 {
 229     DeviceClass *dc = DEVICE_CLASS(klass);
 230
 231     dc->realize = lm32_timer_realize;
 232     dc->reset = timer_reset;
 233     dc->vmsd = &vmstate_lm32_timer;
 234     device_class_set_props(dc, lm32_timer_properties);
 235 }
 236
 237 static const TypeInfo lm32_timer_info = {
 238     .name          = TYPE_LM32_TIMER,
 239     .parent        = TYPE_SYS_BUS_DEVICE,
 240     .instance_size = sizeof(LM32TimerState),
 241     .instance_init = lm32_timer_init,
 242     .class_init    = lm32_timer_class_init,
 243 };
 244
 245 static void lm32_timer_register_types(void)
 246 {
 247     type_register_static(&lm32_timer_info);
 248 }
 249
 250 type_init(lm32_timer_register_types)