hw/timer/lm32_timer.c

   1 /*
   2  *  QEMU model of the LatticeMico32 timer block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.latticesemi.com/documents/mico32timer.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "hw/irq.h"
  26 #include "hw/sysbus.h"
  27 #include "migration/vmstate.h"
  28 #include "trace.h"
  29 #include "qemu/timer.h"
  30 #include "hw/ptimer.h"
  31 #include "qemu/error-report.h"
  32 #include "qemu/main-loop.h"
  33 #include "qemu/module.h"
  34
  35 #define DEFAULT_FREQUENCY (50*1000000)
  36
  37 enum {
  38     R_SR = 0,
  39     R_CR,
  40     R_PERIOD,
  41     R_SNAPSHOT,
  42     R_MAX
  43 };
  44
  45 enum {
  46     SR_TO    = (1 << 0),
  47     SR_RUN   = (1 << 1),
  48 };
  49
  50 enum {
  51     CR_ITO   = (1 << 0),
  52     CR_CONT  = (1 << 1),
  53     CR_START = (1 << 2),
  54     CR_STOP  = (1 << 3),
  55 };
  56
  57 #define TYPE_LM32_TIMER "lm32-timer"
  58 #define LM32_TIMER(obj) OBJECT_CHECK(LM32TimerState, (obj), TYPE_LM32_TIMER)
  59
  60 struct LM32TimerState {
  61     SysBusDevice parent_obj;
  62
  63     MemoryRegion iomem;
  64
  65     QEMUBH *bh;
  66     ptimer_state *ptimer;
  67
  68     qemu_irq irq;
  69     uint32_t freq_hz;
  70
  71     uint32_t regs[R_MAX];
  72 };
  73 typedef struct LM32TimerState LM32TimerState;
  74
  75 static void timer_update_irq(LM32TimerState *s)
  76 {
  77     int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO);
  78
  79     trace_lm32_timer_irq_state(state);
  80     qemu_set_irq(s->irq, state);
  81 }
  82
  83 static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
  84 {
  85     LM32TimerState *s = opaque;
  86     uint32_t r = 0;
  87
  88     addr >>= 2;
  89     switch (addr) {
  90     case R_SR:
  91     case R_CR:
  92     case R_PERIOD:
  93         r = s->regs[addr];
  94         break;
  95     case R_SNAPSHOT:
  96         r = (uint32_t)ptimer_get_count(s->ptimer);
  97         break;
  98     default:
  99         error_report("lm32_timer: read access to unknown register 0x"
 100                 TARGET_FMT_plx, addr << 2);
 101         break;
 102     }
 103
 104     trace_lm32_timer_memory_read(addr << 2, r);
 105     return r;
 106 }
 107
 108 static void timer_write(void *opaque, hwaddr addr,
 109                         uint64_t value, unsigned size)
 110 {
 111     LM32TimerState *s = opaque;
 112
 113     trace_lm32_timer_memory_write(addr, value);
 114
 115     addr >>= 2;
 116     switch (addr) {
 117     case R_SR:
 118         s->regs[R_SR] &= ~SR_TO;
 119         break;
 120     case R_CR:
 121         s->regs[R_CR] = value;
 122         if (s->regs[R_CR] & CR_START) {
 123             ptimer_run(s->ptimer, 1);
 124         }
 125         if (s->regs[R_CR] & CR_STOP) {
 126             ptimer_stop(s->ptimer);
 127         }
 128         break;
 129     case R_PERIOD:
 130         s->regs[R_PERIOD] = value;
 131         ptimer_set_count(s->ptimer, value);
 132         break;
 133     case R_SNAPSHOT:
 134         error_report("lm32_timer: write access to read only register 0x"
 135                 TARGET_FMT_plx, addr << 2);
 136         break;
 137     default:
 138         error_report("lm32_timer: write access to unknown register 0x"
 139                 TARGET_FMT_plx, addr << 2);
 140         break;
 141     }
 142     timer_update_irq(s);
 143 }
 144
 145 static const MemoryRegionOps timer_ops = {
 146     .read = timer_read,
 147     .write = timer_write,
 148     .endianness = DEVICE_NATIVE_ENDIAN,
 149     .valid = {
 150         .min_access_size = 4,
 151         .max_access_size = 4,
 152     },
 153 };
 154
 155 static void timer_hit(void *opaque)
 156 {
 157     LM32TimerState *s = opaque;
 158
 159     trace_lm32_timer_hit();
 160
 161     s->regs[R_SR] |= SR_TO;
 162
 163     if (s->regs[R_CR] & CR_CONT) {
 164         ptimer_set_count(s->ptimer, s->regs[R_PERIOD]);
 165         ptimer_run(s->ptimer, 1);
 166     }
 167     timer_update_irq(s);
 168 }
 169
 170 static void timer_reset(DeviceState *d)
 171 {
 172     LM32TimerState *s = LM32_TIMER(d);
 173     int i;
 174
 175     for (i = 0; i < R_MAX; i++) {
 176         s->regs[i] = 0;
 177     }
 178     ptimer_stop(s->ptimer);
 179 }
 180
 181 static void lm32_timer_init(Object *obj)
 182 {
 183     LM32TimerState *s = LM32_TIMER(obj);
 184     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 185
 186     sysbus_init_irq(dev, &s->irq);
 187
 188     s->bh = qemu_bh_new(timer_hit, s);
 189     s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT);
 190
 191     memory_region_init_io(&s->iomem, obj, &timer_ops, s,
 192                           "timer", R_MAX * 4);
 193     sysbus_init_mmio(dev, &s->iomem);
 194 }
 195
 196 static void lm32_timer_realize(DeviceState *dev, Error **errp)
 197 {
 198     LM32TimerState *s = LM32_TIMER(dev);
 199
 200     ptimer_set_freq(s->ptimer, s->freq_hz);
 201 }
 202
 203 static const VMStateDescription vmstate_lm32_timer = {
 204     .name = "lm32-timer",
 205     .version_id = 1,
 206     .minimum_version_id = 1,
 207     .fields = (VMStateField[]) {
 208         VMSTATE_PTIMER(ptimer, LM32TimerState),
 209         VMSTATE_UINT32(freq_hz, LM32TimerState),
 210         VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX),
 211         VMSTATE_END_OF_LIST()
 212     }
 213 };
 214
 215 static Property lm32_timer_properties[] = {
 216     DEFINE_PROP_UINT32("frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY),
 217     DEFINE_PROP_END_OF_LIST(),
 218 };
 219
 220 static void lm32_timer_class_init(ObjectClass *klass, void *data)
 221 {
 222     DeviceClass *dc = DEVICE_CLASS(klass);
 223
 224     dc->realize = lm32_timer_realize;
 225     dc->reset = timer_reset;
 226     dc->vmsd = &vmstate_lm32_timer;
 227     dc->props = lm32_timer_properties;
 228 }
 229
 230 static const TypeInfo lm32_timer_info = {
 231     .name          = TYPE_LM32_TIMER,
 232     .parent        = TYPE_SYS_BUS_DEVICE,
 233     .instance_size = sizeof(LM32TimerState),
 234     .instance_init = lm32_timer_init,
 235     .class_init    = lm32_timer_class_init,
 236 };
 237
 238 static void lm32_timer_register_types(void)
 239 {
 240     type_register_static(&lm32_timer_info);
 241 }
 242
 243 type_init(lm32_timer_register_types)