hw/timer/pl031.c

   1 /*
   2  * ARM AMBA PrimeCell PL031 RTC
   3  *
   4  * Copyright (c) 2007 CodeSourcery
   5  *
   6  * This file is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Contributions after 2012-01-13 are licensed under the terms of the
  11  * GNU GPL, version 2 or (at your option) any later version.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu-common.h"
  16 #include "hw/timer/pl031.h"
  17 #include "migration/vmstate.h"
  18 #include "hw/irq.h"
  19 #include "hw/sysbus.h"
  20 #include "qemu/timer.h"
  21 #include "sysemu/sysemu.h"
  22 #include "qemu/cutils.h"
  23 #include "qemu/log.h"
  24 #include "qemu/module.h"
  25 #include "trace.h"
  26
  27 #define RTC_DR      0x00    /* Data read register */
  28 #define RTC_MR      0x04    /* Match register */
  29 #define RTC_LR      0x08    /* Data load register */
  30 #define RTC_CR      0x0c    /* Control register */
  31 #define RTC_IMSC    0x10    /* Interrupt mask and set register */
  32 #define RTC_RIS     0x14    /* Raw interrupt status register */
  33 #define RTC_MIS     0x18    /* Masked interrupt status register */
  34 #define RTC_ICR     0x1c    /* Interrupt clear register */
  35
  36 static const unsigned char pl031_id[] = {
  37     0x31, 0x10, 0x14, 0x00,         /* Device ID        */
  38     0x0d, 0xf0, 0x05, 0xb1          /* Cell ID      */
  39 };
  40
  41 static void pl031_update(PL031State *s)
  42 {
  43     uint32_t flags = s->is & s->im;
  44
  45     trace_pl031_irq_state(flags);
  46     qemu_set_irq(s->irq, flags);
  47 }
  48
  49 static void pl031_interrupt(void * opaque)
  50 {
  51     PL031State *s = (PL031State *)opaque;
  52
  53     s->is = 1;
  54     trace_pl031_alarm_raised();
  55     pl031_update(s);
  56 }
  57
  58 static uint32_t pl031_get_count(PL031State *s)
  59 {
  60     int64_t now = qemu_clock_get_ns(rtc_clock);
  61     return s->tick_offset + now / NANOSECONDS_PER_SECOND;
  62 }
  63
  64 static void pl031_set_alarm(PL031State *s)
  65 {
  66     uint32_t ticks;
  67
  68     /* The timer wraps around.  This subtraction also wraps in the same way,
  69        and gives correct results when alarm < now_ticks.  */
  70     ticks = s->mr - pl031_get_count(s);
  71     trace_pl031_set_alarm(ticks);
  72     if (ticks == 0) {
  73         timer_del(s->timer);
  74         pl031_interrupt(s);
  75     } else {
  76         int64_t now = qemu_clock_get_ns(rtc_clock);
  77         timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND);
  78     }
  79 }
  80
  81 static uint64_t pl031_read(void *opaque, hwaddr offset,
  82                            unsigned size)
  83 {
  84     PL031State *s = (PL031State *)opaque;
  85     uint64_t r;
  86
  87     switch (offset) {
  88     case RTC_DR:
  89         r = pl031_get_count(s);
  90         break;
  91     case RTC_MR:
  92         r = s->mr;
  93         break;
  94     case RTC_IMSC:
  95         r = s->im;
  96         break;
  97     case RTC_RIS:
  98         r = s->is;
  99         break;
 100     case RTC_LR:
 101         r = s->lr;
 102         break;
 103     case RTC_CR:
 104         /* RTC is permanently enabled.  */
 105         r = 1;
 106         break;
 107     case RTC_MIS:
 108         r = s->is & s->im;
 109         break;
 110     case 0xfe0 ... 0xfff:
 111         r = pl031_id[(offset - 0xfe0) >> 2];
 112         break;
 113     case RTC_ICR:
 114         qemu_log_mask(LOG_GUEST_ERROR,
 115                       "pl031: read of write-only register at offset 0x%x\n",
 116                       (int)offset);
 117         r = 0;
 118         break;
 119     default:
 120         qemu_log_mask(LOG_GUEST_ERROR,
 121                       "pl031_read: Bad offset 0x%x\n", (int)offset);
 122         r = 0;
 123         break;
 124     }
 125
 126     trace_pl031_read(offset, r);
 127     return r;
 128 }
 129
 130 static void pl031_write(void * opaque, hwaddr offset,
 131                         uint64_t value, unsigned size)
 132 {
 133     PL031State *s = (PL031State *)opaque;
 134
 135     trace_pl031_write(offset, value);
 136
 137     switch (offset) {
 138     case RTC_LR:
 139         s->tick_offset += value - pl031_get_count(s);
 140         pl031_set_alarm(s);
 141         break;
 142     case RTC_MR:
 143         s->mr = value;
 144         pl031_set_alarm(s);
 145         break;
 146     case RTC_IMSC:
 147         s->im = value & 1;
 148         pl031_update(s);
 149         break;
 150     case RTC_ICR:
 151         /* The PL031 documentation (DDI0224B) states that the interrupt is
 152            cleared when bit 0 of the written value is set.  However the
 153            arm926e documentation (DDI0287B) states that the interrupt is
 154            cleared when any value is written.  */
 155         s->is = 0;
 156         pl031_update(s);
 157         break;
 158     case RTC_CR:
 159         /* Written value is ignored.  */
 160         break;
 161
 162     case RTC_DR:
 163     case RTC_MIS:
 164     case RTC_RIS:
 165         qemu_log_mask(LOG_GUEST_ERROR,
 166                       "pl031: write to read-only register at offset 0x%x\n",
 167                       (int)offset);
 168         break;
 169
 170     default:
 171         qemu_log_mask(LOG_GUEST_ERROR,
 172                       "pl031_write: Bad offset 0x%x\n", (int)offset);
 173         break;
 174     }
 175 }
 176
 177 static const MemoryRegionOps pl031_ops = {
 178     .read = pl031_read,
 179     .write = pl031_write,
 180     .endianness = DEVICE_NATIVE_ENDIAN,
 181 };
 182
 183 static void pl031_init(Object *obj)
 184 {
 185     PL031State *s = PL031(obj);
 186     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 187     struct tm tm;
 188
 189     memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000);
 190     sysbus_init_mmio(dev, &s->iomem);
 191
 192     sysbus_init_irq(dev, &s->irq);
 193     qemu_get_timedate(&tm, 0);
 194     s->tick_offset = mktimegm(&tm) -
 195         qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 196
 197     s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
 198 }
 199
 200 static int pl031_pre_save(void *opaque)
 201 {
 202     PL031State *s = opaque;
 203
 204     /*
 205      * The PL031 device model code uses the tick_offset field, which is
 206      * the offset between what the guest RTC should read and what the
 207      * QEMU rtc_clock reads:
 208      *  guest_rtc = rtc_clock + tick_offset
 209      * and so
 210      *  tick_offset = guest_rtc - rtc_clock
 211      *
 212      * We want to migrate this offset, which sounds straightforward.
 213      * Unfortunately older versions of QEMU migrated a conversion of this
 214      * offset into an offset from the vm_clock. (This was in turn an
 215      * attempt to be compatible with even older QEMU versions, but it
 216      * has incorrect behaviour if the rtc_clock is not the same as the
 217      * vm_clock.) So we put the actual tick_offset into a migration
 218      * subsection, and the backwards-compatible time-relative-to-vm_clock
 219      * in the main migration state.
 220      *
 221      * Calculate base time relative to QEMU_CLOCK_VIRTUAL:
 222      */
 223     int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 224     s->tick_offset_vmstate = s->tick_offset + delta / NANOSECONDS_PER_SECOND;
 225
 226     return 0;
 227 }
 228
 229 static int pl031_pre_load(void *opaque)
 230 {
 231     PL031State *s = opaque;
 232
 233     s->tick_offset_migrated = false;
 234     return 0;
 235 }
 236
 237 static int pl031_post_load(void *opaque, int version_id)
 238 {
 239     PL031State *s = opaque;
 240
 241     /*
 242      * If we got the tick_offset subsection, then we can just use
 243      * the value in that. Otherwise the source is an older QEMU and
 244      * has given us the offset from the vm_clock; convert it back to
 245      * an offset from the rtc_clock. This will cause time to incorrectly
 246      * go backwards compared to the host RTC, but this is unavoidable.
 247      */
 248
 249     if (!s->tick_offset_migrated) {
 250         int64_t delta = qemu_clock_get_ns(rtc_clock) -
 251             qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 252         s->tick_offset = s->tick_offset_vmstate -
 253             delta / NANOSECONDS_PER_SECOND;
 254     }
 255     pl031_set_alarm(s);
 256     return 0;
 257 }
 258
 259 static int pl031_tick_offset_post_load(void *opaque, int version_id)
 260 {
 261     PL031State *s = opaque;
 262
 263     s->tick_offset_migrated = true;
 264     return 0;
 265 }
 266
 267 static bool pl031_tick_offset_needed(void *opaque)
 268 {
 269     PL031State *s = opaque;
 270
 271     return s->migrate_tick_offset;
 272 }
 273
 274 static const VMStateDescription vmstate_pl031_tick_offset = {
 275     .name = "pl031/tick-offset",
 276     .version_id = 1,
 277     .minimum_version_id = 1,
 278     .needed = pl031_tick_offset_needed,
 279     .post_load = pl031_tick_offset_post_load,
 280     .fields = (VMStateField[]) {
 281         VMSTATE_UINT32(tick_offset, PL031State),
 282         VMSTATE_END_OF_LIST()
 283     }
 284 };
 285
 286 static const VMStateDescription vmstate_pl031 = {
 287     .name = "pl031",
 288     .version_id = 1,
 289     .minimum_version_id = 1,
 290     .pre_save = pl031_pre_save,
 291     .pre_load = pl031_pre_load,
 292     .post_load = pl031_post_load,
 293     .fields = (VMStateField[]) {
 294         VMSTATE_UINT32(tick_offset_vmstate, PL031State),
 295         VMSTATE_UINT32(mr, PL031State),
 296         VMSTATE_UINT32(lr, PL031State),
 297         VMSTATE_UINT32(cr, PL031State),
 298         VMSTATE_UINT32(im, PL031State),
 299         VMSTATE_UINT32(is, PL031State),
 300         VMSTATE_END_OF_LIST()
 301     },
 302     .subsections = (const VMStateDescription*[]) {
 303         &vmstate_pl031_tick_offset,
 304         NULL
 305     }
 306 };
 307
 308 static Property pl031_properties[] = {
 309     /*
 310      * True to correctly migrate the tick offset of the RTC. False to
 311      * obtain backward migration compatibility with older QEMU versions,
 312      * at the expense of the guest RTC going backwards compared with the
 313      * host RTC when the VM is saved/restored if using -rtc host.
 314      * (Even if set to 'true' older QEMU can migrate forward to newer QEMU;
 315      * 'false' also permits newer QEMU to migrate to older QEMU.)
 316      */
 317     DEFINE_PROP_BOOL("migrate-tick-offset",
 318                      PL031State, migrate_tick_offset, true),
 319     DEFINE_PROP_END_OF_LIST()
 320 };
 321
 322 static void pl031_class_init(ObjectClass *klass, void *data)
 323 {
 324     DeviceClass *dc = DEVICE_CLASS(klass);
 325
 326     dc->vmsd = &vmstate_pl031;
 327     dc->props = pl031_properties;
 328 }
 329
 330 static const TypeInfo pl031_info = {
 331     .name          = TYPE_PL031,
 332     .parent        = TYPE_SYS_BUS_DEVICE,
 333     .instance_size = sizeof(PL031State),
 334     .instance_init = pl031_init,
 335     .class_init    = pl031_class_init,
 336 };
 337
 338 static void pl031_register_types(void)
 339 {
 340     type_register_static(&pl031_info);
 341 }
 342
 343 type_init(pl031_register_types)