hw/timer/puv3_ost.c

   1 /*
   2  * OSTimer device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/sysbus.h"
  14 #include "hw/irq.h"
  15 #include "hw/ptimer.h"
  16 #include "qemu/module.h"
  17 #include "qemu/log.h"
  18 #include "qom/object.h"
  19
  20 #undef DEBUG_PUV3
  21 #include "hw/unicore32/puv3.h"
  22
  23 #define TYPE_PUV3_OST "puv3_ost"
  24 typedef struct PUV3OSTState PUV3OSTState;
  25 DECLARE_INSTANCE_CHECKER(PUV3OSTState, PUV3_OST,
  26                          TYPE_PUV3_OST)
  27
  28 /* puv3 ostimer implementation. */
  29 struct PUV3OSTState {
  30     SysBusDevice parent_obj;
  31
  32     MemoryRegion iomem;
  33     qemu_irq irq;
  34     ptimer_state *ptimer;
  35
  36     uint32_t reg_OSMR0;
  37     uint32_t reg_OSCR;
  38     uint32_t reg_OSSR;
  39     uint32_t reg_OIER;
  40 };
  41
  42 static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
  43         unsigned size)
  44 {
  45     PUV3OSTState *s = opaque;
  46     uint32_t ret = 0;
  47
  48     switch (offset) {
  49     case 0x10: /* Counter Register */
  50         ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
  51         break;
  52     case 0x14: /* Status Register */
  53         ret = s->reg_OSSR;
  54         break;
  55     case 0x1c: /* Interrupt Enable Register */
  56         ret = s->reg_OIER;
  57         break;
  58     default:
  59         qemu_log_mask(LOG_GUEST_ERROR,
  60                       "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
  61                       __func__, offset);
  62     }
  63     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  64     return ret;
  65 }
  66
  67 static void puv3_ost_write(void *opaque, hwaddr offset,
  68         uint64_t value, unsigned size)
  69 {
  70     PUV3OSTState *s = opaque;
  71
  72     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  73     switch (offset) {
  74     case 0x00: /* Match Register 0 */
  75         ptimer_transaction_begin(s->ptimer);
  76         s->reg_OSMR0 = value;
  77         if (s->reg_OSMR0 > s->reg_OSCR) {
  78             ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
  79         } else {
  80             ptimer_set_count(s->ptimer, s->reg_OSMR0 +
  81                     (0xffffffff - s->reg_OSCR));
  82         }
  83         ptimer_run(s->ptimer, 2);
  84         ptimer_transaction_commit(s->ptimer);
  85         break;
  86     case 0x14: /* Status Register */
  87         assert(value == 0);
  88         if (s->reg_OSSR) {
  89             s->reg_OSSR = value;
  90             qemu_irq_lower(s->irq);
  91         }
  92         break;
  93     case 0x1c: /* Interrupt Enable Register */
  94         s->reg_OIER = value;
  95         break;
  96     default:
  97         qemu_log_mask(LOG_GUEST_ERROR,
  98                       "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
  99                       __func__, offset);
 100     }
 101 }
 102
 103 static const MemoryRegionOps puv3_ost_ops = {
 104     .read = puv3_ost_read,
 105     .write = puv3_ost_write,
 106     .impl = {
 107         .min_access_size = 4,
 108         .max_access_size = 4,
 109     },
 110     .endianness = DEVICE_NATIVE_ENDIAN,
 111 };
 112
 113 static void puv3_ost_tick(void *opaque)
 114 {
 115     PUV3OSTState *s = opaque;
 116
 117     DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
 118             s->reg_OSCR, s->reg_OSMR0);
 119
 120     s->reg_OSCR = s->reg_OSMR0;
 121     if (s->reg_OIER) {
 122         s->reg_OSSR = 1;
 123         qemu_irq_raise(s->irq);
 124     }
 125 }
 126
 127 static void puv3_ost_realize(DeviceState *dev, Error **errp)
 128 {
 129     PUV3OSTState *s = PUV3_OST(dev);
 130     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 131
 132     s->reg_OIER = 0;
 133     s->reg_OSSR = 0;
 134     s->reg_OSMR0 = 0;
 135     s->reg_OSCR = 0;
 136
 137     sysbus_init_irq(sbd, &s->irq);
 138
 139     s->ptimer = ptimer_init(puv3_ost_tick, s, PTIMER_POLICY_DEFAULT);
 140     ptimer_transaction_begin(s->ptimer);
 141     ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
 142     ptimer_transaction_commit(s->ptimer);
 143
 144     memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
 145             PUV3_REGS_OFFSET);
 146     sysbus_init_mmio(sbd, &s->iomem);
 147 }
 148
 149 static void puv3_ost_class_init(ObjectClass *klass, void *data)
 150 {
 151     DeviceClass *dc = DEVICE_CLASS(klass);
 152
 153     dc->realize = puv3_ost_realize;
 154 }
 155
 156 static const TypeInfo puv3_ost_info = {
 157     .name = TYPE_PUV3_OST,
 158     .parent = TYPE_SYS_BUS_DEVICE,
 159     .instance_size = sizeof(PUV3OSTState),
 160     .class_init = puv3_ost_class_init,
 161 };
 162
 163 static void puv3_ost_register_type(void)
 164 {
 165     type_register_static(&puv3_ost_info);
 166 }
 167
 168 type_init(puv3_ost_register_type)