hw/timer/stm32f2xx_timer.c

   1 /*
   2  * STM32F2XX Timer
   3  *
   4  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/irq.h"
  27 #include "hw/timer/stm32f2xx_timer.h"
  28 #include "migration/vmstate.h"
  29 #include "qemu/log.h"
  30 #include "qemu/module.h"
  31
  32 #ifndef STM_TIMER_ERR_DEBUG
  33 #define STM_TIMER_ERR_DEBUG 0
  34 #endif
  35
  36 #define DB_PRINT_L(lvl, fmt, args...) do { \
  37     if (STM_TIMER_ERR_DEBUG >= lvl) { \
  38         qemu_log("%s: " fmt, __func__, ## args); \
  39     } \
  40 } while (0)
  41
  42 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
  43
  44 static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now);
  45
  46 static void stm32f2xx_timer_interrupt(void *opaque)
  47 {
  48     STM32F2XXTimerState *s = opaque;
  49
  50     DB_PRINT("Interrupt\n");
  51
  52     if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) {
  53         s->tim_sr |= 1;
  54         qemu_irq_pulse(s->irq);
  55         stm32f2xx_timer_set_alarm(s, s->hit_time);
  56     }
  57
  58     if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 | TIM_CCMR1_OC2M1) &&
  59         !(s->tim_ccmr1 & TIM_CCMR1_OC2M0) &&
  60         s->tim_ccmr1 & TIM_CCMR1_OC2PE &&
  61         s->tim_ccer & TIM_CCER_CC2E) {
  62         /* PWM 2 - Mode 1 */
  63         DB_PRINT("PWM2 Duty Cycle: %d%%\n",
  64                 s->tim_ccr2 / (100 * (s->tim_psc + 1)));
  65     }
  66 }
  67
  68 static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t)
  69 {
  70     return muldiv64(t, s->freq_hz, 1000000000ULL) / (s->tim_psc + 1);
  71 }
  72
  73 static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now)
  74 {
  75     uint64_t ticks;
  76     int64_t now_ticks;
  77
  78     if (s->tim_arr == 0) {
  79         return;
  80     }
  81
  82     DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1);
  83
  84     now_ticks = stm32f2xx_ns_to_ticks(s, now);
  85     ticks = s->tim_arr - (now_ticks - s->tick_offset);
  86
  87     DB_PRINT("Alarm set in %d ticks\n", (int) ticks);
  88
  89     s->hit_time = muldiv64((ticks + (uint64_t) now_ticks) * (s->tim_psc + 1),
  90                                1000000000ULL, s->freq_hz);
  91
  92     timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hit_time);
  93     DB_PRINT("Wait Time: %" PRId64 " ticks\n", s->hit_time);
  94 }
  95
  96 static void stm32f2xx_timer_reset(DeviceState *dev)
  97 {
  98     STM32F2XXTimerState *s = STM32F2XXTIMER(dev);
  99     int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 100
 101     s->tim_cr1 = 0;
 102     s->tim_cr2 = 0;
 103     s->tim_smcr = 0;
 104     s->tim_dier = 0;
 105     s->tim_sr = 0;
 106     s->tim_egr = 0;
 107     s->tim_ccmr1 = 0;
 108     s->tim_ccmr2 = 0;
 109     s->tim_ccer = 0;
 110     s->tim_psc = 0;
 111     s->tim_arr = 0;
 112     s->tim_ccr1 = 0;
 113     s->tim_ccr2 = 0;
 114     s->tim_ccr3 = 0;
 115     s->tim_ccr4 = 0;
 116     s->tim_dcr = 0;
 117     s->tim_dmar = 0;
 118     s->tim_or = 0;
 119
 120     s->tick_offset = stm32f2xx_ns_to_ticks(s, now);
 121 }
 122
 123 static uint64_t stm32f2xx_timer_read(void *opaque, hwaddr offset,
 124                            unsigned size)
 125 {
 126     STM32F2XXTimerState *s = opaque;
 127
 128     DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset);
 129
 130     switch (offset) {
 131     case TIM_CR1:
 132         return s->tim_cr1;
 133     case TIM_CR2:
 134         return s->tim_cr2;
 135     case TIM_SMCR:
 136         return s->tim_smcr;
 137     case TIM_DIER:
 138         return s->tim_dier;
 139     case TIM_SR:
 140         return s->tim_sr;
 141     case TIM_EGR:
 142         return s->tim_egr;
 143     case TIM_CCMR1:
 144         return s->tim_ccmr1;
 145     case TIM_CCMR2:
 146         return s->tim_ccmr2;
 147     case TIM_CCER:
 148         return s->tim_ccer;
 149     case TIM_CNT:
 150         return stm32f2xx_ns_to_ticks(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) -
 151                s->tick_offset;
 152     case TIM_PSC:
 153         return s->tim_psc;
 154     case TIM_ARR:
 155         return s->tim_arr;
 156     case TIM_CCR1:
 157         return s->tim_ccr1;
 158     case TIM_CCR2:
 159         return s->tim_ccr2;
 160     case TIM_CCR3:
 161         return s->tim_ccr3;
 162     case TIM_CCR4:
 163         return s->tim_ccr4;
 164     case TIM_DCR:
 165         return s->tim_dcr;
 166     case TIM_DMAR:
 167         return s->tim_dmar;
 168     case TIM_OR:
 169         return s->tim_or;
 170     default:
 171         qemu_log_mask(LOG_GUEST_ERROR,
 172                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset);
 173     }
 174
 175     return 0;
 176 }
 177
 178 static void stm32f2xx_timer_write(void *opaque, hwaddr offset,
 179                         uint64_t val64, unsigned size)
 180 {
 181     STM32F2XXTimerState *s = opaque;
 182     uint32_t value = val64;
 183     int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 184     uint32_t timer_val = 0;
 185
 186     DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset);
 187
 188     switch (offset) {
 189     case TIM_CR1:
 190         s->tim_cr1 = value;
 191         return;
 192     case TIM_CR2:
 193         s->tim_cr2 = value;
 194         return;
 195     case TIM_SMCR:
 196         s->tim_smcr = value;
 197         return;
 198     case TIM_DIER:
 199         s->tim_dier = value;
 200         return;
 201     case TIM_SR:
 202         /* This is set by hardware and cleared by software */
 203         s->tim_sr &= value;
 204         return;
 205     case TIM_EGR:
 206         s->tim_egr = value;
 207         if (s->tim_egr & TIM_EGR_UG) {
 208             timer_val = 0;
 209             break;
 210         }
 211         return;
 212     case TIM_CCMR1:
 213         s->tim_ccmr1 = value;
 214         return;
 215     case TIM_CCMR2:
 216         s->tim_ccmr2 = value;
 217         return;
 218     case TIM_CCER:
 219         s->tim_ccer = value;
 220         return;
 221     case TIM_PSC:
 222         timer_val = stm32f2xx_ns_to_ticks(s, now) - s->tick_offset;
 223         s->tim_psc = value & 0xFFFF;
 224         value = timer_val;
 225         break;
 226     case TIM_CNT:
 227         timer_val = value;
 228         break;
 229     case TIM_ARR:
 230         s->tim_arr = value;
 231         stm32f2xx_timer_set_alarm(s, now);
 232         return;
 233     case TIM_CCR1:
 234         s->tim_ccr1 = value;
 235         return;
 236     case TIM_CCR2:
 237         s->tim_ccr2 = value;
 238         return;
 239     case TIM_CCR3:
 240         s->tim_ccr3 = value;
 241         return;
 242     case TIM_CCR4:
 243         s->tim_ccr4 = value;
 244         return;
 245     case TIM_DCR:
 246         s->tim_dcr = value;
 247         return;
 248     case TIM_DMAR:
 249         s->tim_dmar = value;
 250         return;
 251     case TIM_OR:
 252         s->tim_or = value;
 253         return;
 254     default:
 255         qemu_log_mask(LOG_GUEST_ERROR,
 256                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset);
 257         return;
 258     }
 259
 260     /* This means that a register write has affected the timer in a way that
 261      * requires a refresh of both tick_offset and the alarm.
 262      */
 263     s->tick_offset = stm32f2xx_ns_to_ticks(s, now) - timer_val;
 264     stm32f2xx_timer_set_alarm(s, now);
 265 }
 266
 267 static const MemoryRegionOps stm32f2xx_timer_ops = {
 268     .read = stm32f2xx_timer_read,
 269     .write = stm32f2xx_timer_write,
 270     .endianness = DEVICE_NATIVE_ENDIAN,
 271 };
 272
 273 static const VMStateDescription vmstate_stm32f2xx_timer = {
 274     .name = TYPE_STM32F2XX_TIMER,
 275     .version_id = 1,
 276     .minimum_version_id = 1,
 277     .fields = (VMStateField[]) {
 278         VMSTATE_INT64(tick_offset, STM32F2XXTimerState),
 279         VMSTATE_UINT32(tim_cr1, STM32F2XXTimerState),
 280         VMSTATE_UINT32(tim_cr2, STM32F2XXTimerState),
 281         VMSTATE_UINT32(tim_smcr, STM32F2XXTimerState),
 282         VMSTATE_UINT32(tim_dier, STM32F2XXTimerState),
 283         VMSTATE_UINT32(tim_sr, STM32F2XXTimerState),
 284         VMSTATE_UINT32(tim_egr, STM32F2XXTimerState),
 285         VMSTATE_UINT32(tim_ccmr1, STM32F2XXTimerState),
 286         VMSTATE_UINT32(tim_ccmr2, STM32F2XXTimerState),
 287         VMSTATE_UINT32(tim_ccer, STM32F2XXTimerState),
 288         VMSTATE_UINT32(tim_psc, STM32F2XXTimerState),
 289         VMSTATE_UINT32(tim_arr, STM32F2XXTimerState),
 290         VMSTATE_UINT32(tim_ccr1, STM32F2XXTimerState),
 291         VMSTATE_UINT32(tim_ccr2, STM32F2XXTimerState),
 292         VMSTATE_UINT32(tim_ccr3, STM32F2XXTimerState),
 293         VMSTATE_UINT32(tim_ccr4, STM32F2XXTimerState),
 294         VMSTATE_UINT32(tim_dcr, STM32F2XXTimerState),
 295         VMSTATE_UINT32(tim_dmar, STM32F2XXTimerState),
 296         VMSTATE_UINT32(tim_or, STM32F2XXTimerState),
 297         VMSTATE_END_OF_LIST()
 298     }
 299 };
 300
 301 static Property stm32f2xx_timer_properties[] = {
 302     DEFINE_PROP_UINT64("clock-frequency", struct STM32F2XXTimerState,
 303                        freq_hz, 1000000000),
 304     DEFINE_PROP_END_OF_LIST(),
 305 };
 306
 307 static void stm32f2xx_timer_init(Object *obj)
 308 {
 309     STM32F2XXTimerState *s = STM32F2XXTIMER(obj);
 310
 311     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 312
 313     memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s,
 314                           "stm32f2xx_timer", 0x400);
 315     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
 316
 317     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s);
 318 }
 319
 320 static void stm32f2xx_timer_class_init(ObjectClass *klass, void *data)
 321 {
 322     DeviceClass *dc = DEVICE_CLASS(klass);
 323
 324     dc->reset = stm32f2xx_timer_reset;
 325     dc->props = stm32f2xx_timer_properties;
 326     dc->vmsd = &vmstate_stm32f2xx_timer;
 327 }
 328
 329 static const TypeInfo stm32f2xx_timer_info = {
 330     .name          = TYPE_STM32F2XX_TIMER,
 331     .parent        = TYPE_SYS_BUS_DEVICE,
 332     .instance_size = sizeof(STM32F2XXTimerState),
 333     .instance_init = stm32f2xx_timer_init,
 334     .class_init    = stm32f2xx_timer_class_init,
 335 };
 336
 337 static void stm32f2xx_timer_register_types(void)
 338 {
 339     type_register_static(&stm32f2xx_timer_info);
 340 }
 341
 342 type_init(stm32f2xx_timer_register_types)