hw/timer/xlnx-zynqmp-rtc.c

   1 /*
   2  * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).
   3  *
   4  * Copyright (c) 2017 Xilinx Inc.
   5  *
   6  * Written-by: Alistair Francis <alistair.francis@xilinx.com>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/register.h"
  30 #include "qemu/bitops.h"
  31 #include "qemu/log.h"
  32 #include "qemu/module.h"
  33 #include "hw/ptimer.h"
  34 #include "qemu/cutils.h"
  35 #include "sysemu/sysemu.h"
  36 #include "trace.h"
  37 #include "hw/timer/xlnx-zynqmp-rtc.h"
  38
  39 #ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG
  40 #define XLNX_ZYNQMP_RTC_ERR_DEBUG 0
  41 #endif
  42
  43 static void rtc_int_update_irq(XlnxZynqMPRTC *s)
  44 {
  45     bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK];
  46     qemu_set_irq(s->irq_rtc_int, pending);
  47 }
  48
  49 static void addr_error_int_update_irq(XlnxZynqMPRTC *s)
  50 {
  51     bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK];
  52     qemu_set_irq(s->irq_addr_error_int, pending);
  53 }
  54
  55 static uint32_t rtc_get_count(XlnxZynqMPRTC *s)
  56 {
  57     int64_t now = qemu_clock_get_ns(rtc_clock);
  58     return s->tick_offset + now / NANOSECONDS_PER_SECOND;
  59 }
  60
  61 static uint64_t current_time_postr(RegisterInfo *reg, uint64_t val64)
  62 {
  63     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  64
  65     return rtc_get_count(s);
  66 }
  67
  68 static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64)
  69 {
  70     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  71     rtc_int_update_irq(s);
  72 }
  73
  74 static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64)
  75 {
  76     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  77
  78     s->regs[R_RTC_INT_MASK] &= (uint32_t) ~val64;
  79     rtc_int_update_irq(s);
  80     return 0;
  81 }
  82
  83 static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64)
  84 {
  85     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  86
  87     s->regs[R_RTC_INT_MASK] |= (uint32_t) val64;
  88     rtc_int_update_irq(s);
  89     return 0;
  90 }
  91
  92 static void addr_error_postw(RegisterInfo *reg, uint64_t val64)
  93 {
  94     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  95     addr_error_int_update_irq(s);
  96 }
  97
  98 static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64)
  99 {
 100     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
 101
 102     s->regs[R_ADDR_ERROR_INT_MASK] &= (uint32_t) ~val64;
 103     addr_error_int_update_irq(s);
 104     return 0;
 105 }
 106
 107 static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64)
 108 {
 109     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
 110
 111     s->regs[R_ADDR_ERROR_INT_MASK] |= (uint32_t) val64;
 112     addr_error_int_update_irq(s);
 113     return 0;
 114 }
 115
 116 static const RegisterAccessInfo rtc_regs_info[] = {
 117     {   .name = "SET_TIME_WRITE",  .addr = A_SET_TIME_WRITE,
 118         .unimp = MAKE_64BIT_MASK(0, 32),
 119     },{ .name = "SET_TIME_READ",  .addr = A_SET_TIME_READ,
 120         .ro = 0xffffffff,
 121         .post_read = current_time_postr,
 122     },{ .name = "CALIB_WRITE",  .addr = A_CALIB_WRITE,
 123         .unimp = MAKE_64BIT_MASK(0, 32),
 124     },{ .name = "CALIB_READ",  .addr = A_CALIB_READ,
 125         .ro = 0x1fffff,
 126     },{ .name = "CURRENT_TIME",  .addr = A_CURRENT_TIME,
 127         .ro = 0xffffffff,
 128         .post_read = current_time_postr,
 129     },{ .name = "CURRENT_TICK",  .addr = A_CURRENT_TICK,
 130         .ro = 0xffff,
 131     },{ .name = "ALARM",  .addr = A_ALARM,
 132     },{ .name = "RTC_INT_STATUS",  .addr = A_RTC_INT_STATUS,
 133         .w1c = 0x3,
 134         .post_write = rtc_int_status_postw,
 135     },{ .name = "RTC_INT_MASK",  .addr = A_RTC_INT_MASK,
 136         .reset = 0x3,
 137         .ro = 0x3,
 138     },{ .name = "RTC_INT_EN",  .addr = A_RTC_INT_EN,
 139         .pre_write = rtc_int_en_prew,
 140     },{ .name = "RTC_INT_DIS",  .addr = A_RTC_INT_DIS,
 141         .pre_write = rtc_int_dis_prew,
 142     },{ .name = "ADDR_ERROR",  .addr = A_ADDR_ERROR,
 143         .w1c = 0x1,
 144         .post_write = addr_error_postw,
 145     },{ .name = "ADDR_ERROR_INT_MASK",  .addr = A_ADDR_ERROR_INT_MASK,
 146         .reset = 0x1,
 147         .ro = 0x1,
 148     },{ .name = "ADDR_ERROR_INT_EN",  .addr = A_ADDR_ERROR_INT_EN,
 149         .pre_write = addr_error_int_en_prew,
 150     },{ .name = "ADDR_ERROR_INT_DIS",  .addr = A_ADDR_ERROR_INT_DIS,
 151         .pre_write = addr_error_int_dis_prew,
 152     },{ .name = "CONTROL",  .addr = A_CONTROL,
 153         .reset = 0x1000000,
 154         .rsvd = 0x70fffffe,
 155     },{ .name = "SAFETY_CHK",  .addr = A_SAFETY_CHK,
 156     }
 157 };
 158
 159 static void rtc_reset(DeviceState *dev)
 160 {
 161     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(dev);
 162     unsigned int i;
 163
 164     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
 165         register_reset(&s->regs_info[i]);
 166     }
 167
 168     rtc_int_update_irq(s);
 169     addr_error_int_update_irq(s);
 170 }
 171
 172 static const MemoryRegionOps rtc_ops = {
 173     .read = register_read_memory,
 174     .write = register_write_memory,
 175     .endianness = DEVICE_LITTLE_ENDIAN,
 176     .valid = {
 177         .min_access_size = 4,
 178         .max_access_size = 4,
 179     },
 180 };
 181
 182 static void rtc_init(Object *obj)
 183 {
 184     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj);
 185     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 186     RegisterInfoArray *reg_array;
 187     struct tm current_tm;
 188
 189     memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC,
 190                        XLNX_ZYNQMP_RTC_R_MAX * 4);
 191     reg_array =
 192         register_init_block32(DEVICE(obj), rtc_regs_info,
 193                               ARRAY_SIZE(rtc_regs_info),
 194                               s->regs_info, s->regs,
 195                               &rtc_ops,
 196                               XLNX_ZYNQMP_RTC_ERR_DEBUG,
 197                               XLNX_ZYNQMP_RTC_R_MAX * 4);
 198     memory_region_add_subregion(&s->iomem,
 199                                 0x0,
 200                                 &reg_array->mem);
 201     sysbus_init_mmio(sbd, &s->iomem);
 202     sysbus_init_irq(sbd, &s->irq_rtc_int);
 203     sysbus_init_irq(sbd, &s->irq_addr_error_int);
 204
 205     qemu_get_timedate(&current_tm, 0);
 206     s->tick_offset = mktimegm(&current_tm) -
 207         qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 208
 209     trace_xlnx_zynqmp_rtc_gettime(current_tm.tm_year, current_tm.tm_mon,
 210                                   current_tm.tm_mday, current_tm.tm_hour,
 211                                   current_tm.tm_min, current_tm.tm_sec);
 212 }
 213
 214 static int rtc_pre_save(void *opaque)
 215 {
 216     XlnxZynqMPRTC *s = opaque;
 217     int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 218
 219     /* Add the time at migration */
 220     s->tick_offset = s->tick_offset + now;
 221
 222     return 0;
 223 }
 224
 225 static int rtc_post_load(void *opaque, int version_id)
 226 {
 227     XlnxZynqMPRTC *s = opaque;
 228     int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 229
 230     /* Subtract the time after migration. This combined with the pre_save
 231      * action results in us having subtracted the time that the guest was
 232      * stopped to the offset.
 233      */
 234     s->tick_offset = s->tick_offset - now;
 235
 236     return 0;
 237 }
 238
 239 static const VMStateDescription vmstate_rtc = {
 240     .name = TYPE_XLNX_ZYNQMP_RTC,
 241     .version_id = 1,
 242     .minimum_version_id = 1,
 243     .pre_save = rtc_pre_save,
 244     .post_load = rtc_post_load,
 245     .fields = (VMStateField[]) {
 246         VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX),
 247         VMSTATE_UINT32(tick_offset, XlnxZynqMPRTC),
 248         VMSTATE_END_OF_LIST(),
 249     }
 250 };
 251
 252 static void rtc_class_init(ObjectClass *klass, void *data)
 253 {
 254     DeviceClass *dc = DEVICE_CLASS(klass);
 255
 256     dc->reset = rtc_reset;
 257     dc->vmsd = &vmstate_rtc;
 258 }
 259
 260 static const TypeInfo rtc_info = {
 261     .name          = TYPE_XLNX_ZYNQMP_RTC,
 262     .parent        = TYPE_SYS_BUS_DEVICE,
 263     .instance_size = sizeof(XlnxZynqMPRTC),
 264     .class_init    = rtc_class_init,
 265     .instance_init = rtc_init,
 266 };
 267
 268 static void rtc_register_types(void)
 269 {
 270     type_register_static(&rtc_info);
 271 }
 272
 273 type_init(rtc_register_types)