include/asm-arm/arch-arm720t/s3c4510b.h

   1 #ifndef __HW_S3C4510_H
   2 #define __HW_S3C4510_H
   3
   4 /*
   5  * Copyright (c) 2004   Cucy Systems (http://www.cucy.com)
   6  * Curt Brune <curt@cucy.com>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  *
  26  * Description:   Samsung S3C4510B register layout
  27  */
  28
  29 /*------------------------------------------------------------------------
  30  *        ASIC Address Definition
  31  *----------------------------------------------------------------------*/
  32
  33 /* L1 8KB on chip SRAM base address */
  34 #define SRAM_BASE       (0x03fe0000)
  35
  36 /* Special Register Start Address After System Reset */
  37 #define REG_BASE        (0x03ff0000)
  38 #define SPSTR           (REG_BASE)
  39
  40 /* *********************** */
  41 /* System Manager Register */
  42 /* *********************** */
  43 #define REG_SYSCFG      (REG_BASE+0x0000)
  44
  45 #define REG_CLKCON      (REG_BASE+0x3000)
  46 #define REG_EXTACON0    (REG_BASE+0x3008)
  47 #define REG_EXTACON1    (REG_BASE+0x300c)
  48 #define REG_EXTDBWTH    (REG_BASE+0x3010)
  49 #define REG_ROMCON0     (REG_BASE+0x3014)
  50 #define REG_ROMCON1     (REG_BASE+0x3018)
  51 #define REG_ROMCON2     (REG_BASE+0x301c)
  52 #define REG_ROMCON3     (REG_BASE+0x3020)
  53 #define REG_ROMCON4     (REG_BASE+0x3024)
  54 #define REG_ROMCON5     (REG_BASE+0x3028)
  55 #define REG_DRAMCON0    (REG_BASE+0x302c)
  56 #define REG_DRAMCON1    (REG_BASE+0x3030)
  57 #define REG_DRAMCON2    (REG_BASE+0x3034)
  58 #define REG_DRAMCON3    (REG_BASE+0x3038)
  59 #define REG_REFEXTCON   (REG_BASE+0x303c)
  60
  61 /* *********************** */
  62 /* Ethernet BDMA Register  */
  63 /* *********************** */
  64 #define REG_BDMATXCON   (REG_BASE+0x9000)
  65 #define REG_BDMARXCON   (REG_BASE+0x9004)
  66 #define REG_BDMATXPTR   (REG_BASE+0x9008)
  67 #define REG_BDMARXPTR   (REG_BASE+0x900c)
  68 #define REG_BDMARXLSZ   (REG_BASE+0x9010)
  69 #define REG_BDMASTAT    (REG_BASE+0x9014)
  70
  71 /* Content Address Memory */
  72 #define REG_CAM_BASE    (REG_BASE+0x9100)
  73
  74 #define REG_BDMATXBUF   (REG_BASE+0x9200)
  75 #define REG_BDMARXBUF   (REG_BASE+0x9800)
  76
  77 /* *********************** */
  78 /* Ethernet MAC Register   */
  79 /* *********************** */
  80 #define REG_MACCON      (REG_BASE+0xa000)
  81 #define REG_CAMCON      (REG_BASE+0xa004)
  82 #define REG_MACTXCON    (REG_BASE+0xa008)
  83 #define REG_MACTXSTAT   (REG_BASE+0xa00c)
  84 #define REG_MACRXCON    (REG_BASE+0xa010)
  85 #define REG_MACRXSTAT   (REG_BASE+0xa014)
  86 #define REG_STADATA     (REG_BASE+0xa018)
  87 #define REG_STACON      (REG_BASE+0xa01c)
  88 #define REG_CAMEN       (REG_BASE+0xa028)
  89 #define REG_EMISSCNT    (REG_BASE+0xa03c)
  90 #define REG_EPZCNT      (REG_BASE+0xa040)
  91 #define REG_ERMPZCNT    (REG_BASE+0xa044)
  92 #define REG_ETXSTAT     (REG_BASE+0x9040)
  93 #define REG_MACRXDESTR  (REG_BASE+0xa064)
  94 #define REG_MACRXSTATEM (REG_BASE+0xa090)
  95 #define REG_MACRXFIFO   (REG_BASE+0xa200)
  96
  97 /********************/
  98 /* I2C Bus Register */
  99 /********************/
 100 #define REG_I2C_CON     (REG_BASE+0xf000)
 101 #define REG_I2C_BUF     (REG_BASE+0xf004)
 102 #define REG_I2C_PS      (REG_BASE+0xf008)
 103 #define REG_I2C_COUNT   (REG_BASE+0xf00c)
 104
 105 /********************/
 106 /*    GDMA 0        */
 107 /********************/
 108 #define REG_GDMACON0    (REG_BASE+0xb000)
 109 #define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020)
 110 #define REG_GDMASRC0    (REG_BASE+0xb004)
 111 #define REG_GDMADST0    (REG_BASE+0xb008)
 112 #define REG_GDMACNT0    (REG_BASE+0xb00c)
 113
 114 /********************/
 115 /*    GDMA 1        */
 116 /********************/
 117 #define REG_GDMACON1    (REG_BASE+0xc000)
 118 #define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020)
 119 #define REG_GDMASRC1    (REG_BASE+0xc004)
 120 #define REG_GDMADST1    (REG_BASE+0xc008)
 121 #define REG_GDMACNT1    (REG_BASE+0xc00c)
 122
 123 /********************/
 124 /*      UART 0      */
 125 /********************/
 126 #define UART0_BASE       (REG_BASE+0xd000)
 127 #define REG_UART0_LCON   (REG_BASE+0xd000)
 128 #define REG_UART0_CTRL   (REG_BASE+0xd004)
 129 #define REG_UART0_STAT   (REG_BASE+0xd008)
 130 #define REG_UART0_TXB    (REG_BASE+0xd00c)
 131 #define REG_UART0_RXB    (REG_BASE+0xd010)
 132 #define REG_UART0_BAUD_DIV    (REG_BASE+0xd014)
 133 #define REG_UART0_BAUD_CNT    (REG_BASE+0xd018)
 134 #define REG_UART0_BAUD_CLK    (REG_BASE+0xd01C)
 135
 136 /********************/
 137 /*     UART 1       */
 138 /********************/
 139 #define UART1_BASE       (REG_BASE+0xe000)
 140 #define REG_UART1_LCON   (REG_BASE+0xe000)
 141 #define REG_UART1_CTRL   (REG_BASE+0xe004)
 142 #define REG_UART1_STAT   (REG_BASE+0xe008)
 143 #define REG_UART1_TXB    (REG_BASE+0xe00c)
 144 #define REG_UART1_RXB    (REG_BASE+0xe010)
 145 #define REG_UART1_BAUD_DIV    (REG_BASE+0xe014)
 146 #define REG_UART1_BAUD_CNT    (REG_BASE+0xe018)
 147 #define REG_UART1_BAUD_CLK    (REG_BASE+0xe01C)
 148
 149 /********************/
 150 /*  Timer Register  */
 151 /********************/
 152 #define REG_TMOD        (REG_BASE+0x6000)
 153 #define REG_TDATA0      (REG_BASE+0x6004)
 154 #define REG_TDATA1      (REG_BASE+0x6008)
 155 #define REG_TCNT0       (REG_BASE+0x600c)
 156 #define REG_TCNT1       (REG_BASE+0x6010)
 157
 158 /**********************/
 159 /* I/O Port Interface */
 160 /**********************/
 161 #define REG_IOPMODE     (REG_BASE+0x5000)
 162 #define REG_IOPCON      (REG_BASE+0x5004)
 163 #define REG_IOPDATA     (REG_BASE+0x5008)
 164
 165 /*********************************/
 166 /* Interrupt Controller Register */
 167 /*********************************/
 168 #define REG_INTMODE     (REG_BASE+0x4000)
 169 #define REG_INTPEND     (REG_BASE+0x4004)
 170 #define REG_INTMASK     (REG_BASE+0x4008)
 171
 172 #define REG_INTPRI0     (REG_BASE+0x400c)
 173 #define REG_INTPRI1     (REG_BASE+0x4010)
 174 #define REG_INTPRI2     (REG_BASE+0x4014)
 175 #define REG_INTPRI3     (REG_BASE+0x4018)
 176 #define REG_INTPRI4     (REG_BASE+0x401c)
 177 #define REG_INTPRI5     (REG_BASE+0x4020)
 178 #define REG_INTOFFSET   (REG_BASE+0x4024)
 179 #define REG_INTPNDPRI   (REG_BASE+0x4028)
 180 #define REG_INTPNDTST   (REG_BASE+0x402C)
 181
 182 /*********************************/
 183 /* CACHE CONTROL MASKS           */
 184 /*********************************/
 185 #define CACHE_STALL      (0x00000001)
 186 #define CACHE_ENABLE     (0x00000002)
 187 #define CACHE_WRITE_BUFF (0x00000004)
 188 #define CACHE_MODE       (0x00000030)
 189 #define CACHE_MODE_00    (0x00000000)
 190 #define CACHE_MODE_01    (0x00000010)
 191 #define CACHE_MODE_10    (0x00000020)
 192
 193 /*********************************/
 194 /* CACHE RAM BASE ADDRESSES      */
 195 /*********************************/
 196 #define CACHE_SET0_RAM   (0x10000000)
 197 #define CACHE_SET1_RAM   (0x10800000)
 198 #define CACHE_TAG_RAM    (0x11000000)
 199
 200 /*********************************/
 201 /* CACHE_DISABLE MASK            */
 202 /*********************************/
 203 #define CACHE_DISABLE_MASK (0x04000000)
 204
 205 #define GET_REG(reg)       (*((volatile u32 *)(reg)))
 206 #define PUT_REG(reg, val)  (*((volatile u32 *)(reg)) = ((u32)(val)))
 207 #define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) |  mask))
 208 #define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask))
 209 #define PUT_U16(reg, val)  (*((volatile u16 *)(reg)) = ((u16)(val)))
 210 #define PUT__U8(reg, val)  (*((volatile u8  *)(reg)) = (( u8)((val)&0xFF)))
 211 #define GET__U8(reg)       (*((volatile u8  *)(reg)))
 212
 213 #define PUT_LED(val)       (PUT_REG(REG_IOPDATA, (~val)&0xFF))
 214 #define GET_LED()          ((~GET_REG( REG_IOPDATA)) & 0xFF)
 215 #define SET_LED(val)       { u32 led = GET_LED(); led |= 1 << (val);  PUT_LED( led); }
 216 #define CLR_LED(val)       { u32 led = GET_LED(); led &= ~(1 << (val));  PUT_LED( led); }
 217
 218 /***********************************/
 219 /* CLOCK CONSTANTS -- 50 MHz Clock */
 220 /***********************************/
 221
 222 #define CLK_FREQ_MHZ       (50)
 223 #define t_data_us(t)       ((t)*CLK_FREQ_MHZ-1)   /* t is time tick,unit[us] */
 224 #define t_data_ms(t)       (t_data_us((t)*1000))  /* t is time tick,unit[ms] */
 225
 226 /*********************************************************/
 227 /*             TIMER MODE REGISTER                       */
 228 /*********************************************************/
 229 #define  TM0_RUN      0x01  /* Timer 0 enable */
 230 #define  TM0_TOGGLE   0x02  /* 0, interval mode */
 231 #define  TM0_OUT_1    0x04  /* Timer 0 Initial TOUT0 value */
 232 #define  TM1_RUN      0x08  /* Timer 1 enable */
 233 #define  TM1_TOGGLE   0x10  /* 0, interval mode */
 234 #define  TM1_OUT_1    0x20  /* Timer 0 Initial TOUT0 value */
 235
 236
 237 /*********************************/
 238 /* INTERRUPT SOURCES             */
 239 /*********************************/
 240 #define INT_EXTINT0     0
 241 #define INT_EXTINT1     1
 242 #define INT_EXTINT2     2
 243 #define INT_EXTINT3     3
 244 #define INT_UARTTX0     4
 245 #define INT_UARTRX0     5
 246 #define INT_UARTTX1     6
 247 #define INT_UARTRX1     7
 248 #define INT_GDMA0       8
 249 #define INT_GDMA1       9
 250 #define INT_TIMER0      10
 251 #define INT_TIMER1      11
 252 #define INT_HDLCTXA     12
 253 #define INT_HDLCRXA     13
 254 #define INT_HDLCTXB     14
 255 #define INT_HDLCRXB     15
 256 #define INT_BDMATX      16
 257 #define INT_BDMARX      17
 258 #define INT_MACTX       18
 259 #define INT_MACRX       19
 260 #define INT_IIC         20
 261 #define INT_GLOBAL      21
 262 #define N_IRQS         (21)
 263
 264 #ifndef __ASSEMBLER__
 265 struct _irq_handler {
 266         void                *m_data;
 267         void (*m_func)( void *data);
 268 };
 269
 270 #endif
 271
 272 #endif /* __S3C4510_h */