2 * (C) Copyright 2007 DENX Software Engineering
4 * MPC512x Internal Memory Map
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * Based on the MPC83xx header.
24 #ifndef __IMMAP_512x__
25 #define __IMMAP_512x__
27 #include <asm/types.h>
29 typedef struct law512x
{
30 u32 bar
; /* Base Addr Register */
31 u32 ar
; /* Attributes Register */
35 * System configuration registers
37 typedef struct sysconf512x
{
38 u32 immrbar
; /* Internal memory map base address register */
40 u32 lpbaw
; /* LP Boot Access Window */
41 u32 lpcs0aw
; /* LP CS0 Access Window */
42 u32 lpcs1aw
; /* LP CS1 Access Window */
43 u32 lpcs2aw
; /* LP CS2 Access Window */
44 u32 lpcs3aw
; /* LP CS3 Access Window */
45 u32 lpcs4aw
; /* LP CS4 Access Window */
46 u32 lpcs5aw
; /* LP CS5 Access Window */
47 u32 lpcs6aw
; /* LP CS6 Access Window */
48 u32 lpcs7aw
; /* LP CS7 Access Window */
50 law521x_t pcilaw
[3]; /* PCI Local Access Window 0-2 Registers */
52 law521x_t ddrlaw
; /* DDR Local Access Window */
54 u32 mbxbar
; /* MBX Base Address */
55 u32 srambar
; /* SRAM Base Address */
56 u32 nfcbar
; /* NFC Base Address */
58 u32 spridr
; /* System Part and Revision ID Register */
59 u32 spcr
; /* System Priority Configuration Register */
64 * Watch Dog Timer (WDT) Registers
66 typedef struct wdt512x
{
68 u32 swcrr
; /* System watchdog control register */
69 u32 swcnr
; /* System watchdog count register */
71 u16 swsrr
; /* System watchdog service register */
76 * RTC Module Registers
78 typedef struct rtclk512x
{
83 * General Purpose Timer
85 typedef struct gpt512x
{
90 * Integrated Programmable Interrupt Controller
92 typedef struct ipic512x
{
97 * System Arbiter Registers
99 typedef struct arbiter512x
{
100 u32 acr
; /* Arbiter Configuration Register */
101 u32 atr
; /* Arbiter Timers Register */
102 u32 ater
; /* Arbiter Transfer Error Register */
103 u32 aer
; /* Arbiter Event Register */
104 u32 aidr
; /* Arbiter Interrupt Definition Register */
105 u32 amr
; /* Arbiter Mask Register */
106 u32 aeatr
; /* Arbiter Event Attributes Register */
107 u32 aeadr
; /* Arbiter Event Address Register */
108 u32 aerr
; /* Arbiter Event Response Register */
115 typedef struct reset512x
{
116 u32 rcwl
; /* Reset Configuration Word Low Register */
117 u32 rcwh
; /* Reset Configuration Word High Register */
119 u32 rsr
; /* Reset Status Register */
120 u32 rmr
; /* Reset Mode Register */
121 u32 rpr
; /* Reset protection Register */
122 u32 rcr
; /* Reset Control Register */
123 u32 rcer
; /* Reset Control Enable Register */
130 typedef struct clk512x
{
131 u32 spmr
; /* System PLL Mode Register */
132 u32 sccr
[2]; /* System Clock Control Registers */
133 u32 scfr
[2]; /* System Clock Frequency Registers */
135 u32 bcr
; /* Bread Crumb Register */
136 u32 pscccr
[12]; /* PSC0-11 Clock Control Registers */
137 u32 spccr
; /* SPDIF Clock Control Registers */
138 u32 cccr
; /* CFM Clock Control Registers */
139 u32 dccr
; /* DIU Clock Control Registers */
144 * Power Management Control Module
146 typedef struct pmc512x
{
151 * General purpose I/O module
153 typedef struct gpio512x
{
158 * DDR Memory Controller Memory Map
160 typedef struct ddr512x
{
161 u32 ddr_sys_config
; /* System Configuration Register */
162 u32 ddr_time_config0
; /* Timing Configuration Register */
163 u32 ddr_time_config1
; /* Timing Configuration Register */
164 u32 ddr_time_config2
; /* Timing Configuration Register */
165 u32 ddr_command
; /* Command Register */
166 u32 ddr_compact_command
; /* Compact Command Register */
167 u32 self_refresh_cmd_0
; /* Enter/Exit Self Refresh Registers */
168 u32 self_refresh_cmd_1
; /* Enter/Exit Self Refresh Registers */
169 u32 self_refresh_cmd_2
; /* Enter/Exit Self Refresh Registers */
170 u32 self_refresh_cmd_3
; /* Enter/Exit Self Refresh Registers */
171 u32 self_refresh_cmd_4
; /* Enter/Exit Self Refresh Registers */
172 u32 self_refresh_cmd_5
; /* Enter/Exit Self Refresh Registers */
173 u32 self_refresh_cmd_6
; /* Enter/Exit Self Refresh Registers */
174 u32 self_refresh_cmd_7
; /* Enter/Exit Self Refresh Registers */
175 u32 DQS_config_offset_count
; /* DQS Config Offset Count */
176 u32 DQS_config_offset_time
; /* DQS Config Offset Time */
177 u32 DQS_delay_status
; /* DQS Delay Status */
179 u32 prioman_config1
; /* Priority Manager Configuration */
180 u32 prioman_config2
; /* Priority Manager Configuration */
181 u32 hiprio_config
; /* High Priority Configuration */
182 u32 lut_table0_main_upper
; /* LUT0 Main Upper */
183 u32 lut_table1_main_upper
; /* LUT1 Main Upper */
184 u32 lut_table2_main_upper
; /* LUT2 Main Upper */
185 u32 lut_table3_main_upper
; /* LUT3 Main Upper */
186 u32 lut_table4_main_upper
; /* LUT4 Main Upper */
187 u32 lut_table0_main_lower
; /* LUT0 Main Lower */
188 u32 lut_table1_main_lower
; /* LUT1 Main Lower */
189 u32 lut_table2_main_lower
; /* LUT2 Main Lower */
190 u32 lut_table3_main_lower
; /* LUT3 Main Lower */
191 u32 lut_table4_main_lower
; /* LUT4 Main Lower */
192 u32 lut_table0_alternate_upper
; /* LUT0 Alternate Upper */
193 u32 lut_table1_alternate_upper
; /* LUT1 Alternate Upper */
194 u32 lut_table2_alternate_upper
; /* LUT2 Alternate Upper */
195 u32 lut_table3_alternate_upper
; /* LUT3 Alternate Upper */
196 u32 lut_table4_alternate_upper
; /* LUT4 Alternate Upper */
197 u32 lut_table0_alternate_lower
; /* LUT0 Alternate Lower */
198 u32 lut_table1_alternate_lower
; /* LUT1 Alternate Lower */
199 u32 lut_table2_alternate_lower
; /* LUT2 Alternate Lower */
200 u32 lut_table3_alternate_lower
; /* LUT3 Alternate Lower */
201 u32 lut_table4_alternate_lower
; /* LUT4 Alternate Lower */
202 u32 performance_monitor_config
;
203 u32 event_time_counter
;
204 u32 event_time_preset
;
205 u32 performance_monitor1_address_low
;
206 u32 performance_monitor2_address_low
;
207 u32 performance_monitor1_address_hi
;
208 u32 performance_monitor2_address_hi
;
210 u32 performance_monitor1_read_counter
;
211 u32 performance_monitor2_read_counter
;
212 u32 performance_monitor1_write_counter
;
213 u32 performance_monitor2_write_counter
;
214 u32 granted_ack_counter0
;
215 u32 granted_ack_counter1
;
216 u32 granted_ack_counter2
;
217 u32 granted_ack_counter3
;
218 u32 granted_ack_counter4
;
219 u32 cumulative_wait_counter0
;
220 u32 cumulative_wait_counter1
;
221 u32 cumulative_wait_counter2
;
222 u32 cumulative_wait_counter3
;
223 u32 cumulative_wait_counter4
;
224 u32 summed_priority_counter0
;
225 u32 summed_priority_counter1
;
226 u32 summed_priority_counter2
;
227 u32 summed_priority_counter3
;
228 u32 summed_priority_counter4
;
236 typedef struct dma512x
{
241 * PCI Software Configuration Registers
243 typedef struct pciconf512x
{
250 typedef struct ios512x
{
257 typedef struct pcictrl512x
{
265 typedef struct mscan512x
{
272 typedef struct bdlc512x
{
279 typedef struct sdhc512x
{
286 typedef struct spdif512x
{
293 typedef struct i2c512x_dev
{
294 volatile u32 madr
; /* I2Cn + 0x00 */
295 volatile u32 mfdr
; /* I2Cn + 0x04 */
296 volatile u32 mcr
; /* I2Cn + 0x08 */
297 volatile u32 msr
; /* I2Cn + 0x0C */
298 volatile u32 mdr
; /* I2Cn + 0x10 */
302 typedef struct i2c512x
{
303 i2c512x_dev_t dev
[3];
312 typedef struct axe512x
{
319 typedef struct diu512x
{
326 typedef struct cfm512x
{
333 typedef struct fec512x
{
340 typedef struct ulpi512x
{
347 typedef struct utmi512x
{
354 typedef struct pcidma512x
{
361 typedef struct ioctrl512x
{
368 typedef struct iim512x
{
375 typedef struct lpc512x
{
376 u32 cs_cfg
[8]; /* Chip Select N Configuration Registers
377 No dedicated entry for CS Boot as == CS0 */
378 u32 cs_cr
; /* Chip Select Control Register */
379 u32 cs_sr
; /* Chip Select Status Register */
380 u32 cs_bcr
; /* Chip Select Burst Control Register */
381 u32 cs_dccr
; /* Chip Select Deadcycle Control Register */
382 u32 cs_hccr
; /* Chip Select Holdcycle Control Register */
384 u32 sclpc_psr
; /* SCLPC Packet Size Register */
385 u32 sclpc_sar
; /* SCLPC Start Address Register */
386 u32 sclpc_cr
; /* SCLPC Control Register */
387 u32 sclpc_er
; /* SCLPC Enable Register */
388 u32 sclpc_nar
; /* SCLPC NextAddress Register */
389 u32 sclpc_sr
; /* SCLPC Status Register */
390 u32 sclpc_bdr
; /* SCLPC Bytes Done Register */
391 u32 emb_scr
; /* EMB Share Counter Register */
392 u32 emb_pcr
; /* EMB Pause Control Register */
394 u32 lpc_fdwr
; /* LPC RX/TX FIFO Data Word Register */
395 u32 lpc_fsr
; /* LPC RX/TX FIFO Status Register */
396 u32 lpc_cr
; /* LPC RX/TX FIFO Control Register */
397 u32 lpc_ar
; /* LPC RX/TX FIFO Alarm Register */
404 typedef struct pata512x
{
411 typedef struct psc512x
{
412 volatile u8 mode
; /* PSC + 0x00 */
414 union { /* PSC + 0x04 */
416 volatile u16 clock_select
;
418 #define psc_status sr_csr.status
419 #define psc_clock_select sr_csr.clock_select
421 volatile u8 command
; /* PSC + 0x08 */
423 union { /* PSC + 0x0c */
424 volatile u8 buffer_8
;
425 volatile u16 buffer_16
;
426 volatile u32 buffer_32
;
428 #define psc_buffer_8 buffer.buffer_8
429 #define psc_buffer_16 buffer.buffer_16
430 #define psc_buffer_32 buffer.buffer_32
431 union { /* PSC + 0x10 */
435 #define psc_ipcr ipcr_acr.ipcr
436 #define psc_acr ipcr_acr.acr
438 union { /* PSC + 0x14 */
442 #define psc_isr isr_imr.isr
443 #define psc_imr isr_imr.imr
445 volatile u8 ctur
; /* PSC + 0x18 */
447 volatile u8 ctlr
; /* PSC + 0x1c */
449 volatile u32 ccr
; /* PSC + 0x20 */
450 volatile u8 res7
[12];
451 volatile u8 ivr
; /* PSC + 0x30 */
453 volatile u8 ip
; /* PSC + 0x34 */
455 volatile u8 op1
; /* PSC + 0x38 */
456 volatile u8 res10
[3];
457 volatile u8 op0
; /* PSC + 0x3c */
458 volatile u8 res11
[3];
459 volatile u32 sicr
; /* PSC + 0x40 */
460 volatile u8 res12
[60];
461 volatile u32 tfcmd
; /* PSC + 0x80 */
462 volatile u32 tfalarm
; /* PSC + 0x84 */
463 volatile u32 tfstat
; /* PSC + 0x88 */
464 volatile u32 tfintstat
; /* PSC + 0x8C */
465 volatile u32 tfintmask
; /* PSC + 0x90 */
466 volatile u32 tfcount
; /* PSC + 0x94 */
467 volatile u16 tfwptr
; /* PSC + 0x98 */
468 volatile u16 tfrptr
; /* PSC + 0x9A */
469 volatile u32 tfsize
; /* PSC + 0x9C */
470 volatile u8 res13
[28];
471 union { /* PSC + 0xBC */
472 volatile u8 buffer_8
;
473 volatile u16 buffer_16
;
474 volatile u32 buffer_32
;
476 #define tfdata_8 tfdata_buffer.buffer_8
477 #define tfdata_16 tfdata_buffer.buffer_16
478 #define tfdata_32 tfdata_buffer.buffer_32
480 volatile u32 rfcmd
; /* PSC + 0xC0 */
481 volatile u32 rfalarm
; /* PSC + 0xC4 */
482 volatile u32 rfstat
; /* PSC + 0xC8 */
483 volatile u32 rfintstat
; /* PSC + 0xCC */
484 volatile u32 rfintmask
; /* PSC + 0xD0 */
485 volatile u32 rfcount
; /* PSC + 0xD4 */
486 volatile u16 rfwptr
; /* PSC + 0xD8 */
487 volatile u16 rfrptr
; /* PSC + 0xDA */
488 volatile u32 rfsize
; /* PSC + 0xDC */
489 volatile u8 res18
[28];
490 union { /* PSC + 0xFC */
491 volatile u8 buffer_8
;
492 volatile u16 buffer_16
;
493 volatile u32 buffer_32
;
495 #define rfdata_8 rfdata_buffer.buffer_8
496 #define rfdata_16 rfdata_buffer.buffer_16
497 #define rfdata_32 rfdata_buffer.buffer_32
503 typedef struct fifoc512x
{
515 typedef struct sata512x
{
519 typedef struct immap
{
520 sysconf512x_t sysconf
; /* System configuration */
522 wdt512x_t wdt
; /* Watch Dog Timer (WDT) */
523 rtclk512x_t rtc
; /* Real Time Clock Module */
524 gpt512x_t gpt
; /* General Purpose Timer */
525 ipic512x_t ipic
; /* Integrated Programmable Interrupt Controller */
526 arbiter512x_t arbiter
; /* CSB Arbiter */
527 reset512x_t reset
; /* Reset Module */
528 clk512x_t clk
; /* Clock Module */
529 pmc512x_t pmc
; /* Power Management Control Module */
530 gpio512x_t gpio
; /* General purpose I/O module */
532 mscan512x_t mscan
; /* MSCAN */
533 bdlc512x_t bdlc
; /* BDLC */
534 sdhc512x_t sdhc
; /* SDHC */
535 spdif512x_t spdif
; /* SPDIF */
536 i2c512x_t i2c
; /* I2C Controllers */
538 axe512x_t axe
; /* AXE */
539 diu512x_t diu
; /* Display Interface Unit */
540 cfm512x_t cfm
; /* Clock Frequency Measurement */
542 fec512x_t fec
; /* Fast Ethernet Controller */
543 ulpi512x_t ulpi
; /* USB ULPI */
545 utmi512x_t utmi
; /* USB UTMI */
547 pcidma512x_t pci_dma
; /* PCI DMA */
548 pciconf512x_t pci_conf
; /* PCI Configuration */
550 ios512x_t ios
; /* PCI Sequencer */
551 pcictrl512x_t pci_ctrl
; /* PCI Controller Control and Status */
553 ddr512x_t mddrc
; /* Multi-port DDR Memory Controller */
554 ioctrl512x_t io_ctrl
; /* IO Control */
555 iim512x_t iim
; /* IC Identification module */
557 lpc512x_t lpc
; /* LocalPlus Controller */
558 pata512x_t pata
; /* Parallel ATA */
560 psc512x_t psc
[12]; /* PSCs */
562 fifoc512x_t fifoc
; /* FIFO Controller */
564 dma512x_t dma
; /* DMA */
566 sata512x_t sata
; /* Serial ATA */
569 #endif /* __IMMAP_512x__ */