]>
git.ipfire.org Git - people/ms/u-boot.git/blob - include/asm-ppc/ppc4xx-sdram.h
992a3d22105a1c70e3b5355130c38b51ef27d646
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifndef _PPC4xx_SDRAM_H_
25 #define _PPC4xx_SDRAM_H_
27 #if defined(CONFIG_SDRAM_PPC4xx_IBM_SDRAM)
34 * XXX - ToDo: Revisit file to change all these lower case defines into
35 * upper case. Also needs to be done in the controller setup code too
36 * of course. sr, 2008-06-02
39 #define mem_besra 0x00 /* bus error syndrome reg a */
40 #define mem_besrsa 0x04 /* bus error syndrome reg set a */
41 #define mem_besrb 0x08 /* bus error syndrome reg b */
42 #define mem_besrsb 0x0c /* bus error syndrome reg set b */
43 #define mem_bear 0x10 /* bus error address reg */
45 #define mem_mcopt1 0x20 /* memory controller options 1 */
46 #define mem_status 0x24 /* memory status */
47 #define mem_rtr 0x30 /* refresh timer reg */
48 #define mem_pmit 0x34 /* power management idle timer */
49 #define mem_mb0cf 0x40 /* memory bank 0 configuration */
50 #define mem_mb1cf 0x44 /* memory bank 1 configuration */
52 #define mem_mb2cf 0x48 /* memory bank 2 configuration */
53 #define mem_mb3cf 0x4c /* memory bank 3 configuration */
55 #define mem_sdtr1 0x80 /* timing reg 1 */
57 #define mem_ecccf 0x94 /* ECC configuration */
58 #define mem_eccerr 0x98 /* ECC error status */
61 #endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */
63 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
66 * Memory controller registers
68 #define SDRAM_CFG0 0x20 /* memory controller options 0 */
69 #define SDRAM_CFG1 0x21 /* memory controller options 1 */
72 * XXX - ToDo: Revisit file to change all these lower case defines into
73 * upper case. Also needs to be done in the controller setup code too
74 * of course. sr, 2008-06-02
76 #define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
77 #define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
78 #define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */
79 #define mem_besr1_set 0x000c /* bus error status reg 1 (set) */
80 #define mem_bear 0x0010 /* bus error address reg */
81 #define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */
82 #define mem_mirq_set 0x0012 /* bus master interrupt (set) */
83 #define mem_slio 0x0018 /* ddr sdram slave interface options */
84 #define mem_cfg0 0x0020 /* ddr sdram options 0 */
85 #define mem_cfg1 0x0021 /* ddr sdram options 1 */
86 #define mem_devopt 0x0022 /* ddr sdram device options */
87 #define mem_mcsts 0x0024 /* memory controller status */
88 #define mem_rtr 0x0030 /* refresh timer register */
89 #define mem_pmit 0x0034 /* power management idle timer */
90 #define mem_uabba 0x0038 /* plb UABus base address */
91 #define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */
92 #define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */
93 #define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */
94 #define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */
95 #define mem_tr0 0x0080 /* sdram timing register 0 */
96 #define mem_tr1 0x0081 /* sdram timing register 1 */
97 #define mem_clktr 0x0082 /* ddr clock timing register */
98 #define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */
99 #define mem_dlycal 0x0084 /* delay line calibration register */
100 #define mem_eccesr 0x0098 /* ECC error status */
103 * Memory Controller Options 0
105 #define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
106 #define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
107 #define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
108 #define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
109 #define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
110 #define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
111 #define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
112 #define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
113 #define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
114 #define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
115 #define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
116 #define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
119 * Memory Controller Options 1
121 #define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
122 #define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
125 * SDRAM DEVPOT Options
127 #define SDRAM_DEVOPT_DLL 0x80000000
128 #define SDRAM_DEVOPT_DS 0x40000000
131 * SDRAM MCSTS Options
133 #define SDRAM_MCSTS_MRSC 0x80000000
134 #define SDRAM_MCSTS_SRMS 0x40000000
135 #define SDRAM_MCSTS_CIS 0x20000000
138 * SDRAM Refresh Timer Register
140 #define SDRAM_RTR_RINT_MASK 0xFFFF0000
141 #define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
144 * SDRAM UABus Base Address Reg
146 #define SDRAM_UABBA_UBBA_MASK 0x0000000F
149 * Memory Bank 0-7 configuration
151 #define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
152 #define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
153 #define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
154 #define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
155 #define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
156 #define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
157 #define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
158 #define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
159 #define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
160 #define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
161 #define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
162 #define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
163 #define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
164 #define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
165 #define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
170 #define SDRAM_TR0_SDWR_MASK 0x80000000
171 #define SDRAM_TR0_SDWR_2_CLK 0x00000000
172 #define SDRAM_TR0_SDWR_3_CLK 0x80000000
173 #define SDRAM_TR0_SDWD_MASK 0x40000000
174 #define SDRAM_TR0_SDWD_0_CLK 0x00000000
175 #define SDRAM_TR0_SDWD_1_CLK 0x40000000
176 #define SDRAM_TR0_SDCL_MASK 0x01800000
177 #define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
178 #define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
179 #define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
180 #define SDRAM_TR0_SDPA_MASK 0x000C0000
181 #define SDRAM_TR0_SDPA_2_CLK 0x00040000
182 #define SDRAM_TR0_SDPA_3_CLK 0x00080000
183 #define SDRAM_TR0_SDPA_4_CLK 0x000C0000
184 #define SDRAM_TR0_SDCP_MASK 0x00030000
185 #define SDRAM_TR0_SDCP_2_CLK 0x00000000
186 #define SDRAM_TR0_SDCP_3_CLK 0x00010000
187 #define SDRAM_TR0_SDCP_4_CLK 0x00020000
188 #define SDRAM_TR0_SDCP_5_CLK 0x00030000
189 #define SDRAM_TR0_SDLD_MASK 0x0000C000
190 #define SDRAM_TR0_SDLD_1_CLK 0x00000000
191 #define SDRAM_TR0_SDLD_2_CLK 0x00004000
192 #define SDRAM_TR0_SDRA_MASK 0x0000001C
193 #define SDRAM_TR0_SDRA_6_CLK 0x00000000
194 #define SDRAM_TR0_SDRA_7_CLK 0x00000004
195 #define SDRAM_TR0_SDRA_8_CLK 0x00000008
196 #define SDRAM_TR0_SDRA_9_CLK 0x0000000C
197 #define SDRAM_TR0_SDRA_10_CLK 0x00000010
198 #define SDRAM_TR0_SDRA_11_CLK 0x00000014
199 #define SDRAM_TR0_SDRA_12_CLK 0x00000018
200 #define SDRAM_TR0_SDRA_13_CLK 0x0000001C
201 #define SDRAM_TR0_SDRD_MASK 0x00000003
202 #define SDRAM_TR0_SDRD_2_CLK 0x00000001
203 #define SDRAM_TR0_SDRD_3_CLK 0x00000002
204 #define SDRAM_TR0_SDRD_4_CLK 0x00000003
209 #define SDRAM_TR1_RDSS_MASK 0xC0000000
210 #define SDRAM_TR1_RDSS_TR0 0x00000000
211 #define SDRAM_TR1_RDSS_TR1 0x40000000
212 #define SDRAM_TR1_RDSS_TR2 0x80000000
213 #define SDRAM_TR1_RDSS_TR3 0xC0000000
214 #define SDRAM_TR1_RDSL_MASK 0x00C00000
215 #define SDRAM_TR1_RDSL_STAGE1 0x00000000
216 #define SDRAM_TR1_RDSL_STAGE2 0x00400000
217 #define SDRAM_TR1_RDSL_STAGE3 0x00800000
218 #define SDRAM_TR1_RDCD_MASK 0x00000800
219 #define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
220 #define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
221 #define SDRAM_TR1_RDCT_MASK 0x000001FF
222 #define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
223 #define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
224 #define SDRAM_TR1_RDCT_MIN 0x00000000
225 #define SDRAM_TR1_RDCT_MAX 0x000001FF
228 * SDRAM WDDCTR Options
230 #define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
231 #define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
232 #define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
233 #define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
234 #define SDRAM_WDDCTR_DCD_MASK 0x000001FF
237 * SDRAM CLKTR Options
239 #define SDRAM_CLKTR_CLKP_MASK 0xC0000000
240 #define SDRAM_CLKTR_CLKP_0DEG 0x00000000
241 #define SDRAM_CLKTR_CLKP_90DEG 0x40000000
242 #define SDRAM_CLKTR_CLKP_180DEG 0x80000000
243 #define SDRAM_CLKTR_DCDT_MASK 0x000001FF
246 * SDRAM DLYCAL Options
248 #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
249 #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
250 #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
252 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR */
254 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
256 #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
257 #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
258 #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
260 #if !defined(CONFIG_405EX)
262 * Memory queue defines
264 #define SDRAMQ_DCR_BASE 0x040
266 #define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
267 #define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
268 #define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
269 #define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
270 #define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
271 #define SDRAM_CONF1HB_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */
272 #define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */
273 #define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */
274 #define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */
275 #define SDRAM_CONF1HB_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */
276 #define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */
277 #define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */
278 #define SDRAM_CONF1HB_WRCL 0x00000080 /* MCIF Cycle Limit 1 - Bits 22..24 */
279 #define SDRAM_CONF1HB_MASK 0x0000F380 /* RPLM & WRCL mask */
281 #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
282 #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
283 #define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
284 #define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
285 #define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
286 #define SDRAM_CONF1LL_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */
287 #define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */
288 #define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */
289 #define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */
290 #define SDRAM_CONF1LL_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */
291 #define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */
292 #define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */
293 #define SDRAM_CONF1LL_MASK 0x0000F000 /* RPLM mask */
295 #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
296 #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
297 #define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
298 #define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
299 #define SDRAM_CONFPATHB_TPEN 0x08000000 /* Transaction Passing Enable - Bit 4 */
301 #define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
304 * Memory Bank 0-7 configuration
306 #if defined(CONFIG_440SPE) || \
307 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
308 defined(CONFIG_460SX)
309 #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
310 #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
311 #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2)
312 #endif /* CONFIG_440SPE */
313 #if defined(CONFIG_440SP)
314 #define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
315 #define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFF800000))
316 #define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFF800000))
317 #endif /* CONFIG_440SP */
318 #define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
319 #define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((u32)(n))&0x3FF)<<6)
320 #define SDRAM_RXBAS_SDSZ_DECODE(n) ((((u32)(n))>>6)&0x3FF)
321 #define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */
322 #define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */
323 #define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */
324 #define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */
325 #define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */
326 #define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */
327 #define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */
328 #define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */
329 #define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */
330 #define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */
331 #define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */
332 #else /* CONFIG_405EX */
335 * Revisit this file to check if all these 405EX defines are correct and
336 * can be used in the common 44x_spd_ddr2 code as well. sr, 2008-06-02
338 #define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF)
339 #define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0)
340 #define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1)
341 #define SDRAM_RXBAS_SDSZ_16MB PPC_REG_VAL(19, 0x2)
342 #define SDRAM_RXBAS_SDSZ_32MB PPC_REG_VAL(19, 0x3)
343 #define SDRAM_RXBAS_SDSZ_64MB PPC_REG_VAL(19, 0x4)
344 #define SDRAM_RXBAS_SDSZ_128MB PPC_REG_VAL(19, 0x5)
345 #define SDRAM_RXBAS_SDSZ_256MB PPC_REG_VAL(19, 0x6)
346 #define SDRAM_RXBAS_SDSZ_512MB PPC_REG_VAL(19, 0x7)
347 #define SDRAM_RXBAS_SDSZ_1024MB PPC_REG_VAL(19, 0x8)
348 #define SDRAM_RXBAS_SDSZ_2048MB PPC_REG_VAL(19, 0x9)
349 #define SDRAM_RXBAS_SDSZ_4096MB PPC_REG_VAL(19, 0xA)
350 #define SDRAM_RXBAS_SDSZ_8192MB PPC_REG_VAL(19, 0xB)
351 #define SDRAM_RXBAS_SDSZ_8 SDRAM_RXBAS_SDSZ_8MB
352 #define SDRAM_RXBAS_SDSZ_16 SDRAM_RXBAS_SDSZ_16MB
353 #define SDRAM_RXBAS_SDSZ_32 SDRAM_RXBAS_SDSZ_32MB
354 #define SDRAM_RXBAS_SDSZ_64 SDRAM_RXBAS_SDSZ_64MB
355 #define SDRAM_RXBAS_SDSZ_128 SDRAM_RXBAS_SDSZ_128MB
356 #define SDRAM_RXBAS_SDSZ_256 SDRAM_RXBAS_SDSZ_256MB
357 #define SDRAM_RXBAS_SDSZ_512 SDRAM_RXBAS_SDSZ_512MB
358 #define SDRAM_RXBAS_SDSZ_1024 SDRAM_RXBAS_SDSZ_1024MB
359 #define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB
360 #define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB
361 #define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB
362 #define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0)
363 #define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1)
364 #define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2)
365 #define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3)
366 #define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4)
367 #define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5)
368 #define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6)
369 #define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7)
370 #define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8)
371 #define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9)
372 #define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0)
373 #define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1)
374 #endif /* CONFIG_405EX */
377 * Memory controller registers
379 #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
380 #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
381 #define SDRAM_BEARL 0x02 /* PLB bus error address low */
382 #define SDRAM_BEARH 0x03 /* PLB bus error address high */
383 #define SDRAM_WMIRQ 0x06 /* PLB write master interrupt (read/clear) */
384 #define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */
385 #define SDRAM_PLBOPT 0x08 /* PLB slave options */
386 #define SDRAM_PUABA 0x09 /* PLB upper address base */
388 #define SDRAM_MCSTAT 0x14 /* memory controller status */
390 #define SDRAM_MCSTAT 0x1F /* memory controller status */
392 #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
393 #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
394 #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
395 #define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
396 #define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
397 #define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
398 #define SDRAM_CODT 0x26 /* on die termination for controller */
399 #define SDRAM_VVPR 0x27 /* variable VRef programmming */
400 #define SDRAM_OPARS 0x28 /* on chip driver control setup */
401 #define SDRAM_OPART 0x29 /* on chip driver control trigger */
402 #define SDRAM_RTR 0x30 /* refresh timer */
403 #define SDRAM_PMIT 0x34 /* power management idle timer */
404 #define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
405 #define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
406 #define SDRAM_MB2CF 0x48
407 #define SDRAM_MB3CF 0x4C
408 #define SDRAM_INITPLR0 0x50 /* manual initialization control */
409 #define SDRAM_INITPLR1 0x51 /* manual initialization control */
410 #define SDRAM_INITPLR2 0x52 /* manual initialization control */
411 #define SDRAM_INITPLR3 0x53 /* manual initialization control */
412 #define SDRAM_INITPLR4 0x54 /* manual initialization control */
413 #define SDRAM_INITPLR5 0x55 /* manual initialization control */
414 #define SDRAM_INITPLR6 0x56 /* manual initialization control */
415 #define SDRAM_INITPLR7 0x57 /* manual initialization control */
416 #define SDRAM_INITPLR8 0x58 /* manual initialization control */
417 #define SDRAM_INITPLR9 0x59 /* manual initialization control */
418 #define SDRAM_INITPLR10 0x5a /* manual initialization control */
419 #define SDRAM_INITPLR11 0x5b /* manual initialization control */
420 #define SDRAM_INITPLR12 0x5c /* manual initialization control */
421 #define SDRAM_INITPLR13 0x5d /* manual initialization control */
422 #define SDRAM_INITPLR14 0x5e /* manual initialization control */
423 #define SDRAM_INITPLR15 0x5f /* manual initialization control */
424 #define SDRAM_RQDC 0x70 /* read DQS delay control */
425 #define SDRAM_RFDC 0x74 /* read feedback delay control */
426 #define SDRAM_RDCC 0x78 /* read data capture control */
427 #define SDRAM_DLCR 0x7A /* delay line calibration */
428 #define SDRAM_CLKTR 0x80 /* DDR clock timing */
429 #define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
430 #define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
431 #define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
432 #define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
433 #define SDRAM_MMODE 0x88 /* memory mode */
434 #define SDRAM_MEMODE 0x89 /* memory extended mode */
435 #define SDRAM_ECCCR 0x98 /* ECC error status */
436 #define SDRAM_ECCES SDRAM_ECCCR
437 #define SDRAM_CID 0xA4 /* core ID */
439 #define SDRAM_RID 0xA8 /* revision ID */
441 #define SDRAM_FCSR 0xB0 /* feedback calibration status */
442 #define SDRAM_RTSR 0xB1 /* run time status tracking */
444 #define SDRAM_RID 0xF8 /* revision ID */
448 * Memory Controller Bus Error Status
450 #define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF)
451 #define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF)
452 #define SDRAM_BESR_M0ID_ICU PPC_REG_VAL(3, 0x0)
453 #define SDRAM_BESR_M0ID_PCIE0 PPC_REG_VAL(3, 0x1)
454 #define SDRAM_BESR_M0ID_PCIE1 PPC_REG_VAL(3, 0x2)
455 #define SDRAM_BESR_M0ID_DMA PPC_REG_VAL(3, 0x3)
456 #define SDRAM_BESR_M0ID_DCU PPC_REG_VAL(3, 0x4)
457 #define SDRAM_BESR_M0ID_OPB PPC_REG_VAL(3, 0x5)
458 #define SDRAM_BESR_M0ID_MAL PPC_REG_VAL(3, 0x6)
459 #define SDRAM_BESR_M0ID_SEC PPC_REG_VAL(3, 0x7)
460 #define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7)
461 #define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0x0)
462 #define SDRAM_BESR_M0ET_ECC PPC_REG_VAL(6, 0x1)
463 #define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0)
464 #define SDRAM_BESR_M0RW_READ PPC_REG_VAL(8, 1)
467 * Memory Controller Status
469 #define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
470 #define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
471 #define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
472 #define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */
473 #define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
474 #define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */
475 #define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */
476 #define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */
477 #define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */
480 * Memory Controller Options 1
482 #define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/
483 #define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
484 #define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
485 #define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
486 #define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
487 #define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((u32)(n))>>28)&0x3)
488 #define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
489 #define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
490 #define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
491 #define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
492 #define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
493 #define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
494 #define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
495 #define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
496 #define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
497 #define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
498 #define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
499 #define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
500 #define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
501 #define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
502 #define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
503 #define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
504 #define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
505 #define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
506 #define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
507 #define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
508 #define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
509 #define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
510 #define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
511 #define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
512 #define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
513 #define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
514 #define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
515 #define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
516 #define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
519 * Memory Controller Options 2
521 #define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
522 #define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
523 #define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
524 #define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
525 #define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
526 #define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
527 #define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
528 #define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
529 #define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
530 #define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
531 #define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
532 #define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
533 #define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
534 #define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
535 #define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
536 #define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
537 #define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
538 #define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
541 * SDRAM Refresh Timer Register
543 #define SDRAM_RTR_RINT_MASK 0xFFF80000
544 #define SDRAM_RTR_RINT_ENCODE(n) ((((u32)(n))&0xFFF8)<<16)
545 #define SDRAM_RTR_RINT_DECODE(n) ((((u32)(n))>>16)&0xFFF8)
548 * SDRAM Read DQS Delay Control Register
550 #define SDRAM_RQDC_RQDE_MASK 0x80000000
551 #define SDRAM_RQDC_RQDE_DISABLE 0x00000000
552 #define SDRAM_RQDC_RQDE_ENABLE 0x80000000
553 #define SDRAM_RQDC_RQFD_MASK 0x000001FF
554 #define SDRAM_RQDC_RQFD_ENCODE(n) ((((u32)(n))&0x1FF)<<0)
556 #define SDRAM_RQDC_RQFD_MAX 0x1FF
559 * SDRAM Read Data Capture Control Register
561 #define SDRAM_RDCC_RDSS_MASK 0xC0000000
562 #define SDRAM_RDCC_RDSS_T1 0x00000000
563 #define SDRAM_RDCC_RDSS_T2 0x40000000
564 #define SDRAM_RDCC_RDSS_T3 0x80000000
565 #define SDRAM_RDCC_RDSS_T4 0xC0000000
566 #define SDRAM_RDCC_RSAE_MASK 0x00000001
567 #define SDRAM_RDCC_RSAE_DISABLE 0x00000001
568 #define SDRAM_RDCC_RSAE_ENABLE 0x00000000
569 #define SDRAM_RDCC_RDSS_ENCODE(n) ((((u32)(n))&0x03)<<30)
570 #define SDRAM_RDCC_RDSS_DECODE(n) ((((u32)(n))>>30)&0x03)
573 * SDRAM Read Feedback Delay Control Register
575 #define SDRAM_RFDC_ARSE_MASK 0x80000000
576 #define SDRAM_RFDC_ARSE_DISABLE 0x80000000
577 #define SDRAM_RFDC_ARSE_ENABLE 0x00000000
578 #define SDRAM_RFDC_RFOS_MASK 0x007F0000
579 #define SDRAM_RFDC_RFOS_ENCODE(n) ((((u32)(n))&0x7F)<<16)
580 #define SDRAM_RFDC_RFFD_MASK 0x000007FF
581 #define SDRAM_RFDC_RFFD_ENCODE(n) ((((u32)(n))&0x7FF)<<0)
583 #define SDRAM_RFDC_RFFD_MAX 0x7FF
586 * SDRAM Delay Line Calibration Register
588 #define SDRAM_DLCR_DCLM_MASK 0x80000000
589 #define SDRAM_DLCR_DCLM_MANUAL 0x80000000
590 #define SDRAM_DLCR_DCLM_AUTO 0x00000000
591 #define SDRAM_DLCR_DLCR_MASK 0x08000000
592 #define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
593 #define SDRAM_DLCR_DLCR_IDLE 0x00000000
594 #define SDRAM_DLCR_DLCS_MASK 0x07000000
595 #define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
596 #define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
597 #define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
598 #define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
599 #define SDRAM_DLCR_DLCS_ERROR 0x04000000
600 #define SDRAM_DLCR_DLCV_MASK 0x000001FF
601 #define SDRAM_DLCR_DLCV_ENCODE(n) ((((u32)(n))&0x1FF)<<0)
602 #define SDRAM_DLCR_DLCV_DECODE(n) ((((u32)(n))>>0)&0x1FF)
605 * SDRAM Memory On Die Terimination Control Register
607 #define SDRAM_MODT_ODTON_DISABLE PPC_REG_VAL(0, 0)
608 #define SDRAM_MODT_ODTON_ENABLE PPC_REG_VAL(0, 1)
609 #define SDRAM_MODT_EB1W_DISABLE PPC_REG_VAL(1, 0)
610 #define SDRAM_MODT_EB1W_ENABLE PPC_REG_VAL(1, 1)
611 #define SDRAM_MODT_EB1R_DISABLE PPC_REG_VAL(2, 0)
612 #define SDRAM_MODT_EB1R_ENABLE PPC_REG_VAL(2, 1)
613 #define SDRAM_MODT_EB0W_DISABLE PPC_REG_VAL(7, 0)
614 #define SDRAM_MODT_EB0W_ENABLE PPC_REG_VAL(7, 1)
615 #define SDRAM_MODT_EB0R_DISABLE PPC_REG_VAL(8, 0)
616 #define SDRAM_MODT_EB0R_ENABLE PPC_REG_VAL(8, 1)
619 * SDRAM Controller On Die Termination Register
621 #define SDRAM_CODT_ODT_ON PPC_REG_VAL(0, 1)
622 #define SDRAM_CODT_ODT_OFF PPC_REG_VAL(0, 0)
623 #define SDRAM_CODT_RK1W_ON PPC_REG_VAL(1, 1)
624 #define SDRAM_CODT_RK1W_OFF PPC_REG_VAL(1, 0)
625 #define SDRAM_CODT_RK1R_ON PPC_REG_VAL(2, 1)
626 #define SDRAM_CODT_RK1R_OFF PPC_REG_VAL(2, 0)
627 #define SDRAM_CODT_RK0W_ON PPC_REG_VAL(7, 1)
628 #define SDRAM_CODT_RK0W_OFF PPC_REG_VAL(7, 0)
629 #define SDRAM_CODT_RK0R_ON PPC_REG_VAL(8, 1)
630 #define SDRAM_CODT_RK0R_OFF PPC_REG_VAL(8, 0)
631 #define SDRAM_CODT_ODTSH_NORMAL PPC_REG_VAL(10, 0)
632 #define SDRAM_CODT_ODTSH_REMOVE_ONE_AT_END PPC_REG_VAL(10, 1)
633 #define SDRAM_CODT_ODTSH_ADD_ONE_AT_START PPC_REG_VAL(10, 2)
634 #define SDRAM_CODT_ODTSH_SHIFT_ONE_EARLIER PPC_REG_VAL(10, 3)
635 #define SDRAM_CODT_CODTZ_75OHM PPC_REG_VAL(11, 0)
636 #define SDRAM_CODT_CKEG_ON PPC_REG_VAL(12, 1)
637 #define SDRAM_CODT_CKEG_OFF PPC_REG_VAL(12, 0)
638 #define SDRAM_CODT_CTLG_ON PPC_REG_VAL(13, 1)
639 #define SDRAM_CODT_CTLG_OFF PPC_REG_VAL(13, 0)
640 #define SDRAM_CODT_FBDG_ON PPC_REG_VAL(14, 1)
641 #define SDRAM_CODT_FBDG_OFF PPC_REG_VAL(14, 0)
642 #define SDRAM_CODT_FBRG_ON PPC_REG_VAL(15, 1)
643 #define SDRAM_CODT_FBRG_OFF PPC_REG_VAL(15, 0)
644 #define SDRAM_CODT_CKLZ_36OHM PPC_REG_VAL(18, 1)
645 #define SDRAM_CODT_CKLZ_18OHM PPC_REG_VAL(18, 0)
646 #define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK PPC_REG_VAL(26, 1)
647 #define SDRAM_CODT_DQS_2_5_V_DDR1 PPC_REG_VAL(26, 0)
648 #define SDRAM_CODT_DQS_1_8_V_DDR2 PPC_REG_VAL(26, 1)
649 #define SDRAM_CODT_DQS_MASK PPC_REG_VAL(27, 1)
650 #define SDRAM_CODT_DQS_DIFFERENTIAL PPC_REG_VAL(27, 0)
651 #define SDRAM_CODT_DQS_SINGLE_END PPC_REG_VAL(27, 1)
652 #define SDRAM_CODT_CKSE_DIFFERENTIAL PPC_REG_VAL(28, 0)
653 #define SDRAM_CODT_CKSE_SINGLE_END PPC_REG_VAL(28, 1)
654 #define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END PPC_REG_VAL(29, 1)
655 #define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END PPC_REG_VAL(30, 1)
656 #define SDRAM_CODT_IO_HIZ PPC_REG_VAL(31, 0)
657 #define SDRAM_CODT_IO_NMODE PPC_REG_VAL(31, 1)
660 * SDRAM Initialization Preload Register
662 #define SDRAM_INITPLR_ENABLE PPC_REG_VAL(0, 1)
663 #define SDRAM_INITPLR_DISABLE PPC_REG_VAL(0, 0)
664 #define SDRAM_INITPLR_IMWT_MASK PPC_REG_VAL(8, 0xFF)
665 #define SDRAM_INITPLR_IMWT_ENCODE(n) PPC_REG_VAL(8, \
669 #define SDRAM_INITPLR_ICMD_MASK PPC_REG_VAL(12, 0x7)
670 #define SDRAM_INITPLR_ICMD_ENCODE(n) PPC_REG_VAL(12, \
674 #define SDRAM_INITPLR_IBA_MASK PPC_REG_VAL(15, 0x7)
675 #define SDRAM_INITPLR_IBA_ENCODE(n) PPC_REG_VAL(15, \
679 #define SDRAM_INITPLR_IMA_MASK PPC_REG_VAL(31, 0x7FFF)
680 #define SDRAM_INITPLR_IMA_ENCODE(n) PPC_REG_VAL(31, \
686 * JEDEC DDR Initialization Commands
688 #define JEDEC_CMD_NOP 7
689 #define JEDEC_CMD_PRECHARGE 2
690 #define JEDEC_CMD_REFRESH 1
691 #define JEDEC_CMD_EMR 0
692 #define JEDEC_CMD_READ 5
693 #define JEDEC_CMD_WRITE 4
696 * JEDEC Precharge Command Memory Address Arguments
698 #define JEDEC_MA_PRECHARGE_ONE (0 << 10)
699 #define JEDEC_MA_PRECHARGE_ALL (1 << 10)
702 * JEDEC DDR EMR Command Bank Address Arguments
704 #define JEDEC_BA_MR 0
705 #define JEDEC_BA_EMR 1
706 #define JEDEC_BA_EMR2 2
707 #define JEDEC_BA_EMR3 3
710 * JEDEC DDR Mode Register
712 #define JEDEC_MA_MR_PDMODE_FAST_EXIT (0 << 12)
713 #define JEDEC_MA_MR_PDMODE_SLOW_EXIT (1 << 12)
714 #define JEDEC_MA_MR_WR_MASK (0x7 << 9)
715 #define JEDEC_MA_MR_WR_DDR1 (0x0 << 9)
716 #define JEDEC_MA_MR_WR_DDR2_2_CYC (0x1 << 9)
717 #define JEDEC_MA_MR_WR_DDR2_3_CYC (0x2 << 9)
718 #define JEDEC_MA_MR_WR_DDR2_4_CYC (0x3 << 9)
719 #define JEDEC_MA_MR_WR_DDR2_5_CYC (0x4 << 9)
720 #define JEDEC_MA_MR_WR_DDR2_6_CYC (0x5 << 9)
721 #define JEDEC_MA_MR_DLL_RESET (1 << 8)
722 #define JEDEC_MA_MR_MODE_NORMAL (0 << 8)
723 #define JEDEC_MA_MR_MODE_TEST (1 << 8)
724 #define JEDEC_MA_MR_CL_MASK (0x7 << 4)
725 #define JEDEC_MA_MR_CL_DDR1_2_0_CLK (0x2 << 4)
726 #define JEDEC_MA_MR_CL_DDR1_2_5_CLK (0x6 << 4)
727 #define JEDEC_MA_MR_CL_DDR1_3_0_CLK (0x3 << 4)
728 #define JEDEC_MA_MR_CL_DDR2_2_0_CLK (0x2 << 4)
729 #define JEDEC_MA_MR_CL_DDR2_3_0_CLK (0x3 << 4)
730 #define JEDEC_MA_MR_CL_DDR2_4_0_CLK (0x4 << 4)
731 #define JEDEC_MA_MR_CL_DDR2_5_0_CLK (0x5 << 4)
732 #define JEDEC_MA_MR_CL_DDR2_6_0_CLK (0x6 << 4)
733 #define JEDEC_MA_MR_CL_DDR2_7_0_CLK (0x7 << 4)
734 #define JEDEC_MA_MR_BTYP_SEQUENTIAL (0 << 3)
735 #define JEDEC_MA_MR_BTYP_INTERLEAVED (1 << 3)
736 #define JEDEC_MA_MR_BLEN_MASK (0x7 << 0)
737 #define JEDEC_MA_MR_BLEN_4 (2 << 0)
738 #define JEDEC_MA_MR_BLEN_8 (3 << 0)
741 * JEDEC DDR Extended Mode Register
743 #define JEDEC_MA_EMR_OUTPUT_MASK (1 << 12)
744 #define JEDEC_MA_EMR_OUTPUT_ENABLE (0 << 12)
745 #define JEDEC_MA_EMR_OUTPUT_DISABLE (1 << 12)
746 #define JEDEC_MA_EMR_RQDS_MASK (1 << 11)
747 #define JEDEC_MA_EMR_RDQS_DISABLE (0 << 11)
748 #define JEDEC_MA_EMR_RDQS_ENABLE (1 << 11)
749 #define JEDEC_MA_EMR_DQS_MASK (1 << 10)
750 #define JEDEC_MA_EMR_DQS_DISABLE (1 << 10)
751 #define JEDEC_MA_EMR_DQS_ENABLE (0 << 10)
752 #define JEDEC_MA_EMR_OCD_MASK (0x7 << 7)
753 #define JEDEC_MA_EMR_OCD_EXIT (0 << 7)
754 #define JEDEC_MA_EMR_OCD_ENTER (7 << 7)
755 #define JEDEC_MA_EMR_AL_DDR1_0_CYC (0 << 3)
756 #define JEDEC_MA_EMR_AL_DDR2_1_CYC (1 << 3)
757 #define JEDEC_MA_EMR_AL_DDR2_2_CYC (2 << 3)
758 #define JEDEC_MA_EMR_AL_DDR2_3_CYC (3 << 3)
759 #define JEDEC_MA_EMR_AL_DDR2_4_CYC (4 << 3)
760 #define JEDEC_MA_EMR_RTT_MASK (0x11 << 2)
761 #define JEDEC_MA_EMR_RTT_DISABLED (0x00 << 2)
762 #define JEDEC_MA_EMR_RTT_75OHM (0x01 << 2)
763 #define JEDEC_MA_EMR_RTT_150OHM (0x10 << 2)
764 #define JEDEC_MA_EMR_RTT_50OHM (0x11 << 2)
765 #define JEDEC_MA_EMR_ODS_MASK (1 << 1)
766 #define JEDEC_MA_EMR_ODS_NORMAL (0 << 1)
767 #define JEDEC_MA_EMR_ODS_WEAK (1 << 1)
768 #define JEDEC_MA_EMR_DLL_MASK (1 << 0)
769 #define JEDEC_MA_EMR_DLL_ENABLE (0 << 0)
770 #define JEDEC_MA_EMR_DLL_DISABLE (1 << 0)
773 * JEDEC DDR Extended Mode Register 2
775 #define JEDEC_MA_EMR2_TEMP_COMMERCIAL (0 << 7)
776 #define JEDEC_MA_EMR2_TEMP_INDUSTRIAL (1 << 7)
779 * SDRAM Mode Register (Corresponds 1:1 w/ JEDEC Mode Register)
781 #define SDRAM_MMODE_WR_MASK JEDEC_MA_MR_WR_MASK
782 #define SDRAM_MMODE_WR_DDR1 JEDEC_MA_MR_WR_DDR1
783 #define SDRAM_MMODE_WR_DDR2_2_CYC JEDEC_MA_MR_WR_DDR2_2_CYC
784 #define SDRAM_MMODE_WR_DDR2_3_CYC JEDEC_MA_MR_WR_DDR2_3_CYC
785 #define SDRAM_MMODE_WR_DDR2_4_CYC JEDEC_MA_MR_WR_DDR2_4_CYC
786 #define SDRAM_MMODE_WR_DDR2_5_CYC JEDEC_MA_MR_WR_DDR2_5_CYC
787 #define SDRAM_MMODE_WR_DDR2_6_CYC JEDEC_MA_MR_WR_DDR2_6_CYC
788 #define SDRAM_MMODE_DCL_MASK JEDEC_MA_MR_CL_MASK
789 #define SDRAM_MMODE_DCL_DDR1_2_0_CLK JEDEC_MA_MR_CL_DDR1_2_0_CLK
790 #define SDRAM_MMODE_DCL_DDR1_2_5_CLK JEDEC_MA_MR_CL_DDR1_2_5_CLK
791 #define SDRAM_MMODE_DCL_DDR1_3_0_CLK JEDEC_MA_MR_CL_DDR1_3_0_CLK
792 #define SDRAM_MMODE_DCL_DDR2_2_0_CLK JEDEC_MA_MR_CL_DDR2_2_0_CLK
793 #define SDRAM_MMODE_DCL_DDR2_3_0_CLK JEDEC_MA_MR_CL_DDR2_3_0_CLK
794 #define SDRAM_MMODE_DCL_DDR2_4_0_CLK JEDEC_MA_MR_CL_DDR2_4_0_CLK
795 #define SDRAM_MMODE_DCL_DDR2_5_0_CLK JEDEC_MA_MR_CL_DDR2_5_0_CLK
796 #define SDRAM_MMODE_DCL_DDR2_6_0_CLK JEDEC_MA_MR_CL_DDR2_6_0_CLK
797 #define SDRAM_MMODE_DCL_DDR2_7_0_CLK JEDEC_MA_MR_CL_DDR2_7_0_CLK
798 #define SDRAM_MMODE_BTYP_SEQUENTIAL JEDEC_MA_MR_BTYP_SEQUENTIAL
799 #define SDRAM_MMODE_BTYP_INTERLEAVED JEDEC_MA_MR_BTYP_INTERLEAVED
800 #define SDRAM_MMODE_BLEN_MASK JEDEC_MA_MR_BLEN_MASK
801 #define SDRAM_MMODE_BLEN_4 JEDEC_MA_MR_BLEN_4
802 #define SDRAM_MMODE_BLEN_8 JEDEC_MA_MR_BLEN_8
805 * SDRAM Extended Mode Register (Corresponds 1:1 w/ JEDEC Extended
808 #define SDRAM_MEMODE_QOFF_MASK JEDEC_MA_EMR_OUTPUT_MASK
809 #define SDRAM_MEMODE_QOFF_DISABLE JEDEC_MA_EMR_OUTPUT_DISABLE
810 #define SDRAM_MEMODE_QOFF_ENABLE JEDEC_MA_EMR_OUTPUT_ENABLE
811 #define SDRAM_MEMODE_RDQS_MASK JEDEC_MA_EMR_RQDS_MASK
812 #define SDRAM_MEMODE_RDQS_DISABLE JEDEC_MA_EMR_RDQS_DISABLE
813 #define SDRAM_MEMODE_RDQS_ENABLE JEDEC_MA_EMR_RDQS_ENABLE
814 #define SDRAM_MEMODE_DQS_MASK JEDEC_MA_EMR_DQS_MASK
815 #define SDRAM_MEMODE_DQS_DISABLE JEDEC_MA_EMR_DQS_DISABLE
816 #define SDRAM_MEMODE_DQS_ENABLE JEDEC_MA_EMR_DQS_ENABLE
817 #define SDRAM_MEMODE_AL_DDR1_0_CYC JEDEC_MA_EMR_AL_DDR1_0_CYC
818 #define SDRAM_MEMODE_AL_DDR2_1_CYC JEDEC_MA_EMR_AL_DDR2_1_CYC
819 #define SDRAM_MEMODE_AL_DDR2_2_CYC JEDEC_MA_EMR_AL_DDR2_2_CYC
820 #define SDRAM_MEMODE_AL_DDR2_3_CYC JEDEC_MA_EMR_AL_DDR2_3_CYC
821 #define SDRAM_MEMODE_AL_DDR2_4_CYC JEDEC_MA_EMR_AL_DDR2_4_CYC
822 #define SDRAM_MEMODE_RTT_MASK JEDEC_MA_EMR_RTT_MASK
823 #define SDRAM_MEMODE_RTT_DISABLED JEDEC_MA_EMR_RTT_DISABLED
824 #define SDRAM_MEMODE_RTT_75OHM JEDEC_MA_EMR_RTT_75OHM
825 #define SDRAM_MEMODE_RTT_150OHM JEDEC_MA_EMR_RTT_150OHM
826 #define SDRAM_MEMODE_RTT_50OHM JEDEC_MA_EMR_RTT_50OHM
827 #define SDRAM_MEMODE_DIC_MASK JEDEC_MA_EMR_ODS_MASK
828 #define SDRAM_MEMODE_DIC_NORMAL JEDEC_MA_EMR_ODS_NORMAL
829 #define SDRAM_MEMODE_DIC_WEAK JEDEC_MA_EMR_ODS_WEAK
830 #define SDRAM_MEMODE_DLL_MASK JEDEC_MA_EMR_DLL_MASK
831 #define SDRAM_MEMODE_DLL_DISABLE JEDEC_MA_EMR_DLL_DISABLE
832 #define SDRAM_MEMODE_DLL_ENABLE JEDEC_MA_EMR_DLL_ENABLE
835 * SDRAM Clock Timing Register
837 #define SDRAM_CLKTR_CLKP_MASK 0xC0000000
838 #define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
839 #define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
840 #define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000
841 #define SDRAM_CLKTR_CLKP_270_DEG_ADV 0xC0000000
844 * SDRAM Write Timing Register
846 #define SDRAM_WRDTR_LLWP_MASK 0x10000000
847 #define SDRAM_WRDTR_LLWP_DIS 0x10000000
848 #define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
849 #define SDRAM_WRDTR_WTR_MASK 0x0E000000
850 #define SDRAM_WRDTR_WTR_0_DEG 0x06000000
851 #define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000
852 #define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
853 #define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
856 * SDRAM SDTR1 Options
858 #define SDRAM_SDTR1_LDOF_MASK 0x80000000
859 #define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
860 #define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
861 #define SDRAM_SDTR1_RTW_MASK 0x00F00000
862 #define SDRAM_SDTR1_RTW_2_CLK 0x00200000
863 #define SDRAM_SDTR1_RTW_3_CLK 0x00300000
864 #define SDRAM_SDTR1_WTWO_MASK 0x000F0000
865 #define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
866 #define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
867 #define SDRAM_SDTR1_RTRO_MASK 0x0000F000
868 #define SDRAM_SDTR1_RTRO_1_CLK 0x00001000
869 #define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
872 * SDRAM SDTR2 Options
874 #define SDRAM_SDTR2_RCD_MASK 0xF0000000
875 #define SDRAM_SDTR2_RCD_1_CLK 0x10000000
876 #define SDRAM_SDTR2_RCD_2_CLK 0x20000000
877 #define SDRAM_SDTR2_RCD_3_CLK 0x30000000
878 #define SDRAM_SDTR2_RCD_4_CLK 0x40000000
879 #define SDRAM_SDTR2_RCD_5_CLK 0x50000000
880 #define SDRAM_SDTR2_WTR_MASK 0x0F000000
881 #define SDRAM_SDTR2_WTR_1_CLK 0x01000000
882 #define SDRAM_SDTR2_WTR_2_CLK 0x02000000
883 #define SDRAM_SDTR2_WTR_3_CLK 0x03000000
884 #define SDRAM_SDTR2_WTR_4_CLK 0x04000000
885 #define SDRAM_SDTR3_WTR_ENCODE(n) ((((u32)(n))&0xF)<<24)
886 #define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
887 #define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
888 #define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
889 #define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
890 #define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
891 #define SDRAM_SDTR2_WPC_MASK 0x0000F000
892 #define SDRAM_SDTR2_WPC_2_CLK 0x00002000
893 #define SDRAM_SDTR2_WPC_3_CLK 0x00003000
894 #define SDRAM_SDTR2_WPC_4_CLK 0x00004000
895 #define SDRAM_SDTR2_WPC_5_CLK 0x00005000
896 #define SDRAM_SDTR2_WPC_6_CLK 0x00006000
897 #define SDRAM_SDTR3_WPC_ENCODE(n) ((((u32)(n))&0xF)<<12)
898 #define SDRAM_SDTR2_RPC_MASK 0x00000F00
899 #define SDRAM_SDTR2_RPC_2_CLK 0x00000200
900 #define SDRAM_SDTR2_RPC_3_CLK 0x00000300
901 #define SDRAM_SDTR2_RPC_4_CLK 0x00000400
902 #define SDRAM_SDTR2_RP_MASK 0x000000F0
903 #define SDRAM_SDTR2_RP_3_CLK 0x00000030
904 #define SDRAM_SDTR2_RP_4_CLK 0x00000040
905 #define SDRAM_SDTR2_RP_5_CLK 0x00000050
906 #define SDRAM_SDTR2_RP_6_CLK 0x00000060
907 #define SDRAM_SDTR2_RP_7_CLK 0x00000070
908 #define SDRAM_SDTR2_RRD_MASK 0x0000000F
909 #define SDRAM_SDTR2_RRD_2_CLK 0x00000002
910 #define SDRAM_SDTR2_RRD_3_CLK 0x00000003
913 * SDRAM SDTR3 Options
915 #define SDRAM_SDTR3_RAS_MASK 0x1F000000
916 #define SDRAM_SDTR3_RAS_ENCODE(n) ((((u32)(n))&0x1F)<<24)
917 #define SDRAM_SDTR3_RC_MASK 0x001F0000
918 #define SDRAM_SDTR3_RC_ENCODE(n) ((((u32)(n))&0x1F)<<16)
919 #define SDRAM_SDTR3_XCS_MASK 0x00001F00
920 #define SDRAM_SDTR3_XCS 0x00000D00
921 #define SDRAM_SDTR3_RFC_MASK 0x0000003F
922 #define SDRAM_SDTR3_RFC_ENCODE(n) ((((u32)(n))&0x3F)<<0)
927 #define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF)
928 #define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF)
929 #define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1)
930 #define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3)
931 #define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0)
932 #define SDRAM_ECCES_CKBER_16_ECC_0_3 PPC_REG_VAL(17, 2)
933 #define SDRAM_ECCES_CKBER_32_ECC_0_3 PPC_REG_VAL(17, 1)
934 #define SDRAM_ECCES_CKBER_32_ECC_4_8 PPC_REG_VAL(17, 2)
935 #define SDRAM_ECCES_CKBER_32_ECC_0_8 PPC_REG_VAL(17, 3)
936 #define SDRAM_ECCES_CE PPC_REG_VAL(18, 1)
937 #define SDRAM_ECCES_UE PPC_REG_VAL(19, 1)
938 #define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3)
939 #define SDRAM_ECCES_BK0ER PPC_REG_VAL(20, 1)
940 #define SDRAM_ECCES_BK1ER PPC_REG_VAL(21, 1)
943 * Memory Bank 0-1 configuration
945 #define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
946 #define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
947 #define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
948 #define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
949 #define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
950 #define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
951 #define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
952 #define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
953 #define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
954 #define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
955 #define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
956 #define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
957 #define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
958 #define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
960 #define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/
961 #define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */
962 #define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */
963 #define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */
964 #define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */
966 #define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */
968 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */
970 #if defined(CONFIG_SDRAM_PPC4xx_DENALI_DDR2)
975 #define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
976 #define DDR0_00_INT_ACK_ALL 0x7F000000
977 #define DDR0_00_INT_ACK_ENCODE(n) ((((u32)(n))&0x7F)<<24)
978 #define DDR0_00_INT_ACK_DECODE(n) ((((u32)(n))>>24)&0x7F)
980 #define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
981 /* Bit0. A single access outside the defined PHYSICAL memory space detected. */
982 #define DDR0_00_INT_STATUS_BIT0 0x00010000
983 /* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
984 #define DDR0_00_INT_STATUS_BIT1 0x00020000
985 /* Bit2. Single correctable ECC event detected */
986 #define DDR0_00_INT_STATUS_BIT2 0x00040000
987 /* Bit3. Multiple correctable ECC events detected. */
988 #define DDR0_00_INT_STATUS_BIT3 0x00080000
989 /* Bit4. Single uncorrectable ECC event detected. */
990 #define DDR0_00_INT_STATUS_BIT4 0x00100000
991 /* Bit5. Multiple uncorrectable ECC events detected. */
992 #define DDR0_00_INT_STATUS_BIT5 0x00200000
993 /* Bit6. DRAM initialization complete. */
994 #define DDR0_00_INT_STATUS_BIT6 0x00400000
995 /* Bit7. Logical OR of all lower bits. */
996 #define DDR0_00_INT_STATUS_BIT7 0x00800000
998 #define DDR0_00_INT_STATUS_ENCODE(n) ((((u32)(n))&0xFF)<<16)
999 #define DDR0_00_INT_STATUS_DECODE(n) ((((u32)(n))>>16)&0xFF)
1000 #define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
1001 #define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1002 #define DDR0_00_DLL_INCREMENT_DECODE(n) ((((u32)(n))>>8)&0x7F)
1003 #define DDR0_00_DLL_START_POINT_MASK 0x0000007F
1004 #define DDR0_00_DLL_START_POINT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1005 #define DDR0_00_DLL_START_POINT_DECODE(n) ((((u32)(n))>>0)&0x7F)
1007 #define DDR0_01 0x01
1008 #define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
1009 #define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((u32)(n))&0x1F)<<24)
1010 #define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((u32)(n))>>24)&0x1F)
1011 #define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
1012 #define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((u32)(n))&0x1F)<<16)
1013 #define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((u32)(n))>>16)&0x1F)
1014 #define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
1015 #define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((u32)(n))&0x7)<<8)
1016 #define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((u32)(n))>>8)&0x7)
1017 #define DDR0_01_INT_MASK_MASK 0x000000FF
1018 #define DDR0_01_INT_MASK_ENCODE(n) ((((u32)(n))&0xFF)<<0)
1019 #define DDR0_01_INT_MASK_DECODE(n) ((((u32)(n))>>0)&0xFF)
1020 #define DDR0_01_INT_MASK_ALL_ON 0x000000FF
1021 #define DDR0_01_INT_MASK_ALL_OFF 0x00000000
1023 #define DDR0_02 0x02
1024 #define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
1025 #define DDR0_02_MAX_CS_REG_ENCODE(n) ((((u32)(n))&0x2)<<24)
1026 #define DDR0_02_MAX_CS_REG_DECODE(n) ((((u32)(n))>>24)&0x2)
1027 #define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
1028 #define DDR0_02_MAX_COL_REG_ENCODE(n) ((((u32)(n))&0xF)<<16)
1029 #define DDR0_02_MAX_COL_REG_DECODE(n) ((((u32)(n))>>16)&0xF)
1030 #define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
1031 #define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((u32)(n))&0xF)<<8)
1032 #define DDR0_02_MAX_ROW_REG_DECODE(n) ((((u32)(n))>>8)&0xF)
1033 #define DDR0_02_START_MASK 0x00000001
1034 #define DDR0_02_START_ENCODE(n) ((((u32)(n))&0x1)<<0)
1035 #define DDR0_02_START_DECODE(n) ((((u32)(n))>>0)&0x1)
1036 #define DDR0_02_START_OFF 0x00000000
1037 #define DDR0_02_START_ON 0x00000001
1039 #define DDR0_03 0x03
1040 #define DDR0_03_BSTLEN_MASK 0x07000000
1041 #define DDR0_03_BSTLEN_ENCODE(n) ((((u32)(n))&0x7)<<24)
1042 #define DDR0_03_BSTLEN_DECODE(n) ((((u32)(n))>>24)&0x7)
1043 #define DDR0_03_CASLAT_MASK 0x00070000
1044 #define DDR0_03_CASLAT_ENCODE(n) ((((u32)(n))&0x7)<<16)
1045 #define DDR0_03_CASLAT_DECODE(n) ((((u32)(n))>>16)&0x7)
1046 #define DDR0_03_CASLAT_LIN_MASK 0x00000F00
1047 #define DDR0_03_CASLAT_LIN_ENCODE(n) ((((u32)(n))&0xF)<<8)
1048 #define DDR0_03_CASLAT_LIN_DECODE(n) ((((u32)(n))>>8)&0xF)
1049 #define DDR0_03_INITAREF_MASK 0x0000000F
1050 #define DDR0_03_INITAREF_ENCODE(n) ((((u32)(n))&0xF)<<0)
1051 #define DDR0_03_INITAREF_DECODE(n) ((((u32)(n))>>0)&0xF)
1053 #define DDR0_04 0x04
1054 #define DDR0_04_TRC_MASK 0x1F000000
1055 #define DDR0_04_TRC_ENCODE(n) ((((u32)(n))&0x1F)<<24)
1056 #define DDR0_04_TRC_DECODE(n) ((((u32)(n))>>24)&0x1F)
1057 #define DDR0_04_TRRD_MASK 0x00070000
1058 #define DDR0_04_TRRD_ENCODE(n) ((((u32)(n))&0x7)<<16)
1059 #define DDR0_04_TRRD_DECODE(n) ((((u32)(n))>>16)&0x7)
1060 #define DDR0_04_TRTP_MASK 0x00000700
1061 #define DDR0_04_TRTP_ENCODE(n) ((((u32)(n))&0x7)<<8)
1062 #define DDR0_04_TRTP_DECODE(n) ((((u32)(n))>>8)&0x7)
1064 #define DDR0_05 0x05
1065 #define DDR0_05_TMRD_MASK 0x1F000000
1066 #define DDR0_05_TMRD_ENCODE(n) ((((u32)(n))&0x1F)<<24)
1067 #define DDR0_05_TMRD_DECODE(n) ((((u32)(n))>>24)&0x1F)
1068 #define DDR0_05_TEMRS_MASK 0x00070000
1069 #define DDR0_05_TEMRS_ENCODE(n) ((((u32)(n))&0x7)<<16)
1070 #define DDR0_05_TEMRS_DECODE(n) ((((u32)(n))>>16)&0x7)
1071 #define DDR0_05_TRP_MASK 0x00000F00
1072 #define DDR0_05_TRP_ENCODE(n) ((((u32)(n))&0xF)<<8)
1073 #define DDR0_05_TRP_DECODE(n) ((((u32)(n))>>8)&0xF)
1074 #define DDR0_05_TRAS_MIN_MASK 0x000000FF
1075 #define DDR0_05_TRAS_MIN_ENCODE(n) ((((u32)(n))&0xFF)<<0)
1076 #define DDR0_05_TRAS_MIN_DECODE(n) ((((u32)(n))>>0)&0xFF)
1078 #define DDR0_06 0x06
1079 #define DDR0_06_WRITEINTERP_MASK 0x01000000
1080 #define DDR0_06_WRITEINTERP_ENCODE(n) ((((u32)(n))&0x1)<<24)
1081 #define DDR0_06_WRITEINTERP_DECODE(n) ((((u32)(n))>>24)&0x1)
1082 #define DDR0_06_TWTR_MASK 0x00070000
1083 #define DDR0_06_TWTR_ENCODE(n) ((((u32)(n))&0x7)<<16)
1084 #define DDR0_06_TWTR_DECODE(n) ((((u32)(n))>>16)&0x7)
1085 #define DDR0_06_TDLL_MASK 0x0000FF00
1086 #define DDR0_06_TDLL_ENCODE(n) ((((u32)(n))&0xFF)<<8)
1087 #define DDR0_06_TDLL_DECODE(n) ((((u32)(n))>>8)&0xFF)
1088 #define DDR0_06_TRFC_MASK 0x0000007F
1089 #define DDR0_06_TRFC_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1090 #define DDR0_06_TRFC_DECODE(n) ((((u32)(n))>>0)&0x7F)
1092 #define DDR0_07 0x07
1093 #define DDR0_07_NO_CMD_INIT_MASK 0x01000000
1094 #define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((u32)(n))&0x1)<<24)
1095 #define DDR0_07_NO_CMD_INIT_DECODE(n) ((((u32)(n))>>24)&0x1)
1096 #define DDR0_07_TFAW_MASK 0x001F0000
1097 #define DDR0_07_TFAW_ENCODE(n) ((((u32)(n))&0x1F)<<16)
1098 #define DDR0_07_TFAW_DECODE(n) ((((u32)(n))>>16)&0x1F)
1099 #define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
1100 #define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((u32)(n))&0x1)<<8)
1101 #define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((u32)(n))>>8)&0x1)
1102 #define DDR0_07_AREFRESH_MASK 0x00000001
1103 #define DDR0_07_AREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<0)
1104 #define DDR0_07_AREFRESH_DECODE(n) ((((u32)(n))>>0)&0x1)
1106 #define DDR0_08 0x08
1107 #define DDR0_08_WRLAT_MASK 0x07000000
1108 #define DDR0_08_WRLAT_ENCODE(n) ((((u32)(n))&0x7)<<24)
1109 #define DDR0_08_WRLAT_DECODE(n) ((((u32)(n))>>24)&0x7)
1110 #define DDR0_08_TCPD_MASK 0x00FF0000
1111 #define DDR0_08_TCPD_ENCODE(n) ((((u32)(n))&0xFF)<<16)
1112 #define DDR0_08_TCPD_DECODE(n) ((((u32)(n))>>16)&0xFF)
1113 #define DDR0_08_DQS_N_EN_MASK 0x00000100
1114 #define DDR0_08_DQS_N_EN_ENCODE(n) ((((u32)(n))&0x1)<<8)
1115 #define DDR0_08_DQS_N_EN_DECODE(n) ((((u32)(n))>>8)&0x1)
1116 #define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
1117 #define DDR0_08_DDRII_ENCODE(n) ((((u32)(n))&0x1)<<0)
1118 #define DDR0_08_DDRII_DECODE(n) ((((u32)(n))>>0)&0x1)
1120 #define DDR0_09 0x09
1121 #define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
1122 #define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<24)
1123 #define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((u32)(n))>>24)&0x1F)
1124 #define DDR0_09_RTT_0_MASK 0x00030000
1125 #define DDR0_09_RTT_0_ENCODE(n) ((((u32)(n))&0x3)<<16)
1126 #define DDR0_09_RTT_0_DECODE(n) ((((u32)(n))>>16)&0x3)
1127 #define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
1128 #define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1129 #define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>8)&0x7F)
1130 #define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
1131 #define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1132 #define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((u32)(n))>>0)&0x7F)
1134 #define DDR0_10 0x0A
1135 #define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
1136 #define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((u32)(n))&0x1)<<16)
1137 #define DDR0_10_WRITE_MODEREG_DECODE(n) ((((u32)(n))>>16)&0x1)
1138 #define DDR0_10_CS_MAP_MASK 0x00000300
1139 #define DDR0_10_CS_MAP_NO_MEM 0x00000000
1140 #define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
1141 #define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
1142 #define DDR0_10_CS_MAP_ENCODE(n) ((((u32)(n))&0x3)<<8)
1143 #define DDR0_10_CS_MAP_DECODE(n) ((((u32)(n))>>8)&0x3)
1144 #define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
1145 #define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<0)
1146 #define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((u32)(n))>>0)&0x1F)
1148 #define DDR0_11 0x0B
1149 #define DDR0_11_SREFRESH_MASK 0x01000000
1150 #define DDR0_11_SREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<24)
1151 #define DDR0_11_SREFRESH_DECODE(n) ((((u32)(n))>>24)&0x1F)
1152 #define DDR0_11_TXSNR_MASK 0x00FF0000
1153 #define DDR0_11_TXSNR_ENCODE(n) ((((u32)(n))&0xFF)<<16)
1154 #define DDR0_11_TXSNR_DECODE(n) ((((u32)(n))>>16)&0xFF)
1155 #define DDR0_11_TXSR_MASK 0x0000FF00
1156 #define DDR0_11_TXSR_ENCODE(n) ((((u32)(n))&0xFF)<<8)
1157 #define DDR0_11_TXSR_DECODE(n) ((((u32)(n))>>8)&0xFF)
1159 #define DDR0_12 0x0C
1160 #define DDR0_12_TCKE_MASK 0x0000007
1161 #define DDR0_12_TCKE_ENCODE(n) ((((u32)(n))&0x7)<<0)
1162 #define DDR0_12_TCKE_DECODE(n) ((((u32)(n))>>0)&0x7)
1164 #define DDR0_14 0x0E
1165 #define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
1166 #define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((u32)(n))&0x1)<<24)
1167 #define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((u32)(n))>>24)&0x1)
1168 #define DDR0_14_REDUC_MASK 0x00010000
1169 #define DDR0_14_REDUC_64BITS 0x00000000
1170 #define DDR0_14_REDUC_32BITS 0x00010000
1171 #define DDR0_14_REDUC_ENCODE(n) ((((u32)(n))&0x1)<<16)
1172 #define DDR0_14_REDUC_DECODE(n) ((((u32)(n))>>16)&0x1)
1173 #define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
1174 #define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((u32)(n))&0x1)<<8)
1175 #define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((u32)(n))>>8)&0x1)
1177 #define DDR0_17 0x11
1178 #define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
1179 #define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1180 #define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((u32)(n))>>24)&0x7F)
1181 #define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
1182 #define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
1183 #define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
1184 #define DDR0_17_DLLLOCKREG_ENCODE(n) ((((u32)(n))&0x1)<<16)
1185 #define DDR0_17_DLLLOCKREG_DECODE(n) ((((u32)(n))>>16)&0x1)
1186 #define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
1187 #define DDR0_17_DLL_LOCK_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1188 #define DDR0_17_DLL_LOCK_DECODE(n) ((((u32)(n))>>8)&0x7F)
1190 #define DDR0_18 0x12
1191 #define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
1192 #define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
1193 #define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1194 #define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((u32)(n))>>24)&0x7F)
1195 #define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
1196 #define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1197 #define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((u32)(n))>>16)&0x7F)
1198 #define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
1199 #define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1200 #define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((u32)(n))>>8)&0x7F)
1201 #define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
1202 #define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1203 #define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((u32)(n))>>0)&0x7F)
1205 #define DDR0_19 0x13
1206 #define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
1207 #define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
1208 #define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1209 #define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((u32)(n))>>24)&0x7F)
1210 #define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
1211 #define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1212 #define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((u32)(n))>>16)&0x7F)
1213 #define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
1214 #define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1215 #define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((u32)(n))>>8)&0x7F)
1216 #define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
1217 #define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1218 #define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((u32)(n))>>0)&0x7F)
1220 #define DDR0_20 0x14
1221 #define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
1222 #define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1223 #define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((u32)(n))>>24)&0x7F)
1224 #define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
1225 #define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1226 #define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((u32)(n))>>16)&0x7F)
1227 #define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
1228 #define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1229 #define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((u32)(n))>>8)&0x7F)
1230 #define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
1231 #define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1232 #define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((u32)(n))>>0)&0x7F)
1234 #define DDR0_21 0x15
1235 #define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
1236 #define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((u32)(n))&0x7F)<<24)
1237 #define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((u32)(n))>>24)&0x7F)
1238 #define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
1239 #define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1240 #define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((u32)(n))>>16)&0x7F)
1241 #define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
1242 #define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1243 #define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((u32)(n))>>8)&0x7F)
1244 #define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
1245 #define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1246 #define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((u32)(n))>>0)&0x7F)
1248 #define DDR0_22 0x16
1249 #define DDR0_22_CTRL_RAW_MASK 0x03000000
1250 #define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000
1251 #define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000
1252 #define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000
1253 #define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000
1254 #define DDR0_22_CTRL_RAW_ENCODE(n) ((((u32)(n))&0x3)<<24)
1255 #define DDR0_22_CTRL_RAW_DECODE(n) ((((u32)(n))>>24)&0x3)
1256 #define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
1257 #define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1258 #define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>16)&0x7F)
1259 #define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
1260 #define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1261 #define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((u32)(n))>>8)&0x7F)
1262 #define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
1263 #define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1264 #define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((u32)(n))>>0)&0x7F)
1266 #define DDR0_23 0x17
1267 #define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
1268 #define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<24)
1269 #define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((u32)(n))>>24)&0x3)
1270 #define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
1271 #define DDR0_23_ECC_C_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<16)
1272 #define DDR0_23_ECC_C_SYND_DECODE(n) ((((u32)(n))>>16)&0xFF)
1273 #define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
1274 #define DDR0_23_ECC_U_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<8)
1275 #define DDR0_23_ECC_U_SYND_DECODE(n) ((((u32)(n))>>8)&0xFF)
1276 #define DDR0_23_FWC_MASK 0x00000001 /* Write only */
1277 #define DDR0_23_FWC_ENCODE(n) ((((u32)(n))&0x1)<<0)
1278 #define DDR0_23_FWC_DECODE(n) ((((u32)(n))>>0)&0x1)
1280 #define DDR0_24 0x18
1281 #define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
1282 #define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((u32)(n))&0x3)<<24)
1283 #define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((u32)(n))>>24)&0x3)
1284 #define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
1285 #define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<16)
1286 #define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((u32)(n))>>16)&0x3)
1287 #define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
1288 #define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<8)
1289 #define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((u32)(n))>>8)&0x3)
1290 #define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
1291 #define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<0)
1292 #define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((u32)(n))>>0)&0x3)
1294 #define DDR0_25 0x19
1295 #define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
1296 #define DDR0_25_VERSION_ENCODE(n) ((((u32)(n))&0xFFFF)<<16)
1297 #define DDR0_25_VERSION_DECODE(n) ((((u32)(n))>>16)&0xFFFF)
1298 #define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
1299 #define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((u32)(n))&0x3FF)<<0)
1300 #define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((u32)(n))>>0)&0x3FF)
1302 #define DDR0_26 0x1A
1303 #define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
1304 #define DDR0_26_TRAS_MAX_ENCODE(n) ((((u32)(n))&0xFFFF)<<16)
1305 #define DDR0_26_TRAS_MAX_DECODE(n) ((((u32)(n))>>16)&0xFFFF)
1306 #define DDR0_26_TREF_MASK 0x00003FFF
1307 #define DDR0_26_TREF_ENCODE(n) ((((u32)(n))&0x3FFF)<<0)
1308 #define DDR0_26_TREF_DECODE(n) ((((u32)(n))>>0)&0x3FFF)
1310 #define DDR0_27 0x1B
1311 #define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
1312 #define DDR0_27_EMRS_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16)
1313 #define DDR0_27_EMRS_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF)
1314 #define DDR0_27_TINIT_MASK 0x0000FFFF
1315 #define DDR0_27_TINIT_ENCODE(n) ((((u32)(n))&0xFFFF)<<0)
1316 #define DDR0_27_TINIT_DECODE(n) ((((u32)(n))>>0)&0xFFFF)
1318 #define DDR0_28 0x1C
1319 #define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
1320 #define DDR0_28_EMRS3_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16)
1321 #define DDR0_28_EMRS3_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF)
1322 #define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
1323 #define DDR0_28_EMRS2_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<0)
1324 #define DDR0_28_EMRS2_DATA_DECODE(n) ((((u32)(n))>>0)&0x3FFF)
1326 #define DDR0_31 0x1F
1327 #define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
1328 #define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((u32)(n))&0xFFFF)<<0)
1329 #define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((u32)(n))>>0)&0xFFFF)
1331 #define DDR0_32 0x20
1332 #define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
1333 #define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1334 #define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1336 #define DDR0_33 0x21
1337 #define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
1338 #define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
1339 #define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
1341 #define DDR0_34 0x22
1342 #define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
1343 #define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1344 #define DDR0_34_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1346 #define DDR0_35 0x23
1347 #define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
1348 #define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
1349 #define DDR0_35_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
1351 #define DDR0_36 0x24
1352 #define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
1353 #define DDR0_36_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1354 #define DDR0_36_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1356 #define DDR0_37 0x25
1357 #define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
1358 #define DDR0_37_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1359 #define DDR0_37_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1361 #define DDR0_38 0x26
1362 #define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
1363 #define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1364 #define DDR0_38_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1366 #define DDR0_39 0x27
1367 #define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
1368 #define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
1369 #define DDR0_39_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
1371 #define DDR0_40 0x28
1372 #define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
1373 #define DDR0_40_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1374 #define DDR0_40_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1376 #define DDR0_41 0x29
1377 #define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
1378 #define DDR0_41_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1379 #define DDR0_41_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1381 #define DDR0_42 0x2A
1382 #define DDR0_42_ADDR_PINS_MASK 0x07000000
1383 #define DDR0_42_ADDR_PINS_ENCODE(n) ((((u32)(n))&0x7)<<24)
1384 #define DDR0_42_ADDR_PINS_DECODE(n) ((((u32)(n))>>24)&0x7)
1385 #define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
1386 #define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((u32)(n))&0xF)<<0)
1387 #define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((u32)(n))>>0)&0xF)
1389 #define DDR0_43 0x2B
1390 #define DDR0_43_TWR_MASK 0x07000000
1391 #define DDR0_43_TWR_ENCODE(n) ((((u32)(n))&0x7)<<24)
1392 #define DDR0_43_TWR_DECODE(n) ((((u32)(n))>>24)&0x7)
1393 #define DDR0_43_APREBIT_MASK 0x000F0000
1394 #define DDR0_43_APREBIT_ENCODE(n) ((((u32)(n))&0xF)<<16)
1395 #define DDR0_43_APREBIT_DECODE(n) ((((u32)(n))>>16)&0xF)
1396 #define DDR0_43_COLUMN_SIZE_MASK 0x00000700
1397 #define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((u32)(n))&0x7)<<8)
1398 #define DDR0_43_COLUMN_SIZE_DECODE(n) ((((u32)(n))>>8)&0x7)
1399 #define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
1400 #define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
1401 #define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
1402 #define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((u32)(n))&0x1)<<0)
1403 #define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((u32)(n))>>0)&0x1)
1405 #define DDR0_44 0x2C
1406 #define DDR0_44_TRCD_MASK 0x000000FF
1407 #define DDR0_44_TRCD_ENCODE(n) ((((u32)(n))&0xFF)<<0)
1408 #define DDR0_44_TRCD_DECODE(n) ((((u32)(n))>>0)&0xFF)
1410 #endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
1412 #ifndef __ASSEMBLY__
1416 void inline blank_string(int size
);
1417 inline void ppc4xx_ibm_ddr2_register_dump(void);
1419 void mtdcr_any(u32
, u32
);
1422 void spd_ddr_init_hang(void);
1423 u32
DQS_autocalibration(void);
1424 #endif /* __ASSEMBLY__ */
1426 #endif /* _PPC4xx_SDRAM_H_ */
projects / people / ms / u-boot.git / blob