include/configs/Alaska8220.h

   1 /*
   2  * (C) Copyright 2004
   3  * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31 #define CONFIG_MPC8220          1
  32 #define CONFIG_ALASKA8220       1       /* ... on Alaska board  */
  33
  34 /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
  35    determine the CPU speed. */
  36 #define CFG_MPC8220_CLKIN       30000000/* ... running at 30MHz */
  37 #define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
  38
  39 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
  40 #define BOOTFLAG_WARM           0x02    /* Software reboot      */
  41
  42 #define CFG_CACHELINE_SIZE      32      /* For MPC8220 CPUs */
  43
  44 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  45 #  define CFG_CACHELINE_SHIFT   5   /* log base 2 of the above value */
  46 #endif
  47
  48 /*
  49  * Serial console configuration
  50  */
  51
  52 /* Define this for PSC console
  53 #define CONFIG_PSC_CONSOLE      1
  54 */
  55
  56 #define CONFIG_EXTUART_CONSOLE  1
  57
  58 #ifdef CONFIG_EXTUART_CONSOLE
  59 #   define CONFIG_CONS_INDEX    1
  60 #   define CFG_NS16550_SERIAL
  61 #   define CFG_NS16550
  62 #   define CFG_NS16550_REG_SIZE 1
  63 #   define CFG_NS16550_COM1     (CFG_CPLD_BASE + 0x1008)
  64 #   define CFG_NS16550_CLK      18432000
  65 #endif
  66
  67 #define CONFIG_BAUDRATE         115200      /* ... at 115200 bps */
  68
  69 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  70
  71 #define CONFIG_TIMESTAMP                        /* Print image info with timestamp */
  72
  73 /*
  74  * Supported commands
  75  */
  76 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
  77                                 CFG_CMD_BOOTD   | \
  78                                 CFG_CMD_CACHE   | \
  79                                 CFG_CMD_DHCP    | \
  80                                 CFG_CMD_DIAG    | \
  81                                 CFG_CMD_EEPROM  | \
  82                                 CFG_CMD_ELF     | \
  83                                 CFG_CMD_I2C     | \
  84                                 CFG_CMD_NET     | \
  85                                 CFG_CMD_NFS     | \
  86                                 CFG_CMD_PCI     | \
  87                                 CFG_CMD_PING    | \
  88                                 CFG_CMD_REGINFO | \
  89                                 CFG_CMD_SDRAM   | \
  90                                 CFG_CMD_SNTP    )
  91
  92 #define CONFIG_NET_MULTI
  93
  94 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  95 #include <cmd_confdefs.h>
  96
  97 /*
  98  * Autobooting
  99  */
 100 #define CONFIG_BOOTDELAY        5    /* autoboot after 5 seconds */
 101 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
 102 #define CONFIG_ETHADDR          00:e0:0c:bc:e0:60
 103 #define CONFIG_HAS_ETH1
 104 #define CONFIG_ETH1ADDR         00:e0:0c:bc:e0:61
 105 #define CONFIG_IPADDR           192.162.1.2
 106 #define CONFIG_NETMASK          255.255.255.0
 107 #define CONFIG_SERVERIP         192.162.1.1
 108 #define CONFIG_GATEWAYIP        192.162.1.1
 109 #define CONFIG_HOSTNAME         Alaska
 110 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 111
 112
 113 /*
 114  * I2C configuration
 115  */
 116 #define CONFIG_HARD_I2C         1
 117 #define CFG_I2C_MODULE          1
 118
 119 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 120 #define CFG_I2C_SLAVE           0x7F
 121
 122 /*
 123  * EEPROM configuration
 124  */
 125 #define CFG_I2C_EEPROM_ADDR             0x52    /* 1011000xb */
 126 #define CFG_I2C_EEPROM_ADDR_LEN         1
 127 #define CFG_EEPROM_PAGE_WRITE_BITS      3
 128 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  70
 129 /*
 130 #define CFG_ENV_IS_IN_EEPROM    1
 131 #define CFG_ENV_OFFSET          0
 132 #define CFG_ENV_SIZE            256
 133 */
 134
 135 /* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
 136    else undefined it will boot from Intel Strata flash */
 137 #define CFG_AMD_BOOT            1
 138
 139 /*
 140  * Flexbus Chipselect configuration
 141  */
 142 #if defined (CFG_AMD_BOOT)
 143 #define CFG_CS0_BASE            0xfff0
 144 #define CFG_CS0_MASK            0x00080000  /* 512 KB */
 145 #define CFG_CS0_CTRL            0x003f0d40
 146
 147 #define CFG_CS1_BASE            0xfe00
 148 #define CFG_CS1_MASK            0x01000000  /* 16 MB */
 149 #define CFG_CS1_CTRL            0x003f1540
 150 #else
 151 #define CFG_CS0_BASE            0xff00
 152 #define CFG_CS0_MASK            0x01000000  /* 16 MB */
 153 #define CFG_CS0_CTRL            0x003f1540
 154
 155 #define CFG_CS1_BASE            0xfe08
 156 #define CFG_CS1_MASK            0x00080000  /* 512 KB */
 157 #define CFG_CS1_CTRL            0x003f0d40
 158 #endif
 159
 160 #define CFG_CS2_BASE            0xf100
 161 #define CFG_CS2_MASK            0x00040000
 162 #define CFG_CS2_CTRL            0x003f1140
 163
 164 #define CFG_CS3_BASE            0xf200
 165 #define CFG_CS3_MASK            0x00040000
 166 #define CFG_CS3_CTRL            0x003f1100
 167
 168
 169 #define CFG_FLASH0_BASE         (CFG_CS0_BASE << 16)
 170 #define CFG_FLASH1_BASE         (CFG_CS1_BASE << 16)
 171
 172 #if defined (CFG_AMD_BOOT)
 173 #define CFG_AMD_BASE            CFG_FLASH0_BASE
 174 #define CFG_INTEL_BASE          CFG_FLASH1_BASE + 0xf00000
 175 #define CFG_FLASH_BASE          CFG_AMD_BASE
 176 #else
 177 #define CFG_INTEL_BASE          CFG_FLASH0_BASE + 0xf00000
 178 #define CFG_AMD_BASE            CFG_FLASH1_BASE
 179 #define CFG_FLASH_BASE          CFG_INTEL_BASE
 180 #endif
 181
 182 #define CFG_CPLD_BASE           (CFG_CS2_BASE << 16)
 183 #define CFG_FPGA_BASE           (CFG_CS3_BASE << 16)
 184
 185
 186 #define CFG_MAX_FLASH_BANKS     4       /* max num of memory banks      */
 187 #define CFG_MAX_FLASH_SECT      128     /* max num of sects on one chip */
 188
 189 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 190 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 191 #define CFG_FLASH_LOCK_TOUT     5       /* Timeout for Flash Set Lock Bit (in ms) */
 192 #define CFG_FLASH_UNLOCK_TOUT   10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 193 #define CFG_FLASH_PROTECTION            /* "Real" (hardware) sectors protection */
 194
 195 #define PHYS_AMD_SECT_SIZE      0x00010000 /*  64 KB sectors (x2) */
 196 #define PHYS_INTEL_SECT_SIZE    0x00020000 /* 128 KB sectors (x2) */
 197
 198 #define CFG_FLASH_CHECKSUM
 199 /*
 200  * Environment settings
 201  */
 202 #define CFG_ENV_IS_IN_FLASH     1
 203 #if defined (CFG_AMD_BOOT)
 204 #define CFG_ENV_ADDR            (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
 205 #define CFG_ENV_SIZE            PHYS_AMD_SECT_SIZE
 206 #define CFG_ENV_SECT_SIZE       PHYS_AMD_SECT_SIZE
 207 #define CFG_ENV1_ADDR           (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
 208 #define CFG_ENV1_SIZE           PHYS_INTEL_SECT_SIZE
 209 #define CFG_ENV1_SECT_SIZE      PHYS_INTEL_SECT_SIZE
 210 #else
 211 #define CFG_ENV_ADDR            (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
 212 #define CFG_ENV_SIZE            PHYS_INTEL_SECT_SIZE
 213 #define CFG_ENV_SECT_SIZE       PHYS_INTEL_SECT_SIZE
 214 #define CFG_ENV1_ADDR           (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
 215 #define CFG_ENV1_SIZE           PHYS_AMD_SECT_SIZE
 216 #define CFG_ENV1_SECT_SIZE      PHYS_AMD_SECT_SIZE
 217 #endif
 218
 219 #define CONFIG_ENV_OVERWRITE    1
 220
 221 #if defined CFG_ENV_IS_IN_FLASH
 222 #undef CFG_ENV_IS_IN_NVRAM
 223 #undef CFG_ENV_IS_IN_EEPROM
 224 #elif defined CFG_ENV_IS_IN_NVRAM
 225 #undef CFG_ENV_IS_IN_FLASH
 226 #undef CFG_ENV_IS_IN_EEPROM
 227 #elif defined CFG_ENV_IS_IN_EEPROM
 228 #undef CFG_ENV_IS_IN_NVRAM
 229 #undef CFG_ENV_IS_IN_FLASH
 230 #endif
 231
 232 /*
 233  * Memory map
 234  */
 235 #define CFG_MBAR                0xF0000000
 236 #define CFG_SDRAM_BASE          0x00000000
 237 #define CFG_DEFAULT_MBAR        0x80000000
 238 #define CFG_SRAM_BASE           (CFG_MBAR + 0x20000)
 239 #define CFG_SRAM_SIZE           0x8000
 240
 241 /* Use SRAM until RAM will be available */
 242 #define CFG_INIT_RAM_ADDR       (CFG_MBAR + 0x20000)
 243 #define CFG_INIT_RAM_END        0x8000  /* End of used area in DPRAM */
 244
 245 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 246 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 247 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 248
 249 #define CFG_MONITOR_BASE        TEXT_BASE
 250 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 251 #   define CFG_RAMBOOT          1
 252 #endif
 253
 254 #define CFG_MONITOR_LEN         (256 << 10) /* Reserve 256 kB for Monitor   */
 255 #define CFG_MALLOC_LEN          (128 << 10) /* Reserve 128 kB for malloc()  */
 256 #define CFG_BOOTMAPSZ           (8 << 20)   /* Initial Memory map for Linux */
 257
 258 /* SDRAM configuration */
 259 #define CFG_SDRAM_TOTAL_BANKS           2
 260 #define CFG_SDRAM_SPD_I2C_ADDR          0x51            /* 7bit */
 261 #define CFG_SDRAM_SPD_SIZE              0x40
 262 #define CFG_SDRAM_CAS_LATENCY           4               /* (CL=2)x2 */
 263
 264 /* SDRAM drive strength register */
 265 #define CFG_SDRAM_DRIVE_STRENGTH        ((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
 266                                          (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
 267                                          (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
 268                                          (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
 269                                          (DRIVE_STRENGTH_LOW  << SDRAMDS_SBD_SHIFT))
 270
 271 /*
 272  * Ethernet configuration
 273  */
 274 #define CONFIG_MPC8220_FEC      1
 275 #define CONFIG_FEC_10MBIT       1 /* Workaround for FEC 100Mbit problem */
 276 #define CONFIG_PHY_ADDR         0x18
 277
 278
 279 /*
 280  * Miscellaneous configurable options
 281  */
 282 #define CFG_LONGHELP                        /* undef to save memory     */
 283 #define CFG_PROMPT              "=> "       /* Monitor Command Prompt   */
 284 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 285 #define CFG_CBSIZE              1024        /* Console I/O Buffer Size  */
 286 #else
 287 #define CFG_CBSIZE              256         /* Console I/O Buffer Size  */
 288 #endif
 289 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 290 #define CFG_MAXARGS             16          /* max number of command args   */
 291 #define CFG_BARGSIZE            CFG_CBSIZE  /* Boot Argument Buffer Size    */
 292
 293 #define CFG_MEMTEST_START       0x00100000  /* memtest works on */
 294 #define CFG_MEMTEST_END         0x00f00000  /* 1 ... 15 MB in DRAM  */
 295
 296 #define CFG_LOAD_ADDR           0x100000    /* default load address */
 297
 298 #define CFG_HZ                  1000        /* decrementer freq: 1 ms ticks */
 299
 300 /*
 301  * Various low-level settings
 302  */
 303 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 304 #define CFG_HID0_FINAL          HID0_ICE
 305
 306 /*
 307  * JFFS2 partitions
 308  */
 309
 310 /* No command line, one static partition */
 311 /*
 312 #undef CONFIG_JFFS2_CMDLINE
 313 #define CONFIG_JFFS2_DEV                "nor0"
 314 #define CONFIG_JFFS2_PART_SIZE          0x00400000
 315 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 316 */
 317
 318 /* mtdparts command line support */
 319 /*
 320 #define CONFIG_JFFS2_CMDLINE
 321 #define MTDIDS_DEFAULT          "nor0=alaska-0"
 322 #define MTDPARTS_DEFAULT        "mtdparts=alaska-0:4m(user)"
 323 */
 324
 325 #endif /* __CONFIG_H */