include/configs/CPCI4052.h

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_CPCI405          1       /* ...on a CPCI405 board        */
  39 #define CONFIG_CPCI405_VER2     1       /* ...version 2                 */
  40 #undef  CONFIG_CPCI405_6U               /* enable this for 6U boards    */
  41
  42 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  43
  44 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  45
  46 #define CONFIG_BAUDRATE         9600
  47 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  48
  49 #undef  CONFIG_BOOTARGS
  50 #undef  CONFIG_BOOTCOMMAND
  51
  52 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  53
  54 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  55 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
  56
  57 #define CONFIG_MII              1       /* MII PHY management           */
  58 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  59 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  60 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  61
  62 #define CONFIG_NET_MULTI        1
  63 #undef  CONFIG_HAS_ETH1
  64
  65 #define CONFIG_RTC_M48T35A      1               /* ST Electronics M48 timekeeper */
  66
  67 /*
  68  * BOOTP options
  69  */
  70 #define CONFIG_BOOTP_SUBNETMASK
  71 #define CONFIG_BOOTP_GATEWAY
  72 #define CONFIG_BOOTP_HOSTNAME
  73 #define CONFIG_BOOTP_BOOTPATH
  74 #define CONFIG_BOOTP_DNS
  75 #define CONFIG_BOOTP_DNS2
  76 #define CONFIG_BOOTP_SEND_HOSTNAME
  77
  78
  79 /*
  80  * Command line configuration.
  81  */
  82 #include <config_cmd_default.h>
  83
  84 #define CONFIG_CMD_DHCP
  85 #define CONFIG_CMD_PCI
  86 #define CONFIG_CMD_IRQ
  87 #define CONFIG_CMD_IDE
  88 #define CONFIG_CMD_FAT
  89 #define CONFIG_CMD_ELF
  90 #define CONFIG_CMD_DATE
  91 #define CONFIG_CMD_JFFS2
  92 #define CONFIG_CMD_I2C
  93 #define CONFIG_CMD_MII
  94 #define CONFIG_CMD_PING
  95 #define CONFIG_CMD_BSP
  96 #define CONFIG_CMD_EEPROM
  97
  98
  99 #if 0 /* test-only */
 100 #define CONFIG_NETCONSOLE
 101 #define CONFIG_NET_MULTI
 102
 103 #ifdef CONFIG_NET_MULTI
 104 #define CONFIG_PHY1_ADDR        1       /* PHY address: for NetConsole  */
 105 #endif
 106 #endif
 107
 108 #define CONFIG_MAC_PARTITION
 109 #define CONFIG_DOS_PARTITION
 110
 111 #define CONFIG_SUPPORT_VFAT
 112
 113 #if 0 /* test-only */
 114 #define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
 115 #endif
 116
 117 #define CFG_NAND_LEGACY
 118
 119 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 120
 121 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 122
 123 /*
 124  * Miscellaneous configurable options
 125  */
 126 #define CFG_LONGHELP                    /* undef to save memory         */
 127 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 128
 129 #undef  CFG_HUSH_PARSER                 /* use "hush" command parser    */
 130 #ifdef  CFG_HUSH_PARSER
 131 #define CFG_PROMPT_HUSH_PS2     "> "
 132 #endif
 133
 134 #if defined(CONFIG_CMD_KGDB)
 135 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 136 #else
 137 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 138 #endif
 139 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 140 #define CFG_MAXARGS     16              /* max number of command args   */
 141 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 142
 143 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 144
 145 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 146
 147 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 148
 149 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 150 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 151
 152 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 153 #define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 154 #define CFG_BASE_BAUD       691200
 155
 156 /* The following table includes the supported baudrates */
 157 #define CFG_BAUDRATE_TABLE      \
 158         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 159          57600, 115200, 230400, 460800, 921600 }
 160
 161 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 162 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 163
 164 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 165
 166 #define CONFIG_LOOPW            1       /* enable loopw command         */
 167
 168 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 169
 170 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 171
 172 #define CFG_RX_ETH_BUFFER       16      /* use 16 rx buffer on 405 emac */
 173
 174 /*-----------------------------------------------------------------------
 175  * PCI stuff
 176  *-----------------------------------------------------------------------
 177  */
 178 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 179 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 180 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 181
 182 #define CONFIG_PCI                      /* include pci support          */
 183 #define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 184 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 185                                         /* resource configuration       */
 186
 187 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 188
 189 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 190
 191 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 192
 193 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 194 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 195 #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
 196 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 197 #define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
 198 #define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 199 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 200 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 201 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 202 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 203
 204 /*-----------------------------------------------------------------------
 205  * IDE/ATA stuff
 206  *-----------------------------------------------------------------------
 207  */
 208 #undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
 209 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 210 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 211
 212 #define CFG_IDE_MAXBUS          1               /* max. 1 IDE busses    */
 213 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 214
 215 #define CFG_ATA_BASE_ADDR       0xF0100000
 216 #define CFG_ATA_IDE0_OFFSET     0x0000
 217
 218 #define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O                  */
 219 #define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses  */
 220 #define CFG_ATA_ALT_OFFSET      0x0000  /* Offset for alternate registers       */
 221
 222 /*-----------------------------------------------------------------------
 223  * Start addresses for the final memory configuration
 224  * (Set up by the startup code)
 225  * Please note that CFG_SDRAM_BASE _must_ start at 0
 226  */
 227 #define CFG_SDRAM_BASE          0x00000000
 228 #define CFG_FLASH_BASE          0xFFFC0000
 229 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 230 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
 231 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 232
 233 /*
 234  * For booting Linux, the board info and command line data
 235  * have to be in the first 8 MB of memory, since this is
 236  * the maximum mapped by the Linux kernel during initialization.
 237  */
 238 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 239 /*-----------------------------------------------------------------------
 240  * FLASH organization
 241  */
 242 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 243 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 244
 245 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 246 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 247
 248 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 249 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 250 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 251 /*
 252  * The following defines are added for buggy IOP480 byte interface.
 253  * All other boards should use the standard values (CPCI405 etc.)
 254  */
 255 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 256 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 257 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 258
 259 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 260
 261
 262 /*
 263  * JFFS2 partitions
 264  */
 265
 266 /* No command line, one static partition, use whole device */
 267 #undef CONFIG_JFFS2_CMDLINE
 268 #define CONFIG_JFFS2_DEV                "nor0"
 269 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 270 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 271
 272 /* mtdparts command line support */
 273
 274 /* Use first bank for JFFS2, second bank contains U-Boot.
 275  *
 276  * Note: fake mtd_id's used, no linux mtd map file.
 277  */
 278 /*
 279 #define CONFIG_JFFS2_CMDLINE
 280 #define MTDIDS_DEFAULT          "nor0=cpci4052-0"
 281 #define MTDPARTS_DEFAULT        "mtdparts=cpci4052-0:-(jffs2)"
 282 */
 283
 284 #if 0 /* Use NVRAM for environment variables */
 285 /*-----------------------------------------------------------------------
 286  * NVRAM organization
 287  */
 288 #define CFG_ENV_IS_IN_NVRAM     1       /* use NVRAM for environment vars       */
 289 #define CFG_ENV_SIZE            0x0ff8          /* Size of Environment vars     */
 290 #define CFG_ENV_ADDR            \
 291         (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))   /* Env  */
 292
 293 #else /* Use EEPROM for environment variables */
 294
 295 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 296 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 297 #define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
 298                                    /* total size of a CAT24WC16 is 2048 bytes */
 299 #endif
 300
 301 #define CFG_NVRAM_BASE_ADDR     0xf0200000              /* NVRAM base address   */
 302 #define CFG_NVRAM_SIZE          (32*1024)               /* NVRAM size           */
 303 #define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
 304
 305 /*-----------------------------------------------------------------------
 306  * I2C EEPROM (CAT24WC16) for environment
 307  */
 308 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 309 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 310 #define CFG_I2C_SLAVE           0x7F
 311
 312 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08             */
 313 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 314 /* mask of address bits that overflow into the "EEPROM chip address"    */
 315 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 316 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 317                                         /* 16 byte page write mode using*/
 318                                         /* last 4 bits of the address   */
 319 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 320 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 321
 322 /*-----------------------------------------------------------------------
 323  * Cache Configuration
 324  */
 325 #define CFG_DCACHE_SIZE         16384   /* For AMCC 405 CPUs, older 405 ppc's   */
 326                                         /* have only 8kB, 16kB is save here     */
 327 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 328 #if defined(CONFIG_CMD_KGDB)
 329 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 330 #endif
 331
 332 /*
 333  * Init Memory Controller:
 334  *
 335  * BR0/1 and OR0/1 (FLASH)
 336  */
 337
 338 #define FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank #0        */
 339 #define FLASH_BASE1_PRELIM      0xFFC00000      /* FLASH bank #1        */
 340
 341 /*-----------------------------------------------------------------------
 342  * External Bus Controller (EBC) Setup
 343  */
 344
 345 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 346 #define CFG_EBC_PB0AP           0x92015480
 347 #define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 348
 349 /* Memory Bank 1 (Flash Bank 1) initialization                                  */
 350 #define CFG_EBC_PB1AP           0x92015480
 351 #define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 352
 353 /* Memory Bank 2 (CAN0, 1) initialization                                       */
 354 #define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 355 #define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 356 #define CFG_LED_ADDR            0xF0000380
 357
 358 /* Memory Bank 3 (CompactFlash IDE) initialization                              */
 359 #define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 360 #define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 361
 362 /* Memory Bank 4 (NVRAM/RTC) initialization                                     */
 363 /*#define CFG_EBC_PB4AP           0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1     */
 364 #define CFG_EBC_PB4AP           0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1     */
 365 #define CFG_EBC_PB4CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 366
 367 /* Memory Bank 5 (optional Quart) initialization                                */
 368 #define CFG_EBC_PB5AP           0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
 369 #define CFG_EBC_PB5CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 370
 371 /* Memory Bank 6 (FPGA internal) initialization                                 */
 372 #define CFG_EBC_PB6AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 373 #define CFG_EBC_PB6CR           0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 374 #define CFG_FPGA_BASE_ADDR      0xF0400000
 375
 376 /*-----------------------------------------------------------------------
 377  * FPGA stuff
 378  */
 379 /* FPGA internal regs */
 380 #define CFG_FPGA_MODE           0x00
 381 #define CFG_FPGA_STATUS         0x02
 382 #define CFG_FPGA_TS             0x04
 383 #define CFG_FPGA_TS_LOW         0x06
 384 #define CFG_FPGA_TS_CAP0        0x10
 385 #define CFG_FPGA_TS_CAP0_LOW    0x12
 386 #define CFG_FPGA_TS_CAP1        0x14
 387 #define CFG_FPGA_TS_CAP1_LOW    0x16
 388 #define CFG_FPGA_TS_CAP2        0x18
 389 #define CFG_FPGA_TS_CAP2_LOW    0x1a
 390 #define CFG_FPGA_TS_CAP3        0x1c
 391 #define CFG_FPGA_TS_CAP3_LOW    0x1e
 392
 393 /* FPGA Mode Reg */
 394 #define CFG_FPGA_MODE_CF_RESET      0x0001
 395 #define CFG_FPGA_MODE_DUART_RESET   0x0002
 396 #define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
 397 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 398 #define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
 399 #define CFG_FPGA_MODE_TS_CLEAR      0x2000
 400
 401 /* FPGA Status Reg */
 402 #define CFG_FPGA_STATUS_DIP0    0x0001
 403 #define CFG_FPGA_STATUS_DIP1    0x0002
 404 #define CFG_FPGA_STATUS_DIP2    0x0004
 405 #define CFG_FPGA_STATUS_FLASH   0x0008
 406 #define CFG_FPGA_STATUS_TS_IRQ  0x1000
 407
 408 #define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
 409 #define CFG_FPGA_MAX_SIZE       32*1024     /* 32kByte is enough for XC2S15  */
 410
 411 /* FPGA program pin configuration */
 412 #define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
 413 #define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
 414 #define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
 415 #define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
 416 #define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
 417
 418 /*-----------------------------------------------------------------------
 419  * Definitions for initial stack pointer and data area (in data cache)
 420  */
 421 #define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
 422
 423 #define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
 424 #define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
 425 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 426 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 427 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 428
 429
 430 /*
 431  * Internal Definitions
 432  *
 433  * Boot Flags
 434  */
 435 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 436 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 437
 438 #endif  /* __CONFIG_H */