include/configs/CPCI440.h

   1 /*
   2  * (C) Copyright 2002
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************************************
  25  * board/config_CPCI440.h - configuration for esd CPCI-440 board
  26  ***********************************************************************/
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*-----------------------------------------------------------------------
  32  * High Level Configuration Options
  33  *----------------------------------------------------------------------*/
  34 #define CONFIG_CPCI440          1           /* Board is ebony           */
  35 #define CONFIG_440GP            1           /* Specifc GP support       */
  36 #define CONFIG_440              1           /* ... PPC440 family        */
  37 #define CONFIG_4xx              1           /* ... PPC4xx family        */
  38 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
  39 #undef  CFG_DRAM_TEST                       /* Disable-takes long time! */
  40 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  41
  42 /*-----------------------------------------------------------------------
  43  * Base addresses -- Note these are effective addresses where the
  44  * actual resources get mapped (not physical addresses)
  45  *----------------------------------------------------------------------*/
  46 #define CFG_SDRAM_BASE      0x00000000      /* _must_ be 0              */
  47 #define CFG_FLASH_BASE      0xff800000      /* start of FLASH           */
  48 #if 1
  49 #define CFG_MONITOR_BASE    0xfffc0000      /* start of monitor         */
  50 #else
  51 #define CFG_MONITOR_BASE    0x01fc0000      /* start of monitor         */
  52 #endif
  53 #define CFG_PERIPHERAL_BASE 0xe0000000      /* internal peripherals     */
  54 #define CFG_ISRAM_BASE      0xc0000000      /* internal SRAM            */
  55
  56 #define CFG_FPGA_BASE       (CFG_PERIPHERAL_BASE + 0x08300000)
  57 #define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
  58
  59 /*-----------------------------------------------------------------------
  60  * Initial RAM & stack pointer (placed in internal SRAM)
  61  *----------------------------------------------------------------------*/
  62 #define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address      */
  63 #define CFG_INIT_RAM_END    0x2000          /* End of used area in RAM  */
  64 #define CFG_GBL_DATA_SIZE  128              /* num bytes initial data   */
  65
  66 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  67 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
  68
  69 #define CFG_MONITOR_LEN     (192 * 1024)    /* Reserve 192 kB for Mon   */
  70 #define CFG_MALLOC_LEN      (128 * 1024)    /* Reserve 128 kB for malloc*/
  71
  72 /*-----------------------------------------------------------------------
  73  * Serial Port
  74  *----------------------------------------------------------------------*/
  75 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
  76 #undef CFG_EXT_SERIAL_CLOCK /*   (1843200 * 6)   / * Ext clk @ 11.059 MHz */
  77 #define CONFIG_BAUDRATE         9600
  78
  79 #define CFG_BAUDRATE_TABLE  \
  80     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
  81
  82 /*-----------------------------------------------------------------------
  83  * NVRAM/RTC
  84  *
  85  * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
  86  * The DS1743 code assumes this condition (i.e. -- it assumes the base
  87  * address for the RTC registers is:
  88  *
  89  *      CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
  90  *
  91  *----------------------------------------------------------------------*/
  92 #define CFG_NVRAM_SIZE      (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
  93 #define CONFIG_RTC_DS174x       1                   /* DS1743 RTC               */
  94
  95 /*-----------------------------------------------------------------------
  96  * FLASH related
  97  *----------------------------------------------------------------------*/
  98 #if 1 /* test-only */
  99
 100 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant              */
 101 #define CFG_MAX_FLASH_SECT      128     /* max number of sectors on one chip    */
 102 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 103 #define CFG_FLASH_INCREMENT     0       /* there is only one bank               */
 104 #define CFG_FLASH_PROTECTION    1       /* use hardware protection              */
 105 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 106 #undef CFG_FLASH_BASE
 107 #define CFG_FLASH_BASE          0xFF800000 /* test-only...*/
 108
 109 #else /* test-only */
 110
 111 #define CFG_MAX_FLASH_BANKS     3                   /* number of banks      */
 112 #define CFG_MAX_FLASH_SECT      32                  /* sectors per device   */
 113
 114 #undef  CFG_FLASH_CHECKSUM
 115 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 116 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 117
 118 #endif
 119
 120 /*-----------------------------------------------------------------------
 121  * Environment
 122  *----------------------------------------------------------------------*/
 123 #if 0 /* test-only */
 124 #define CFG_ENV_IS_IN_NVRAM     1           /* Environment uses NVRAM   */
 125 #undef  CFG_ENV_IS_IN_FLASH                 /* ... not in flash         */
 126 #undef  CFG_ENV_IS_IN_EEPROM                /* ... not in EEPROM        */
 127
 128 #define CFG_ENV_SIZE            0x1000      /* Size of Environment vars */
 129 #define CFG_ENV_ADDR            \
 130         (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
 131 #else
 132
 133 #if 0 /* test-only */
 134 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 135 #define CFG_ENV_OFFSET          0x010   /* environment starts at the beginning of the EEPROM */
 136 #define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
 137                                    /* total size of a CAT24WC16 is 2048 bytes */
 138 #else
 139 #define CFG_ENV_IS_IN_FLASH     1
 140 #define CFG_ENV_OFFSET          0x8000  /*   Offset   of Environment Sector     */
 141 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 142 #endif
 143
 144 /*-----------------------------------------------------------------------
 145  * I2C EEPROM (CAT24WC16) for environment
 146  */
 147 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 148 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 149 #define CFG_I2C_SLAVE           0x7F
 150
 151 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08             */
 152 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 153 /* mask of address bits that overflow into the "EEPROM chip address"    */
 154 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 155 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 156                                         /* 16 byte page write mode using*/
 157                                         /* last 4 bits of the address   */
 158 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 159 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 160
 161 #endif
 162
 163 #undef  CONFIG_BOOTARGS
 164 #undef  CONFIG_BOOTCOMMAND
 165
 166 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
 167 #define CONFIG_BAUDRATE         9600
 168
 169 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 170
 171 #define CONFIG_MII              1       /* MII PHY management           */
 172 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 173 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 174
 175
 176 /*
 177  * BOOTP options
 178  */
 179 #define CONFIG_BOOTP_BOOTFILESIZE
 180 #define CONFIG_BOOTP_BOOTPATH
 181 #define CONFIG_BOOTP_GATEWAY
 182 #define CONFIG_BOOTP_HOSTNAME
 183
 184
 185 /*
 186  * Command line configuration.
 187  */
 188 #include <config_cmd_default.h>
 189
 190 #define CONFIG_CMD_IRQ
 191 #define CONFIG_CMD_ELF
 192 #define CONFIG_CMD_DATE
 193 #define CONFIG_CMD_I2C
 194 #define CONFIG_CMD_EEPROM
 195
 196
 197 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 198
 199 #undef CONFIG_SPD_EEPROM       /* don't use SPD EEPROM for setup    */
 200
 201 /*
 202  * Miscellaneous configurable options
 203  */
 204 #define CFG_LONGHELP                    /* undef to save memory         */
 205 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 206 #if defined(CONFIG_CMD_KGDB)
 207 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 208 #else
 209 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 210 #endif
 211 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 212 #define CFG_MAXARGS     16              /* max number of command args   */
 213 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 214
 215 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 216 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 217
 218 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 219 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 220
 221 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 222
 223 #if 0 /* test-only */
 224 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 225 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 226 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 227 #define CFG_I2C_SLAVE           0x7F
 228 #endif
 229
 230
 231 /*-----------------------------------------------------------------------
 232  * PCI stuff
 233  *-----------------------------------------------------------------------
 234  */
 235 #if 0
 236 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 237 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 238 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 239
 240 #define CONFIG_PCI                      /* include pci support          */
 241 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 242 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 243                                         /* resource configuration       */
 244
 245 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 246
 247 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 248
 249 #define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 250 #define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
 251 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 252 #define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 253 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 254 #define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
 255 #define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
 256 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 257 #endif
 258
 259 /*
 260  * For booting Linux, the board info and command line data
 261  * have to be in the first 8 MB of memory, since this is
 262  * the maximum mapped by the Linux kernel during initialization.
 263  */
 264 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 265 /*-----------------------------------------------------------------------
 266  * Cache Configuration
 267  */
 268 #define CFG_DCACHE_SIZE         32768   /* For AMCC 440 CPUs                    */
 269 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 270 #if defined(CONFIG_CMD_KGDB)
 271 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 272 #endif
 273
 274
 275 /* Configuration Port location */
 276 #define CONFIG_PORT_ADDR        0xF0000500
 277
 278 /*-----------------------------------------------------------------------
 279  * Definitions for Serial Presence Detect EEPROM address
 280  * (to get SDRAM settings)
 281  */
 282 #define SPD_EEPROM_ADDRESS      0x50
 283
 284 /*
 285  * Internal Definitions
 286  *
 287  * Boot Flags
 288  */
 289 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 290 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 291
 292 #if defined(CONFIG_CMD_KGDB)
 293 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 294 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 295 #endif
 296 #endif  /* __CONFIG_H */