include/configs/CPCI440.h

   1 /*
   2  * (C) Copyright 2002
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************************************
  25  * board/config_CPCI440.h - configuration for esd CPCI-440 board
  26  ***********************************************************************/
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*-----------------------------------------------------------------------
  32  * High Level Configuration Options
  33  *----------------------------------------------------------------------*/
  34 #define CONFIG_CPCI440          1           /* Board is ebony           */
  35 #define CONFIG_440GP            1           /* Specifc GP support       */
  36 #define CONFIG_4xx              1           /* ... PPC4xx family        */
  37 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
  38 #undef  CFG_DRAM_TEST                       /* Disable-takes long time! */
  39 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  40
  41 /*-----------------------------------------------------------------------
  42  * Base addresses -- Note these are effective addresses where the
  43  * actual resources get mapped (not physical addresses)
  44  *----------------------------------------------------------------------*/
  45 #define CFG_SDRAM_BASE      0x00000000      /* _must_ be 0              */
  46 #define CFG_FLASH_BASE      0xff800000      /* start of FLASH           */
  47 #if 1
  48 #define CFG_MONITOR_BASE    0xfffc0000      /* start of monitor         */
  49 #else
  50 #define CFG_MONITOR_BASE    0x01fc0000      /* start of monitor         */
  51 #endif
  52 #define CFG_PERIPHERAL_BASE 0xe0000000      /* internal peripherals     */
  53 #define CFG_ISRAM_BASE      0xc0000000      /* internal SRAM            */
  54
  55 #define CFG_FPGA_BASE       (CFG_PERIPHERAL_BASE + 0x08300000)
  56 #define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
  57
  58 /*-----------------------------------------------------------------------
  59  * Initial RAM & stack pointer (placed in internal SRAM)
  60  *----------------------------------------------------------------------*/
  61 #define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address      */
  62 #define CFG_INIT_RAM_END    0x2000          /* End of used area in RAM  */
  63 #define CFG_GBL_DATA_SIZE  128              /* num bytes initial data   */
  64
  65 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  66 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
  67
  68 #define CFG_MONITOR_LEN     (192 * 1024)    /* Reserve 192 kB for Mon   */
  69 #define CFG_MALLOC_LEN      (128 * 1024)    /* Reserve 128 kB for malloc*/
  70
  71 /*-----------------------------------------------------------------------
  72  * Serial Port
  73  *----------------------------------------------------------------------*/
  74 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
  75 #undef CFG_EXT_SERIAL_CLOCK /*   (1843200 * 6)   / * Ext clk @ 11.059 MHz */
  76 #define CONFIG_BAUDRATE         9600
  77
  78 #define CFG_BAUDRATE_TABLE  \
  79     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
  80
  81 /*-----------------------------------------------------------------------
  82  * NVRAM/RTC
  83  *
  84  * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
  85  * The DS1743 code assumes this condition (i.e. -- it assumes the base
  86  * address for the RTC registers is:
  87  *
  88  *      CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
  89  *
  90  *----------------------------------------------------------------------*/
  91 #define CFG_NVRAM_SIZE      (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
  92 #define CONFIG_RTC_DS174x       1                   /* DS1743 RTC               */
  93
  94 /*-----------------------------------------------------------------------
  95  * FLASH related
  96  *----------------------------------------------------------------------*/
  97 #if 1 /* test-only */
  98
  99 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant              */
 100 #define CFG_MAX_FLASH_SECT      128     /* max number of sectors on one chip    */
 101 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 102 #define CFG_FLASH_INCREMENT     0       /* there is only one bank               */
 103 #define CFG_FLASH_PROTECTION    1       /* use hardware protection              */
 104 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 105 #undef CFG_FLASH_BASE
 106 #define CFG_FLASH_BASE          0xFF800000 /* test-only...*/
 107
 108 #else /* test-only */
 109
 110 #define CFG_MAX_FLASH_BANKS     3                   /* number of banks      */
 111 #define CFG_MAX_FLASH_SECT      32                  /* sectors per device   */
 112
 113 #undef  CFG_FLASH_CHECKSUM
 114 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 115 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 116
 117 #endif
 118
 119 /*-----------------------------------------------------------------------
 120  * Environment
 121  *----------------------------------------------------------------------*/
 122 #if 0 /* test-only */
 123 #define CFG_ENV_IS_IN_NVRAM     1           /* Environment uses NVRAM   */
 124 #undef  CFG_ENV_IS_IN_FLASH                 /* ... not in flash         */
 125 #undef  CFG_ENV_IS_IN_EEPROM                /* ... not in EEPROM        */
 126
 127 #define CFG_ENV_SIZE            0x1000      /* Size of Environment vars */
 128 #define CFG_ENV_ADDR            \
 129         (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
 130 #else
 131
 132 #if 0 /* test-only */
 133 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 134 #define CFG_ENV_OFFSET          0x010   /* environment starts at the beginning of the EEPROM */
 135 #define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
 136                                    /* total size of a CAT24WC16 is 2048 bytes */
 137 #else
 138 #define CFG_ENV_IS_IN_FLASH     1
 139 #define CFG_ENV_OFFSET          0x8000  /*   Offset   of Environment Sector     */
 140 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 141 #endif
 142
 143 /*-----------------------------------------------------------------------
 144  * I2C EEPROM (CAT24WC16) for environment
 145  */
 146 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 147 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 148 #define CFG_I2C_SLAVE           0x7F
 149
 150 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08             */
 151 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 152 /* mask of address bits that overflow into the "EEPROM chip address"    */
 153 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 154 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 155                                         /* 16 byte page write mode using*/
 156                                         /* last 4 bits of the address   */
 157 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 158 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 159
 160 #endif
 161
 162 #undef  CONFIG_BOOTARGS
 163 #undef  CONFIG_BOOTCOMMAND
 164
 165 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
 166 #define CONFIG_BAUDRATE         9600
 167
 168 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 169
 170 #define CONFIG_MII              1       /* MII PHY management           */
 171 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 172 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 173
 174 #if 0 /* test-only */
 175 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
 176                                 CFG_CMD_IRQ     | \
 177                                 CFG_CMD_I2C     | \
 178                                 CFG_CMD_KGDB    | \
 179                                 CFG_CMD_DHCP    | \
 180                                 CFG_CMD_DATE    | \
 181                                 CFG_CMD_BEDBUG  | \
 182                                 CFG_CMD_ELF     )
 183 #else
 184 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
 185                                 CFG_CMD_IRQ     | \
 186                                 CFG_CMD_ELF     | \
 187                                 CFG_CMD_DATE    | \
 188                                 CFG_CMD_I2C     | \
 189                                 CFG_CMD_EEPROM  )
 190 /* test-only: support fehlt bisher... */
 191 /*                              CFG_CMD_IDE     | \*/
 192 /*                              CFG_CMD_PCI     | \*/
 193 #endif
 194
 195 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 196 #include <cmd_confdefs.h>
 197
 198 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 199
 200 #undef CONFIG_SPD_EEPROM       /* don't use SPD EEPROM for setup    */
 201
 202 /*
 203  * Miscellaneous configurable options
 204  */
 205 #define CFG_LONGHELP                    /* undef to save memory         */
 206 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 207 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 208 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 209 #else
 210 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 211 #endif
 212 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 213 #define CFG_MAXARGS     16              /* max number of command args   */
 214 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 215
 216 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 217 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 218
 219 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 220 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 221
 222 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 223
 224 #if 0 /* test-only */
 225 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 226 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 227 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 228 #define CFG_I2C_SLAVE           0x7F
 229 #endif
 230
 231
 232 /*-----------------------------------------------------------------------
 233  * PCI stuff
 234  *-----------------------------------------------------------------------
 235  */
 236 #if 0
 237 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 238 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 239 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 240
 241 #define CONFIG_PCI                      /* include pci support          */
 242 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 243 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 244                                         /* resource configuration       */
 245
 246 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 247
 248 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 249
 250 #define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 251 #define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
 252 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 253 #define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 254 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 255 #define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
 256 #define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
 257 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 258 #endif
 259
 260 /*
 261  * For booting Linux, the board info and command line data
 262  * have to be in the first 8 MB of memory, since this is
 263  * the maximum mapped by the Linux kernel during initialization.
 264  */
 265 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 266 /*-----------------------------------------------------------------------
 267  * Cache Configuration
 268  */
 269 #define CFG_DCACHE_SIZE         32768   /* For AMCC 440 CPUs                    */
 270 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 271 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 272 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 273 #endif
 274
 275
 276 /* Configuration Port location */
 277 #define CONFIG_PORT_ADDR        0xF0000500
 278
 279 /*-----------------------------------------------------------------------
 280  * Definitions for Serial Presence Detect EEPROM address
 281  * (to get SDRAM settings)
 282  */
 283 #define SPD_EEPROM_ADDRESS      0x50
 284
 285 /*
 286  * Internal Definitions
 287  *
 288  * Boot Flags
 289  */
 290 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 291 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 292
 293 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 294 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 295 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 296 #endif
 297 #endif  /* __CONFIG_H */