include/configs/GEN860T.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Keith Outwater, keith_outwater@mvis.com
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * board/config_GEN860T.h - board specific configuration options
  27  */
  28
  29 #ifndef __CONFIG_GEN860T_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_MPC860
  36 #define CONFIG_GEN860T
  37
  38 /*
  39  * Identify the board
  40  */
  41 #if !defined(CONFIG_SC)
  42 #define CONFIG_IDENT_STRING                             " B2"
  43 #else
  44 #define CONFIG_IDENT_STRING                             " SC"
  45 #endif
  46
  47 /*
  48  * Don't depend on the RTC clock to determine clock frequency -
  49  * the 860's internal rtc uses a 32.768 KHz clock which is
  50  * generated by the DS1337 - and the DS1337 clock can be turned off.
  51  */
  52 #if !defined(CONFIG_SC)
  53 #define CONFIG_8xx_GCLK_FREQ                    66600000
  54 #else
  55 #define CONFIG_8xx_GCLK_FREQ                    48000000
  56 #endif
  57
  58 /*
  59  * The RS-232 console port is on SMC1
  60  */
  61 #define CONFIG_8xx_CONS_SMC1
  62 #define CONFIG_BAUDRATE                                 38400
  63
  64 /*
  65  * Set allowable console baud rates
  66  */
  67 #define CFG_BAUDRATE_TABLE                              { 9600,         \
  68                                                                                   19200,        \
  69                                                                                   38400,        \
  70                                                                                   57600,        \
  71                                                                                   115200,       \
  72                                                                                 }
  73
  74 /*
  75  * Print console information
  76  */
  77 #undef   CFG_CONSOLE_INFO_QUIET
  78
  79 /*
  80  * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
  81  */
  82 #define CONFIG_BOOTDELAY                                5
  83
  84 /*
  85  * Pass the clock frequency to the Linux kernel in units of MHz
  86  */
  87 #define CONFIG_CLOCKS_IN_MHZ
  88
  89 #define CONFIG_PREBOOT          \
  90         "echo;echo"
  91
  92 #undef  CONFIG_BOOTARGS
  93 #define CONFIG_BOOTCOMMAND      \
  94         "bootp;" \
  95         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  96         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  97         "bootm"
  98
  99 /*
 100  * Turn off echo for serial download by default.  Allow baud rate to be changed
 101  * for downloads
 102  */
 103 #undef  CONFIG_LOADS_ECHO
 104 #define CFG_LOADS_BAUD_CHANGE
 105
 106 /*
 107  * Set default load address for tftp network downloads
 108  */
 109 #define CFG_TFTP_LOADADDR                               0x01000000
 110
 111 /*
 112  * Turn off the watchdog timer
 113  */
 114 #undef  CONFIG_WATCHDOG
 115
 116 /*
 117  * Do not reboot if a panic occurs
 118  */
 119 #define CONFIG_PANIC_HANG
 120
 121 /*
 122  * Enable the status LED
 123  */
 124 #define CONFIG_STATUS_LED
 125
 126 /*
 127  * Reset address. We pick an address such that when an instruction
 128  * is executed at that address, a machine check exception occurs
 129  */
 130 #define CFG_RESET_ADDRESS                               ((ulong) -1)
 131
 132 /*
 133  * BOOTP options
 134  */
 135 #define CONFIG_BOOTP_SUBNETMASK
 136 #define CONFIG_BOOTP_GATEWAY
 137 #define CONFIG_BOOTP_HOSTNAME
 138 #define CONFIG_BOOTP_BOOTPATH
 139 #define CONFIG_BOOTP_BOOTFILESIZE
 140
 141
 142 /*
 143  * The GEN860T network interface uses the on-chip 10/100 FEC with
 144  * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
 145  * MII address is hardwired on the board to zero.
 146  */
 147 #define CONFIG_FEC_ENET
 148 #define CFG_DISCOVER_PHY
 149 #define CONFIG_MII
 150 #define CONFIG_PHY_ADDR                         0
 151
 152 /*
 153  * Set default IP stuff just to get bootstrap entries into the
 154  * environment so that we can autoscript the full default environment.
 155  */
 156 #define CONFIG_ETHADDR                                  9a:52:63:15:85:25
 157 #define CONFIG_SERVERIP                                 10.0.4.201
 158 #define CONFIG_IPADDR                                   10.0.4.111
 159
 160 /*
 161  * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
 162  * the MPC860T I2C interface.
 163  */
 164 #define CFG_I2C_EEPROM_ADDR                             0x50
 165 #define CFG_EEPROM_PAGE_WRITE_BITS              6               /* 64 byte pages                */
 166 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  12              /* 10 mS w/ 20% margin  */
 167 #define CFG_I2C_EEPROM_ADDR_LEN                 2               /* need 16 bit address  */
 168 #define CFG_ENV_EEPROM_SIZE                             (32 * 1024)
 169
 170 /*
 171  * Enable I2C and select the hardware/software driver
 172  */
 173 #define CONFIG_HARD_I2C         1                               /* CPM based I2C                        */
 174 #undef  CONFIG_SOFT_I2C                                 /* Bit-banged I2C                       */
 175
 176 #ifdef CONFIG_HARD_I2C
 177 #define CFG_I2C_SPEED           100000                  /* clock speed in Hz            */
 178 #define CFG_I2C_SLAVE           0xFE                    /* I2C slave address            */
 179 #endif
 180
 181 #ifdef CONFIG_SOFT_I2C
 182 #define PB_SCL                          0x00000020              /* PB 26                                        */
 183 #define PB_SDA                          0x00000010              /* PB 27                                        */
 184 #define I2C_INIT                        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 185 #define I2C_ACTIVE                      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 186 #define I2C_TRISTATE            (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 187 #define I2C_READ                        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 188 #define I2C_SDA(bit)            if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 189                                                                 else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 190 #define I2C_SCL(bit)            if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 191                                                                 else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 192 #define I2C_DELAY                       udelay(5)               /* 1/4 I2C clock duration       */
 193 #endif
 194
 195 /*
 196  * Allow environment overwrites by anyone
 197  */
 198 #define CONFIG_ENV_OVERWRITE
 199
 200 #if !defined(CONFIG_SC)
 201 /*
 202  * The MPC860's internal RTC is horribly broken in rev D masks. Three
 203  * internal MPC860T circuit nodes were inadvertently left floating; this
 204  * causes KAPWR current in power down mode to be three orders of magnitude
 205  * higher than specified in the datasheet (from 10 uA to 10 mA).  No
 206  * reasonable battery can keep that kind RTC running during powerdown for any
 207  * length of time, so we use an external RTC on the I2C bus instead.
 208  */
 209 #define CONFIG_RTC_DS1337
 210 #define CFG_I2C_RTC_ADDR                                0x68
 211
 212 #else
 213 /*
 214  * No external RTC on SC variant, so we're stuck with the internal one.
 215  */
 216 #define CONFIG_RTC_MPC8xx
 217 #endif
 218
 219 /*
 220  * Power On Self Test support
 221  */
 222 #define CONFIG_POST                       ( CFG_POST_CACHE              | \
 223                                                                 CFG_POST_MEMORY         | \
 224                                                                 CFG_POST_CPU            | \
 225                                                                 CFG_POST_UART           | \
 226                                                                 CFG_POST_SPR )
 227
 228
 229 /*
 230  * Command line configuration.
 231  */
 232 #include <config_cmd_default.h>
 233
 234 #define CONFIG_CMD_ASKENV
 235 #define CONFIG_CMD_DHCP
 236 #define CONFIG_CMD_I2C
 237 #define CONFIG_CMD_EEPROM
 238 #define CONFIG_CMD_REGINFO
 239 #define CONFIG_CMD_IMMAP
 240 #define CONFIG_CMD_ELF
 241 #define CONFIG_CMD_DATE
 242 #define CONFIG_CMD_FPGA
 243 #define CONFIG_CMD_MII
 244 #define CONFIG_CMD_BEDBUG
 245
 246 #if !defined(CONFIG_SC)
 247     #define CONFIG_CMD_DOC
 248 #endif
 249
 250 #ifdef CONFIG_POST
 251 #define CONFIG_CMD_DIAG
 252 #endif
 253
 254 /*
 255  * There is no IDE/PCMCIA hardware support on the board.
 256  */
 257 #undef  CONFIG_IDE_PCMCIA
 258 #undef  CONFIG_IDE_LED
 259 #undef  CONFIG_IDE_RESET
 260
 261 /*
 262  * Enable the call to misc_init_r() for miscellaneous platform
 263  * dependent initialization.
 264  */
 265 #define CONFIG_MISC_INIT_R
 266
 267 /*
 268  * Enable call to last_stage_init() so we can twiddle some LEDS :)
 269  */
 270 #define CONFIG_LAST_STAGE_INIT
 271
 272 /*
 273  * Virtex2 FPGA configuration support
 274  */
 275 #define CONFIG_FPGA_COUNT               1
 276 #define CONFIG_FPGA
 277 #define CONFIG_FPGA_XILINX
 278 #define CONFIG_FPGA_VIRTEX2
 279 #define CFG_FPGA_PROG_FEEDBACK
 280
 281
 282 #define CFG_NAND_LEGACY
 283
 284 /*
 285  * Verbose help from command monitor.
 286  */
 287 #define CFG_LONGHELP
 288 #if !defined(CONFIG_SC)
 289 #define CFG_PROMPT                      "B2> "
 290 #else
 291 #define CFG_PROMPT                      "SC> "
 292 #endif
 293
 294
 295 /*
 296  * Use the "hush" command parser
 297  */
 298 #define CFG_HUSH_PARSER
 299 #define CFG_PROMPT_HUSH_PS2     "> "
 300
 301 /*
 302  * Set buffer size for console I/O
 303  */
 304 #if defined(CONFIG_CMD_KGDB)
 305 #define CFG_CBSIZE                      1024
 306 #else
 307 #define CFG_CBSIZE                      256
 308 #endif
 309
 310 /*
 311  * Print buffer size
 312  */
 313 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 314
 315 /*
 316  * Maximum number of arguments that a command can accept
 317  */
 318 #define CFG_MAXARGS                     16
 319
 320 /*
 321  * Boot argument buffer size
 322  */
 323 #define CFG_BARGSIZE            CFG_CBSIZE
 324
 325 /*
 326  * Default memory test range
 327  */
 328 #define CFG_MEMTEST_START       0x0100000
 329 #define CFG_MEMTEST_END         (CFG_MEMTEST_START  + (128 * 1024))
 330
 331 /*
 332  * Select the more full-featured memory test
 333  */
 334 #define CFG_ALT_MEMTEST
 335
 336 /*
 337  * Default load address
 338  */
 339 #define CFG_LOAD_ADDR           0x01000000
 340
 341 /*
 342  * Set decrementer frequency (1 ms ticks)
 343  */
 344 #define CFG_HZ                          1000
 345
 346 /*
 347  * Device memory map (after SDRAM remap to 0x0):
 348  *
 349  * CS           Device                          Base Addr       Size
 350  * ----------------------------------------------------
 351  * CS0*         Flash                           0x40000000      64 M
 352  * CS1*         SDRAM                           0x00000000      16 M
 353  * CS2*         Disk-On-Chip            0x50000000      32 K
 354  * CS3*         FPGA                            0x60000000      64 M
 355  * CS4*         SelectMap                       0x70000000      32 K
 356  * CS5*         Mil-Std 1553 I/F        0x80000000      32 K
 357  * CS6*         Unused
 358  * CS7*         Unused
 359  * IMMR         860T Registers          0xfff00000
 360  */
 361
 362 /*
 363  * Base addresses and block sizes
 364  */
 365 #define CFG_IMMR                        0xFF000000
 366
 367 #define SDRAM_BASE                      0x00000000
 368 #define SDRAM_SIZE                      (64 * 1024 * 1024)
 369
 370 #define FLASH_BASE                      0x40000000
 371 #define FLASH_SIZE                      (16 * 1024 * 1024)
 372
 373 #define DOC_BASE                        0x50000000
 374 #define DOC_SIZE                        (32 * 1024)
 375
 376 #define FPGA_BASE                       0x60000000
 377 #define FPGA_SIZE                       (64 * 1024 * 1024)
 378
 379 #define SELECTMAP_BASE          0x70000000
 380 #define SELECTMAP_SIZE          (32 * 1024)
 381
 382 #define M1553_BASE                      0x80000000
 383 #define M1553_SIZE                      (64 * 1024)
 384
 385 /*
 386  * Definitions for initial stack pointer and data area (in DPRAM)
 387  */
 388 #define CFG_INIT_RAM_ADDR               CFG_IMMR
 389 #define CFG_INIT_RAM_END                0x2F00  /* End of used area in DPRAM            */
 390 #define CFG_INIT_DATA_SIZE              64      /* # bytes reserved for initial data*/
 391 #define CFG_GBL_DATA_OFFSET             (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
 392 #define CFG_INIT_SP_OFFSET              CFG_GBL_DATA_OFFSET
 393
 394 /*
 395  * Start addresses for the final memory configuration
 396  * (Set up by the startup code)
 397  * Please note that CFG_SDRAM_BASE _must_ start at 0
 398  */
 399 #define CFG_SDRAM_BASE                  SDRAM_BASE
 400
 401 /*
 402  * FLASH organization
 403  */
 404 #define CFG_FLASH_BASE                  FLASH_BASE
 405 #define CFG_FLASH_SIZE                  FLASH_SIZE
 406 #define CFG_FLASH_SECT_SIZE             (128 * 1024)
 407 #define CFG_MAX_FLASH_BANKS             1
 408 #define CFG_MAX_FLASH_SECT              128
 409
 410 /*
 411  * The timeout values are for an entire chip and are in milliseconds.
 412  * Yes I know that the write timeout is huge.  Accroding to the
 413  * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
 414  * case VCC and temp after 100K programming cycles.  It works out
 415  * to 280 minutes (might as well be forever).
 416  */
 417 #define CFG_FLASH_ERASE_TOUT    (CFG_MAX_FLASH_SECT * 5000)
 418 #define CFG_FLASH_WRITE_TOUT    (CFG_MAX_FLASH_SECT * 128 * 1024 * 1)
 419
 420 /*
 421  * Allow direct writes to FLASH from tftp transfers (** dangerous **)
 422  */
 423 #define CFG_DIRECT_FLASH_TFTP
 424
 425 /*
 426  * Reserve memory for U-Boot.
 427  */
 428 #define CFG_MAX_UBOOT_SECTS             4
 429 #define CFG_MONITOR_LEN                 (CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)
 430 #define CFG_MONITOR_BASE                CFG_FLASH_BASE
 431
 432 /*
 433  * Select environment placement.  NOTE that u-boot.lds must
 434  * be edited if this is changed!
 435  */
 436 #undef  CFG_ENV_IS_IN_FLASH
 437 #define CFG_ENV_IS_IN_EEPROM
 438
 439 #if defined(CFG_ENV_IS_IN_EEPROM)
 440 #define CFG_ENV_SIZE                    (2 * 1024)
 441 #define CFG_ENV_OFFSET                  (CFG_ENV_EEPROM_SIZE - (8 * 1024))
 442 #else
 443 #define CFG_ENV_SIZE                    0x1000
 444 #define CFG_ENV_SECT_SIZE               CFG_FLASH_SECT_SIZE
 445
 446 /*
 447  * This ultimately gets passed right into the linker script, so we have to
 448  * use a number :(
 449  */
 450 #define CFG_ENV_OFFSET                  0x060000
 451 #endif
 452
 453 /*
 454  * Reserve memory for malloc()
 455  */
 456 #define CFG_MALLOC_LEN          (128 * 1024)
 457
 458 /*
 459  * For booting Linux, the board info and command line data
 460  * have to be in the first 8 MB of memory, since this is
 461  * the maximum mapped by the Linux kernel during initialization.
 462  */
 463 #define CFG_BOOTMAPSZ           (8 * 1024 * 1024)
 464
 465 /*
 466  * Cache Configuration
 467  */
 468 #define CFG_CACHELINE_SIZE              16      /* For all MPC8xx CPUs                          */
 469 #if defined(CONFIG_CMD_KGDB)
 470 #define CFG_CACHELINE_SHIFT             4       /* log base 2 of above value            */
 471 #endif
 472
 473 /*------------------------------------------------------------------------
 474  * SYPCR - System Protection Control                                                    UM 11-9
 475  * -----------------------------------------------------------------------
 476  * SYPCR can only be written once after reset!
 477  *
 478  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 479  */
 480 #if defined(CONFIG_WATCHDOG)
 481 #define CFG_SYPCR       ( SYPCR_SWTC    | \
 482                                           SYPCR_BMT     | \
 483                                           SYPCR_BME     | \
 484                                           SYPCR_SWF     | \
 485                                           SYPCR_SWE     | \
 486                                           SYPCR_SWRI    | \
 487                                           SYPCR_SWP               \
 488                                         )
 489 #else
 490 #define CFG_SYPCR       ( SYPCR_SWTC    | \
 491                                           SYPCR_BMT     | \
 492                                           SYPCR_BME     | \
 493                                           SYPCR_SWF     | \
 494                                           SYPCR_SWP               \
 495                                         )
 496 #endif
 497
 498 /*-----------------------------------------------------------------------
 499  * SIUMCR - SIU Module Configuration                                                    UM 11-6
 500  *-----------------------------------------------------------------------
 501  * Set debug pin mux, enable SPKROUT and GPLB5*.
 502  */
 503 #define CFG_SIUMCR      ( SIUMCR_DBGC11 | \
 504                                           SIUMCR_DBPC11 | \
 505                                           SIUMCR_MLRC11 | \
 506                                           SIUMCR_GB5E     \
 507                                         )
 508
 509 /*-----------------------------------------------------------------------
 510  * TBSCR - Time Base Status and Control                                                 UM 11-26
 511  *-----------------------------------------------------------------------
 512  * Clear Reference Interrupt Status, Timebase freeze enabled
 513  */
 514 #define CFG_TBSCR       ( TBSCR_REFA | \
 515                                           TBSCR_REFB | \
 516                                           TBSCR_TBF        \
 517                                         )
 518
 519 /*-----------------------------------------------------------------------
 520  * RTCSC - Real-Time Clock Status and Control Register                  UM 11-27
 521  *-----------------------------------------------------------------------
 522  */
 523 #define CFG_RTCSC       ( RTCSC_SEC     | \
 524                                           RTCSC_ALR | \
 525                                           RTCSC_RTF | \
 526                                           RTCSC_RTE       \
 527                                         )
 528
 529 /*-----------------------------------------------------------------------
 530  * PISCR - Periodic Interrupt Status and Control                                UM 11-31
 531  *-----------------------------------------------------------------------
 532  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 533  */
 534 #define CFG_PISCR       ( PISCR_PS              | \
 535                                           PISCR_PITF      \
 536                                         )
 537
 538 /*-----------------------------------------------------------------------
 539  * PLPRCR - PLL, Low-Power, and Reset Control Register                  UM 15-30
 540  *-----------------------------------------------------------------------
 541  * Reset PLL lock status sticky bit, timer expired status bit and timer
 542  * interrupt status bit. Set MF for 1:2:1 mode.
 543  */
 544 #define CFG_PLPRCR      ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)    | \
 545                                           PLPRCR_SPLSS  | \
 546                                           PLPRCR_TEXPS  | \
 547                                           PLPRCR_TMIST    \
 548                                         )
 549
 550 /*-----------------------------------------------------------------------
 551  * SCCR - System Clock and reset Control Register                               UM 15-27
 552  *-----------------------------------------------------------------------
 553  * Set clock output, timebase and RTC source and divider,
 554  * power management and some other internal clocks
 555  */
 556 #define SCCR_MASK   SCCR_EBDF11
 557
 558 #if !defined(CONFIG_SC)
 559 #define CFG_SCCR        ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 560                                           SCCR_COM00            |       /* full strength CLKOUT */ \
 561                                           SCCR_DFSYNC00         |       /* SYNCLK / 1 (normal)  */ \
 562                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 563                                           SCCR_DFNL000          | \
 564                                           SCCR_DFNH000            \
 565                                         )
 566 #else
 567 #define CFG_SCCR        ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 568                                           SCCR_COM00            |       /* full strength CLKOUT */ \
 569                                           SCCR_DFSYNC00         |       /* SYNCLK / 1 (normal)  */ \
 570                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 571                                           SCCR_DFNL000          | \
 572                                           SCCR_DFNH000          | \
 573                                           SCCR_RTDIV            | \
 574                                           SCCR_RTSEL              \
 575                                         )
 576 #endif
 577
 578 /*-----------------------------------------------------------------------
 579  * DER - Debug Enable Register                                                                  UM 37-46
 580  *-----------------------------------------------------------------------
 581  * Mask all events that can cause entry into debug mode
 582  */
 583 #define CFG_DER                         0
 584
 585 /*
 586  * Initialize Memory Controller:
 587  *
 588  * BR0 and OR0 (FLASH memory)
 589  */
 590 #define FLASH_BASE0_PRELIM      FLASH_BASE
 591
 592 /*
 593  * Flash address mask
 594  */
 595 #define CFG_PRELIM_OR_AM        0xfe000000
 596
 597 /*
 598  * FLASH timing:
 599  * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
 600  */
 601 #define CFG_OR_TIMING_FLASH     ( OR_CSNT_SAM   | \
 602                                                           OR_ACS_DIV2   | \
 603                                                           OR_BI                 | \
 604                                                           OR_SCY_2_CLK  | \
 605                                                           OR_TRLX               | \
 606                                                           OR_EHTR                 \
 607                                                         )
 608
 609 #define CFG_OR0_PRELIM  ( CFG_PRELIM_OR_AM              | \
 610                                                   CFG_OR_TIMING_FLASH     \
 611                                                 )
 612
 613 #define CFG_BR0_PRELIM  ( (FLASH_BASE0_PRELIM & BR_BA_MSK)      | \
 614                                                   BR_MS_GPCM                                            | \
 615                                                   BR_PS_8                                                       | \
 616                                                   BR_V                                                            \
 617                                                 )
 618
 619 /*
 620  * SDRAM configuration
 621  */
 622 #define CFG_OR1_AM      0xfc000000
 623 #define CFG_OR1         ( (CFG_OR1_AM & OR_AM_MSK)      | \
 624                                           OR_CSNT_SAM                             \
 625                                         )
 626
 627 #define CFG_BR1         ( (SDRAM_BASE & BR_BA_MSK)      | \
 628                                           BR_MS_UPMA                            | \
 629                                           BR_PS_32                                      | \
 630                                           BR_V                                            \
 631                                         )
 632
 633 /*
 634  * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
 635  * of 256 MBit SDRAM
 636  */
 637 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16
 638
 639 /*
 640  * Periodic timer for refresh @ 33 MHz system clock
 641  */
 642 #define CFG_MAMR_PTA    64
 643
 644 /*
 645  * MAMR settings for SDRAM
 646  */
 647 #define CFG_MAMR_8COL   ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT)      | \
 648                                                   MAMR_PTAE                             | \
 649                                                   MAMR_AMA_TYPE_1                       | \
 650                                                   MAMR_DSA_1_CYCL                       | \
 651                                                   MAMR_G0CLA_A10                        | \
 652                                                   MAMR_RLFA_1X                          | \
 653                                                   MAMR_WLFA_1X                          | \
 654                                                   MAMR_TLFA_4X                            \
 655                                                 )
 656
 657 /*
 658  * CS2* configuration for Disk On Chip:
 659  * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
 660  * no burst.
 661  */
 662 #define CFG_OR2_PRELIM  ( (0xffff0000 & OR_AM_MSK)      | \
 663                                                   OR_CSNT_SAM                           | \
 664                                                   OR_ACS_DIV2                           | \
 665                                                   OR_BI                                         | \
 666                                                   OR_SCY_2_CLK                          | \
 667                                                   OR_TRLX                                       | \
 668                                                   OR_EHTR                                         \
 669                                                 )
 670
 671 #define CFG_BR2_PRELIM  ( (DOC_BASE & BR_BA_MSK)        | \
 672                                                   BR_PS_8                                       | \
 673                                                   BR_MS_GPCM                            | \
 674                                                   BR_V                                            \
 675                                                 )
 676
 677 /*
 678  * CS3* configuration for FPGA:
 679  * 33 MHz bus with SCY=15, no burst.
 680  * The FPGA uses TA and TEA to terminate bus cycles, but we
 681  * clear SETA and set the cycle length to a large number so that
 682  * the cycle will still complete even if there is a configuration
 683  * error that prevents TA from asserting on FPGA accesss.
 684  */
 685 #define CFG_OR3_PRELIM  ( (0xfc000000 & OR_AM_MSK)  | \
 686                                                   OR_SCY_15_CLK                         | \
 687                                                   OR_BI                                           \
 688                                                 )
 689
 690 #define CFG_BR3_PRELIM  ( (FPGA_BASE & BR_BA_MSK)       | \
 691                                                   BR_PS_32                                      | \
 692                                                   BR_MS_GPCM                            | \
 693                                                   BR_V                                            \
 694                                                 )
 695 /*
 696  * CS4* configuration for FPGA SelectMap configuration interface.
 697  * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
 698  * of GCLK1_50
 699  */
 700 #define CFG_OR4_PRELIM  ( (0xffff0000 & OR_AM_MSK)      | \
 701                                                   OR_G5LS                                               | \
 702                                                   OR_BI                                                   \
 703                                                 )
 704
 705 #define CFG_BR4_PRELIM  ( (SELECTMAP_BASE & BR_BA_MSK)  | \
 706                                                   BR_PS_8                                               | \
 707                                                   BR_MS_UPMB                                    | \
 708                                                   BR_V                                                    \
 709                                                 )
 710
 711 /*
 712  * CS5* configuration for Mil-Std 1553 databus interface.
 713  * 33 MHz bus, GPCM, no burst.
 714  * The 1553 interface  uses TA and TEA to terminate bus cycles,
 715  * but we clear SETA and set the cycle length to a large number so that
 716  * the cycle will still complete even if there is a configuration
 717  * error that prevents TA from asserting on FPGA accesss.
 718  */
 719 #define CFG_OR5_PRELIM  ( (0xffff0000 & OR_AM_MSK)  | \
 720                                                   OR_SCY_15_CLK                         | \
 721                                                   OR_EHTR                                       | \
 722                                                   OR_TRLX                                       | \
 723                                                   OR_CSNT_SAM                           | \
 724                                                   OR_BI                                           \
 725                                                 )
 726
 727 #define CFG_BR5_PRELIM  ( (M1553_BASE & BR_BA_MSK)      | \
 728                                                   BR_PS_16                                      | \
 729                                                   BR_MS_GPCM                            | \
 730                                                   BR_V                                            \
 731                                                 )
 732
 733 /*
 734  * Boot Flags
 735  */
 736 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH     */
 737 #define BOOTFLAG_WARM   0x02    /* Software reboot                                      */
 738
 739 /*
 740  * Disk On Chip (millenium) configuration
 741  */
 742 #if !defined(CONFIG_SC)
 743 #define CFG_MAX_DOC_DEVICE      1
 744 #undef  CFG_DOC_SUPPORT_2000
 745 #define CFG_DOC_SUPPORT_MILLENNIUM
 746 #undef  CFG_DOC_PASSIVE_PROBE
 747 #endif
 748
 749 /*
 750  * FEC interrupt assignment
 751  */
 752 #define FEC_INTERRUPT   SIU_LEVEL1
 753
 754 /*
 755  * Sanity checks
 756  */
 757 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 758 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
 759 #endif
 760
 761 #endif  /* __CONFIG_GEN860T_H */
 762
 763 /* vim: set ts=4 tw=78 ai shiftwidth=4: */