include/configs/GEN860T.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Keith Outwater, keith_outwater@mvis.com
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * board/config_GEN860T.h - board specific configuration options
  27  */
  28
  29 #ifndef __CONFIG_GEN860T_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_MPC860
  36 #define CONFIG_GEN860T
  37
  38 /*
  39  * Identify the board
  40  */
  41 #if !defined(CONFIG_SC)
  42 #define CONFIG_IDENT_STRING                             " B2"
  43 #else
  44 #define CONFIG_IDENT_STRING                             " SC"
  45 #endif
  46
  47 /*
  48  * Don't depend on the RTC clock to determine clock frequency -
  49  * the 860's internal rtc uses a 32.768 KHz clock which is
  50  * generated by the DS1337 - and the DS1337 clock can be turned off.
  51  */
  52 #if !defined(CONFIG_SC)
  53 #define CONFIG_8xx_GCLK_FREQ                    66600000
  54 #else
  55 #define CONFIG_8xx_GCLK_FREQ                    48000000
  56 #endif
  57
  58 /*
  59  * The RS-232 console port is on SMC1
  60  */
  61 #define CONFIG_8xx_CONS_SMC1
  62 #define CONFIG_BAUDRATE                                 38400
  63
  64 /*
  65  * Set allowable console baud rates
  66  */
  67 #define CFG_BAUDRATE_TABLE                              { 9600,         \
  68                                                                                   19200,        \
  69                                                                                   38400,        \
  70                                                                                   57600,        \
  71                                                                                   115200,       \
  72                                                                                 }
  73
  74 /*
  75  * Print console information
  76  */
  77 #undef   CFG_CONSOLE_INFO_QUIET
  78
  79 /*
  80  * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
  81  */
  82 #define CONFIG_BOOTDELAY                                5
  83
  84 /*
  85  * Pass the clock frequency to the Linux kernel in units of MHz
  86  */
  87 #define CONFIG_CLOCKS_IN_MHZ
  88
  89 #define CONFIG_PREBOOT          \
  90         "echo;echo"
  91
  92 #undef  CONFIG_BOOTARGS
  93 #define CONFIG_BOOTCOMMAND      \
  94         "bootp;" \
  95         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  96         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  97         "bootm"
  98
  99 /*
 100  * Turn off echo for serial download by default.  Allow baud rate to be changed
 101  * for downloads
 102  */
 103 #undef  CONFIG_LOADS_ECHO
 104 #define CFG_LOADS_BAUD_CHANGE
 105
 106 /*
 107  * Set default load address for tftp network downloads
 108  */
 109 #define CFG_TFTP_LOADADDR                               0x01000000
 110
 111 /*
 112  * Turn off the watchdog timer
 113  */
 114 #undef  CONFIG_WATCHDOG
 115
 116 /*
 117  * Do not reboot if a panic occurs
 118  */
 119 #define CONFIG_PANIC_HANG
 120
 121 /*
 122  * Enable the status LED
 123  */
 124 #define CONFIG_STATUS_LED
 125
 126 /*
 127  * Reset address. We pick an address such that when an instruction
 128  * is executed at that address, a machine check exception occurs
 129  */
 130 #define CFG_RESET_ADDRESS                               ((ulong) -1)
 131
 132 /*
 133  * BOOTP options
 134  */
 135 #define CONFIG_BOOTP_MASK                               ( CONFIG_BOOTP_DEFAULT          | \
 136                                                                                   CONFIG_BOOTP_BOOTFILESIZE   \
 137                                                                                 )
 138
 139 /*
 140  * The GEN860T network interface uses the on-chip 10/100 FEC with
 141  * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
 142  * MII address is hardwired on the board to zero.
 143  */
 144 #define CONFIG_FEC_ENET
 145 #define CFG_DISCOVER_PHY
 146 #define CONFIG_MII
 147 #define CONFIG_PHY_ADDR                         0
 148
 149 /*
 150  * Set default IP stuff just to get bootstrap entries into the
 151  * environment so that we can autoscript the full default environment.
 152  */
 153 #define CONFIG_ETHADDR                                  9a:52:63:15:85:25
 154 #define CONFIG_SERVERIP                                 10.0.4.201
 155 #define CONFIG_IPADDR                                   10.0.4.111
 156
 157 /*
 158  * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
 159  * the MPC860T I2C interface.
 160  */
 161 #define CFG_I2C_EEPROM_ADDR                             0x50
 162 #define CFG_EEPROM_PAGE_WRITE_BITS              6               /* 64 byte pages                */
 163 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  12              /* 10 mS w/ 20% margin  */
 164 #define CFG_I2C_EEPROM_ADDR_LEN                 2               /* need 16 bit address  */
 165 #define CFG_ENV_EEPROM_SIZE                             (32 * 1024)
 166
 167 /*
 168  * Enable I2C and select the hardware/software driver
 169  */
 170 #define CONFIG_HARD_I2C         1                               /* CPM based I2C                        */
 171 #undef  CONFIG_SOFT_I2C                                 /* Bit-banged I2C                       */
 172
 173 #ifdef CONFIG_HARD_I2C
 174 #define CFG_I2C_SPEED           100000                  /* clock speed in Hz            */
 175 #define CFG_I2C_SLAVE           0xFE                    /* I2C slave address            */
 176 #endif
 177
 178 #ifdef CONFIG_SOFT_I2C
 179 #define PB_SCL                          0x00000020              /* PB 26                                        */
 180 #define PB_SDA                          0x00000010              /* PB 27                                        */
 181 #define I2C_INIT                        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 182 #define I2C_ACTIVE                      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 183 #define I2C_TRISTATE            (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 184 #define I2C_READ                        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 185 #define I2C_SDA(bit)            if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 186                                                                 else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 187 #define I2C_SCL(bit)            if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 188                                                                 else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 189 #define I2C_DELAY                       udelay(5)               /* 1/4 I2C clock duration       */
 190 #endif
 191
 192 /*
 193  * Allow environment overwrites by anyone
 194  */
 195 #define CONFIG_ENV_OVERWRITE
 196
 197 #if !defined(CONFIG_SC)
 198 /*
 199  * The MPC860's internal RTC is horribly broken in rev D masks. Three
 200  * internal MPC860T circuit nodes were inadvertently left floating; this
 201  * causes KAPWR current in power down mode to be three orders of magnitude
 202  * higher than specified in the datasheet (from 10 uA to 10 mA).  No
 203  * reasonable battery can keep that kind RTC running during powerdown for any
 204  * length of time, so we use an external RTC on the I2C bus instead.
 205  */
 206 #define CONFIG_RTC_DS1337
 207 #define CFG_I2C_RTC_ADDR                                0x68
 208
 209 #else
 210 /*
 211  * No external RTC on SC variant, so we're stuck with the internal one.
 212  */
 213 #define CONFIG_RTC_MPC8xx
 214 #endif
 215
 216 /*
 217  * Power On Self Test support
 218  */
 219 #define CONFIG_POST                       ( CFG_POST_CACHE              | \
 220                                                                 CFG_POST_MEMORY         | \
 221                                                                 CFG_POST_CPU            | \
 222                                                                 CFG_POST_UART           | \
 223                                                                 CFG_POST_SPR )
 224
 225 #ifdef CONFIG_POST
 226 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
 227 #else
 228 #define CFG_CMD_POST_DIAG               0
 229 #endif
 230
 231 /*
 232  * List of available monitor commands.  Use the system default list
 233  * plus add some of the "non-standard" commands back in.
 234  * See ./cmd_confdefs.h
 235  */
 236 #define BASE_CONFIG_COMMANDS    ( CONFIG_CMD_DFL        | \
 237                                                                 CFG_CMD_ASKENV  | \
 238                                                                 CFG_CMD_DHCP    | \
 239                                                                 CFG_CMD_I2C             | \
 240                                                                 CFG_CMD_EEPROM  | \
 241                                                                 CFG_CMD_REGINFO | \
 242                                                                 CFG_CMD_IMMAP   | \
 243                                                                 CFG_CMD_ELF             | \
 244                                                                 CFG_CMD_DATE    | \
 245                                                                 CFG_CMD_FPGA    | \
 246                                                                 CFG_CMD_MII     | \
 247                                                                 CFG_CMD_BEDBUG  | \
 248                                                                 CFG_CMD_POST_DIAG )
 249
 250 #if !defined(CONFIG_SC)
 251 #define CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC )
 252 #else
 253 #define CONFIG_COMMANDS BASE_CONFIG_COMMANDS
 254 #endif
 255
 256 /*
 257  * There is no IDE/PCMCIA hardware support on the board.
 258  */
 259 #undef  CONFIG_IDE_PCMCIA
 260 #undef  CONFIG_IDE_LED
 261 #undef  CONFIG_IDE_RESET
 262
 263 /*
 264  * Enable the call to misc_init_r() for miscellaneous platform
 265  * dependent initialization.
 266  */
 267 #define CONFIG_MISC_INIT_R
 268
 269 /*
 270  * Enable call to last_stage_init() so we can twiddle some LEDS :)
 271  */
 272 #define CONFIG_LAST_STAGE_INIT
 273
 274 /*
 275  * Virtex2 FPGA configuration support
 276  */
 277 #define CONFIG_FPGA_COUNT               1
 278 #define CONFIG_FPGA                             CFG_XILINX_VIRTEX2
 279 #define CFG_FPGA_PROG_FEEDBACK
 280
 281
 282 /************************************************************************
 283  * This must be included AFTER the definition of any CONFIG_COMMANDS
 284  */
 285 #include <cmd_confdefs.h>
 286
 287 #define CFG_NAND_LEGACY
 288
 289 /*
 290  * Verbose help from command monitor.
 291  */
 292 #define CFG_LONGHELP
 293 #if !defined(CONFIG_SC)
 294 #define CFG_PROMPT                      "B2> "
 295 #else
 296 #define CFG_PROMPT                      "SC> "
 297 #endif
 298
 299
 300 /*
 301  * Use the "hush" command parser
 302  */
 303 #define CFG_HUSH_PARSER
 304 #define CFG_PROMPT_HUSH_PS2     "> "
 305
 306 /*
 307  * Set buffer size for console I/O
 308  */
 309 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 310 #define CFG_CBSIZE                      1024
 311 #else
 312 #define CFG_CBSIZE                      256
 313 #endif
 314
 315 /*
 316  * Print buffer size
 317  */
 318 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 319
 320 /*
 321  * Maximum number of arguments that a command can accept
 322  */
 323 #define CFG_MAXARGS                     16
 324
 325 /*
 326  * Boot argument buffer size
 327  */
 328 #define CFG_BARGSIZE            CFG_CBSIZE
 329
 330 /*
 331  * Default memory test range
 332  */
 333 #define CFG_MEMTEST_START       0x0100000
 334 #define CFG_MEMTEST_END         (CFG_MEMTEST_START  + (128 * 1024))
 335
 336 /*
 337  * Select the more full-featured memory test
 338  */
 339 #define CFG_ALT_MEMTEST
 340
 341 /*
 342  * Default load address
 343  */
 344 #define CFG_LOAD_ADDR           0x01000000
 345
 346 /*
 347  * Set decrementer frequency (1 ms ticks)
 348  */
 349 #define CFG_HZ                          1000
 350
 351 /*
 352  * Device memory map (after SDRAM remap to 0x0):
 353  *
 354  * CS           Device                          Base Addr       Size
 355  * ----------------------------------------------------
 356  * CS0*         Flash                           0x40000000      64 M
 357  * CS1*         SDRAM                           0x00000000      16 M
 358  * CS2*         Disk-On-Chip            0x50000000      32 K
 359  * CS3*         FPGA                            0x60000000      64 M
 360  * CS4*         SelectMap                       0x70000000      32 K
 361  * CS5*         Mil-Std 1553 I/F        0x80000000      32 K
 362  * CS6*         Unused
 363  * CS7*         Unused
 364  * IMMR         860T Registers          0xfff00000
 365  */
 366
 367 /*
 368  * Base addresses and block sizes
 369  */
 370 #define CFG_IMMR                        0xFF000000
 371
 372 #define SDRAM_BASE                      0x00000000
 373 #define SDRAM_SIZE                      (64 * 1024 * 1024)
 374
 375 #define FLASH_BASE                      0x40000000
 376 #define FLASH_SIZE                      (16 * 1024 * 1024)
 377
 378 #define DOC_BASE                        0x50000000
 379 #define DOC_SIZE                        (32 * 1024)
 380
 381 #define FPGA_BASE                       0x60000000
 382 #define FPGA_SIZE                       (64 * 1024 * 1024)
 383
 384 #define SELECTMAP_BASE          0x70000000
 385 #define SELECTMAP_SIZE          (32 * 1024)
 386
 387 #define M1553_BASE                      0x80000000
 388 #define M1553_SIZE                      (64 * 1024)
 389
 390 /*
 391  * Definitions for initial stack pointer and data area (in DPRAM)
 392  */
 393 #define CFG_INIT_RAM_ADDR               CFG_IMMR
 394 #define CFG_INIT_RAM_END                0x2F00  /* End of used area in DPRAM            */
 395 #define CFG_INIT_DATA_SIZE              64      /* # bytes reserved for initial data*/
 396 #define CFG_GBL_DATA_OFFSET             (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
 397 #define CFG_INIT_SP_OFFSET              CFG_GBL_DATA_OFFSET
 398
 399 /*
 400  * Start addresses for the final memory configuration
 401  * (Set up by the startup code)
 402  * Please note that CFG_SDRAM_BASE _must_ start at 0
 403  */
 404 #define CFG_SDRAM_BASE                  SDRAM_BASE
 405
 406 /*
 407  * FLASH organization
 408  */
 409 #define CFG_FLASH_BASE                  FLASH_BASE
 410 #define CFG_FLASH_SIZE                  FLASH_SIZE
 411 #define CFG_FLASH_SECT_SIZE             (128 * 1024)
 412 #define CFG_MAX_FLASH_BANKS             1
 413 #define CFG_MAX_FLASH_SECT              128
 414
 415 /*
 416  * The timeout values are for an entire chip and are in milliseconds.
 417  * Yes I know that the write timeout is huge.  Accroding to the
 418  * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
 419  * case VCC and temp after 100K programming cycles.  It works out
 420  * to 280 minutes (might as well be forever).
 421  */
 422 #define CFG_FLASH_ERASE_TOUT    (CFG_MAX_FLASH_SECT * 5000)
 423 #define CFG_FLASH_WRITE_TOUT    (CFG_MAX_FLASH_SECT * 128 * 1024 * 1)
 424
 425 /*
 426  * Allow direct writes to FLASH from tftp transfers (** dangerous **)
 427  */
 428 #define CFG_DIRECT_FLASH_TFTP
 429
 430 /*
 431  * Reserve memory for U-Boot.
 432  */
 433 #define CFG_MAX_UBOOT_SECTS             4
 434 #define CFG_MONITOR_LEN                 (CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)
 435 #define CFG_MONITOR_BASE                CFG_FLASH_BASE
 436
 437 /*
 438  * Select environment placement.  NOTE that u-boot.lds must
 439  * be edited if this is changed!
 440  */
 441 #undef  CFG_ENV_IS_IN_FLASH
 442 #define CFG_ENV_IS_IN_EEPROM
 443
 444 #if defined(CFG_ENV_IS_IN_EEPROM)
 445 #define CFG_ENV_SIZE                    (2 * 1024)
 446 #define CFG_ENV_OFFSET                  (CFG_ENV_EEPROM_SIZE - (8 * 1024))
 447 #else
 448 #define CFG_ENV_SIZE                    0x1000
 449 #define CFG_ENV_SECT_SIZE               CFG_FLASH_SECT_SIZE
 450
 451 /*
 452  * This ultimately gets passed right into the linker script, so we have to
 453  * use a number :(
 454  */
 455 #define CFG_ENV_OFFSET                  0x060000
 456 #endif
 457
 458 /*
 459  * Reserve memory for malloc()
 460  */
 461 #define CFG_MALLOC_LEN          (128 * 1024)
 462
 463 /*
 464  * For booting Linux, the board info and command line data
 465  * have to be in the first 8 MB of memory, since this is
 466  * the maximum mapped by the Linux kernel during initialization.
 467  */
 468 #define CFG_BOOTMAPSZ           (8 * 1024 * 1024)
 469
 470 /*
 471  * Cache Configuration
 472  */
 473 #define CFG_CACHELINE_SIZE              16      /* For all MPC8xx CPUs                          */
 474 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 475 #define CFG_CACHELINE_SHIFT             4       /* log base 2 of above value            */
 476 #endif
 477
 478 /*------------------------------------------------------------------------
 479  * SYPCR - System Protection Control                                                    UM 11-9
 480  * -----------------------------------------------------------------------
 481  * SYPCR can only be written once after reset!
 482  *
 483  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 484  */
 485 #if defined(CONFIG_WATCHDOG)
 486 #define CFG_SYPCR       ( SYPCR_SWTC    | \
 487                                           SYPCR_BMT     | \
 488                                           SYPCR_BME     | \
 489                                           SYPCR_SWF     | \
 490                                           SYPCR_SWE     | \
 491                                           SYPCR_SWRI    | \
 492                                           SYPCR_SWP               \
 493                                         )
 494 #else
 495 #define CFG_SYPCR       ( SYPCR_SWTC    | \
 496                                           SYPCR_BMT     | \
 497                                           SYPCR_BME     | \
 498                                           SYPCR_SWF     | \
 499                                           SYPCR_SWP               \
 500                                         )
 501 #endif
 502
 503 /*-----------------------------------------------------------------------
 504  * SIUMCR - SIU Module Configuration                                                    UM 11-6
 505  *-----------------------------------------------------------------------
 506  * Set debug pin mux, enable SPKROUT and GPLB5*.
 507  */
 508 #define CFG_SIUMCR      ( SIUMCR_DBGC11 | \
 509                                           SIUMCR_DBPC11 | \
 510                                           SIUMCR_MLRC11 | \
 511                                           SIUMCR_GB5E     \
 512                                         )
 513
 514 /*-----------------------------------------------------------------------
 515  * TBSCR - Time Base Status and Control                                                 UM 11-26
 516  *-----------------------------------------------------------------------
 517  * Clear Reference Interrupt Status, Timebase freeze enabled
 518  */
 519 #define CFG_TBSCR       ( TBSCR_REFA | \
 520                                           TBSCR_REFB | \
 521                                           TBSCR_TBF        \
 522                                         )
 523
 524 /*-----------------------------------------------------------------------
 525  * RTCSC - Real-Time Clock Status and Control Register                  UM 11-27
 526  *-----------------------------------------------------------------------
 527  */
 528 #define CFG_RTCSC       ( RTCSC_SEC     | \
 529                                           RTCSC_ALR | \
 530                                           RTCSC_RTF | \
 531                                           RTCSC_RTE       \
 532                                         )
 533
 534 /*-----------------------------------------------------------------------
 535  * PISCR - Periodic Interrupt Status and Control                                UM 11-31
 536  *-----------------------------------------------------------------------
 537  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 538  */
 539 #define CFG_PISCR       ( PISCR_PS              | \
 540                                           PISCR_PITF      \
 541                                         )
 542
 543 /*-----------------------------------------------------------------------
 544  * PLPRCR - PLL, Low-Power, and Reset Control Register                  UM 15-30
 545  *-----------------------------------------------------------------------
 546  * Reset PLL lock status sticky bit, timer expired status bit and timer
 547  * interrupt status bit. Set MF for 1:2:1 mode.
 548  */
 549 #define CFG_PLPRCR      ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)    | \
 550                                           PLPRCR_SPLSS  | \
 551                                           PLPRCR_TEXPS  | \
 552                                           PLPRCR_TMIST    \
 553                                         )
 554
 555 /*-----------------------------------------------------------------------
 556  * SCCR - System Clock and reset Control Register                               UM 15-27
 557  *-----------------------------------------------------------------------
 558  * Set clock output, timebase and RTC source and divider,
 559  * power management and some other internal clocks
 560  */
 561 #define SCCR_MASK   SCCR_EBDF11
 562
 563 #if !defined(CONFIG_SC)
 564 #define CFG_SCCR        ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 565                                           SCCR_COM00            |       /* full strength CLKOUT */ \
 566                                           SCCR_DFSYNC00         |       /* SYNCLK / 1 (normal)  */ \
 567                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 568                                           SCCR_DFNL000          | \
 569                                           SCCR_DFNH000            \
 570                                         )
 571 #else
 572 #define CFG_SCCR        ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
 573                                           SCCR_COM00            |       /* full strength CLKOUT */ \
 574                                           SCCR_DFSYNC00         |       /* SYNCLK / 1 (normal)  */ \
 575                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
 576                                           SCCR_DFNL000          | \
 577                                           SCCR_DFNH000          | \
 578                                           SCCR_RTDIV            | \
 579                                           SCCR_RTSEL              \
 580                                         )
 581 #endif
 582
 583 /*-----------------------------------------------------------------------
 584  * DER - Debug Enable Register                                                                  UM 37-46
 585  *-----------------------------------------------------------------------
 586  * Mask all events that can cause entry into debug mode
 587  */
 588 #define CFG_DER                         0
 589
 590 /*
 591  * Initialize Memory Controller:
 592  *
 593  * BR0 and OR0 (FLASH memory)
 594  */
 595 #define FLASH_BASE0_PRELIM      FLASH_BASE
 596
 597 /*
 598  * Flash address mask
 599  */
 600 #define CFG_PRELIM_OR_AM        0xfe000000
 601
 602 /*
 603  * FLASH timing:
 604  * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
 605  */
 606 #define CFG_OR_TIMING_FLASH     ( OR_CSNT_SAM   | \
 607                                                           OR_ACS_DIV2   | \
 608                                                           OR_BI                 | \
 609                                                           OR_SCY_2_CLK  | \
 610                                                           OR_TRLX               | \
 611                                                           OR_EHTR                 \
 612                                                         )
 613
 614 #define CFG_OR0_PRELIM  ( CFG_PRELIM_OR_AM              | \
 615                                                   CFG_OR_TIMING_FLASH     \
 616                                                 )
 617
 618 #define CFG_BR0_PRELIM  ( (FLASH_BASE0_PRELIM & BR_BA_MSK)      | \
 619                                                   BR_MS_GPCM                                            | \
 620                                                   BR_PS_8                                                       | \
 621                                                   BR_V                                                            \
 622                                                 )
 623
 624 /*
 625  * SDRAM configuration
 626  */
 627 #define CFG_OR1_AM      0xfc000000
 628 #define CFG_OR1         ( (CFG_OR1_AM & OR_AM_MSK)      | \
 629                                           OR_CSNT_SAM                             \
 630                                         )
 631
 632 #define CFG_BR1         ( (SDRAM_BASE & BR_BA_MSK)      | \
 633                                           BR_MS_UPMA                            | \
 634                                           BR_PS_32                                      | \
 635                                           BR_V                                            \
 636                                         )
 637
 638 /*
 639  * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
 640  * of 256 MBit SDRAM
 641  */
 642 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16
 643
 644 /*
 645  * Periodic timer for refresh @ 33 MHz system clock
 646  */
 647 #define CFG_MAMR_PTA    64
 648
 649 /*
 650  * MAMR settings for SDRAM
 651  */
 652 #define CFG_MAMR_8COL   ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT)      | \
 653                                                   MAMR_PTAE                             | \
 654                                                   MAMR_AMA_TYPE_1                       | \
 655                                                   MAMR_DSA_1_CYCL                       | \
 656                                                   MAMR_G0CLA_A10                        | \
 657                                                   MAMR_RLFA_1X                          | \
 658                                                   MAMR_WLFA_1X                          | \
 659                                                   MAMR_TLFA_4X                            \
 660                                                 )
 661
 662 /*
 663  * CS2* configuration for Disk On Chip:
 664  * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
 665  * no burst.
 666  */
 667 #define CFG_OR2_PRELIM  ( (0xffff0000 & OR_AM_MSK)      | \
 668                                                   OR_CSNT_SAM                           | \
 669                                                   OR_ACS_DIV2                           | \
 670                                                   OR_BI                                         | \
 671                                                   OR_SCY_2_CLK                          | \
 672                                                   OR_TRLX                                       | \
 673                                                   OR_EHTR                                         \
 674                                                 )
 675
 676 #define CFG_BR2_PRELIM  ( (DOC_BASE & BR_BA_MSK)        | \
 677                                                   BR_PS_8                                       | \
 678                                                   BR_MS_GPCM                            | \
 679                                                   BR_V                                            \
 680                                                 )
 681
 682 /*
 683  * CS3* configuration for FPGA:
 684  * 33 MHz bus with SCY=15, no burst.
 685  * The FPGA uses TA and TEA to terminate bus cycles, but we
 686  * clear SETA and set the cycle length to a large number so that
 687  * the cycle will still complete even if there is a configuration
 688  * error that prevents TA from asserting on FPGA accesss.
 689  */
 690 #define CFG_OR3_PRELIM  ( (0xfc000000 & OR_AM_MSK)  | \
 691                                                   OR_SCY_15_CLK                         | \
 692                                                   OR_BI                                           \
 693                                                 )
 694
 695 #define CFG_BR3_PRELIM  ( (FPGA_BASE & BR_BA_MSK)       | \
 696                                                   BR_PS_32                                      | \
 697                                                   BR_MS_GPCM                            | \
 698                                                   BR_V                                            \
 699                                                 )
 700 /*
 701  * CS4* configuration for FPGA SelectMap configuration interface.
 702  * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
 703  * of GCLK1_50
 704  */
 705 #define CFG_OR4_PRELIM  ( (0xffff0000 & OR_AM_MSK)      | \
 706                                                   OR_G5LS                                               | \
 707                                                   OR_BI                                                   \
 708                                                 )
 709
 710 #define CFG_BR4_PRELIM  ( (SELECTMAP_BASE & BR_BA_MSK)  | \
 711                                                   BR_PS_8                                               | \
 712                                                   BR_MS_UPMB                                    | \
 713                                                   BR_V                                                    \
 714                                                 )
 715
 716 /*
 717  * CS5* configuration for Mil-Std 1553 databus interface.
 718  * 33 MHz bus, GPCM, no burst.
 719  * The 1553 interface  uses TA and TEA to terminate bus cycles,
 720  * but we clear SETA and set the cycle length to a large number so that
 721  * the cycle will still complete even if there is a configuration
 722  * error that prevents TA from asserting on FPGA accesss.
 723  */
 724 #define CFG_OR5_PRELIM  ( (0xffff0000 & OR_AM_MSK)  | \
 725                                                   OR_SCY_15_CLK                         | \
 726                                                   OR_EHTR                                       | \
 727                                                   OR_TRLX                                       | \
 728                                                   OR_CSNT_SAM                           | \
 729                                                   OR_BI                                           \
 730                                                 )
 731
 732 #define CFG_BR5_PRELIM  ( (M1553_BASE & BR_BA_MSK)      | \
 733                                                   BR_PS_16                                      | \
 734                                                   BR_MS_GPCM                            | \
 735                                                   BR_V                                            \
 736                                                 )
 737
 738 /*
 739  * Boot Flags
 740  */
 741 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH     */
 742 #define BOOTFLAG_WARM   0x02    /* Software reboot                                      */
 743
 744 /*
 745  * Disk On Chip (millenium) configuration
 746  */
 747 #if !defined(CONFIG_SC)
 748 #define CFG_MAX_DOC_DEVICE      1
 749 #undef  CFG_DOC_SUPPORT_2000
 750 #define CFG_DOC_SUPPORT_MILLENNIUM
 751 #undef  CFG_DOC_PASSIVE_PROBE
 752 #endif
 753
 754 /*
 755  * FEC interrupt assignment
 756  */
 757 #define FEC_INTERRUPT   SIU_LEVEL1
 758
 759 /*
 760  * Sanity checks
 761  */
 762 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 763 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
 764 #endif
 765
 766 #endif  /* __CONFIG_GEN860T_H */
 767
 768 /* vim: set ts=4 tw=78 ai shiftwidth=4: */