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[people/ms/u-boot.git] / include / configs / GEN860T.h
1 /*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Keith Outwater, keith_outwater@mvis.com
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25 /*
26 * board/config_GEN860T.h - board specific configuration options
27 */
28
29 #ifndef __CONFIG_GEN860T_H
30 #define __CONFIG_H
31
32 /*
33 * High Level Configuration Options
34 */
35 #define CONFIG_MPC860
36 #define CONFIG_GEN860T
37
38 /*
39 * Identify the board
40 */
41 #if !defined(CONFIG_SC)
42 #define CONFIG_IDENT_STRING " B2"
43 #else
44 #define CONFIG_IDENT_STRING " SC"
45 #endif
46
47 /*
48 * Don't depend on the RTC clock to determine clock frequency -
49 * the 860's internal rtc uses a 32.768 KHz clock which is
50 * generated by the DS1337 - and the DS1337 clock can be turned off.
51 */
52 #if !defined(CONFIG_SC)
53 #define CONFIG_8xx_GCLK_FREQ 66600000
54 #else
55 #define CONFIG_8xx_GCLK_FREQ 48000000
56 #endif
57
58 /*
59 * The RS-232 console port is on SMC1
60 */
61 #define CONFIG_8xx_CONS_SMC1
62 #define CONFIG_BAUDRATE 38400
63
64 /*
65 * Set allowable console baud rates
66 */
67 #define CFG_BAUDRATE_TABLE { 9600, \
68 19200, \
69 38400, \
70 57600, \
71 115200, \
72 }
73
74 /*
75 * Print console information
76 */
77 #undef CFG_CONSOLE_INFO_QUIET
78
79 /*
80 * Set the autoboot delay in seconds. A delay of -1 disables autoboot
81 */
82 #define CONFIG_BOOTDELAY 5
83
84 /*
85 * Pass the clock frequency to the Linux kernel in units of MHz
86 */
87 #define CONFIG_CLOCKS_IN_MHZ
88
89 #define CONFIG_PREBOOT \
90 "echo;echo"
91
92 #undef CONFIG_BOOTARGS
93 #define CONFIG_BOOTCOMMAND \
94 "bootp;" \
95 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
96 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
97 "bootm"
98
99 /*
100 * Turn off echo for serial download by default. Allow baud rate to be changed
101 * for downloads
102 */
103 #undef CONFIG_LOADS_ECHO
104 #define CFG_LOADS_BAUD_CHANGE
105
106 /*
107 * Set default load address for tftp network downloads
108 */
109 #define CFG_TFTP_LOADADDR 0x01000000
110
111 /*
112 * Turn off the watchdog timer
113 */
114 #undef CONFIG_WATCHDOG
115
116 /*
117 * Do not reboot if a panic occurs
118 */
119 #define CONFIG_PANIC_HANG
120
121 /*
122 * Enable the status LED
123 */
124 #define CONFIG_STATUS_LED
125
126 /*
127 * Reset address. We pick an address such that when an instruction
128 * is executed at that address, a machine check exception occurs
129 */
130 #define CFG_RESET_ADDRESS ((ulong) -1)
131
132 /*
133 * BOOTP options
134 */
135 #define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
136 CONFIG_BOOTP_BOOTFILESIZE \
137 )
138
139 /*
140 * The GEN860T network interface uses the on-chip 10/100 FEC with
141 * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
142 * MII address is hardwired on the board to zero.
143 */
144 #define CONFIG_FEC_ENET
145 #define CFG_DISCOVER_PHY
146 #define CONFIG_MII
147 #define CONFIG_PHY_ADDR 0
148
149 /*
150 * Set default IP stuff just to get bootstrap entries into the
151 * environment so that we can autoscript the full default environment.
152 */
153 #define CONFIG_ETHADDR 9a:52:63:15:85:25
154 #define CONFIG_SERVERIP 10.0.4.201
155 #define CONFIG_IPADDR 10.0.4.111
156
157 /*
158 * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
159 * the MPC860T I2C interface.
160 */
161 #define CFG_I2C_EEPROM_ADDR 0x50
162 #define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
163 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */
164 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */
165 #define CFG_ENV_EEPROM_SIZE (32 * 1024)
166
167 /*
168 * Enable I2C and select the hardware/software driver
169 */
170 #define CONFIG_HARD_I2C 1 /* CPM based I2C */
171 #undef CONFIG_SOFT_I2C /* Bit-banged I2C */
172
173 #ifdef CONFIG_HARD_I2C
174 #define CFG_I2C_SPEED 100000 /* clock speed in Hz */
175 #define CFG_I2C_SLAVE 0xFE /* I2C slave address */
176 #endif
177
178 #ifdef CONFIG_SOFT_I2C
179 #define PB_SCL 0x00000020 /* PB 26 */
180 #define PB_SDA 0x00000010 /* PB 27 */
181 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
182 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
183 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
184 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
185 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
186 else immr->im_cpm.cp_pbdat &= ~PB_SDA
187 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
188 else immr->im_cpm.cp_pbdat &= ~PB_SCL
189 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
190 #endif
191
192 /*
193 * Allow environment overwrites by anyone
194 */
195 #define CONFIG_ENV_OVERWRITE
196
197 #if !defined(CONFIG_SC)
198 /*
199 * The MPC860's internal RTC is horribly broken in rev D masks. Three
200 * internal MPC860T circuit nodes were inadvertently left floating; this
201 * causes KAPWR current in power down mode to be three orders of magnitude
202 * higher than specified in the datasheet (from 10 uA to 10 mA). No
203 * reasonable battery can keep that kind RTC running during powerdown for any
204 * length of time, so we use an external RTC on the I2C bus instead.
205 */
206 #define CONFIG_RTC_DS1337
207 #define CFG_I2C_RTC_ADDR 0x68
208
209 #else
210 /*
211 * No external RTC on SC variant, so we're stuck with the internal one.
212 */
213 #define CONFIG_RTC_MPC8xx
214 #endif
215
216 /*
217 * Power On Self Test support
218 */
219 #define CONFIG_POST ( CFG_POST_CACHE | \
220 CFG_POST_MEMORY | \
221 CFG_POST_CPU | \
222 CFG_POST_UART | \
223 CFG_POST_SPR )
224
225 #ifdef CONFIG_POST
226 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
227 #else
228 #define CFG_CMD_POST_DIAG 0
229 #endif
230
231 /*
232 * List of available monitor commands. Use the system default list
233 * plus add some of the "non-standard" commands back in.
234 * See ./cmd_confdefs.h
235 */
236 #define BASE_CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
237 CFG_CMD_ASKENV | \
238 CFG_CMD_DHCP | \
239 CFG_CMD_I2C | \
240 CFG_CMD_EEPROM | \
241 CFG_CMD_REGINFO | \
242 CFG_CMD_IMMAP | \
243 CFG_CMD_ELF | \
244 CFG_CMD_DATE | \
245 CFG_CMD_FPGA | \
246 CFG_CMD_MII | \
247 CFG_CMD_BEDBUG | \
248 CFG_CMD_POST_DIAG )
249
250 #if !defined(CONFIG_SC)
251 #define CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC )
252 #else
253 #define CONFIG_COMMANDS BASE_CONFIG_COMMANDS
254 #endif
255
256 /*
257 * There is no IDE/PCMCIA hardware support on the board.
258 */
259 #undef CONFIG_IDE_PCMCIA
260 #undef CONFIG_IDE_LED
261 #undef CONFIG_IDE_RESET
262
263 /*
264 * Enable the call to misc_init_r() for miscellaneous platform
265 * dependent initialization.
266 */
267 #define CONFIG_MISC_INIT_R
268
269 /*
270 * Enable call to last_stage_init() so we can twiddle some LEDS :)
271 */
272 #define CONFIG_LAST_STAGE_INIT
273
274 /*
275 * Virtex2 FPGA configuration support
276 */
277 #define CONFIG_FPGA_COUNT 1
278 #define CONFIG_FPGA CFG_XILINX_VIRTEX2
279 #define CFG_FPGA_PROG_FEEDBACK
280
281
282 /************************************************************************
283 * This must be included AFTER the definition of any CONFIG_COMMANDS
284 */
285 #include <cmd_confdefs.h>
286
287 /*
288 * Verbose help from command monitor.
289 */
290 #define CFG_LONGHELP
291 #if !defined(CONFIG_SC)
292 #define CFG_PROMPT "B2> "
293 #else
294 #define CFG_PROMPT "SC> "
295 #endif
296
297
298 /*
299 * Use the "hush" command parser
300 */
301 #define CFG_HUSH_PARSER
302 #define CFG_PROMPT_HUSH_PS2 "> "
303
304 /*
305 * Set buffer size for console I/O
306 */
307 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
308 #define CFG_CBSIZE 1024
309 #else
310 #define CFG_CBSIZE 256
311 #endif
312
313 /*
314 * Print buffer size
315 */
316 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
317
318 /*
319 * Maximum number of arguments that a command can accept
320 */
321 #define CFG_MAXARGS 16
322
323 /*
324 * Boot argument buffer size
325 */
326 #define CFG_BARGSIZE CFG_CBSIZE
327
328 /*
329 * Default memory test range
330 */
331 #define CFG_MEMTEST_START 0x0100000
332 #define CFG_MEMTEST_END (CFG_MEMTEST_START + (128 * 1024))
333
334 /*
335 * Select the more full-featured memory test
336 */
337 #define CFG_ALT_MEMTEST
338
339 /*
340 * Default load address
341 */
342 #define CFG_LOAD_ADDR 0x01000000
343
344 /*
345 * Set decrementer frequency (1 ms ticks)
346 */
347 #define CFG_HZ 1000
348
349 /*
350 * Device memory map (after SDRAM remap to 0x0):
351 *
352 * CS Device Base Addr Size
353 * ----------------------------------------------------
354 * CS0* Flash 0x40000000 64 M
355 * CS1* SDRAM 0x00000000 16 M
356 * CS2* Disk-On-Chip 0x50000000 32 K
357 * CS3* FPGA 0x60000000 64 M
358 * CS4* SelectMap 0x70000000 32 K
359 * CS5* Mil-Std 1553 I/F 0x80000000 32 K
360 * CS6* Unused
361 * CS7* Unused
362 * IMMR 860T Registers 0xfff00000
363 */
364
365 /*
366 * Base addresses and block sizes
367 */
368 #define CFG_IMMR 0xFF000000
369
370 #define SDRAM_BASE 0x00000000
371 #define SDRAM_SIZE (64 * 1024 * 1024)
372
373 #define FLASH_BASE 0x40000000
374 #define FLASH_SIZE (16 * 1024 * 1024)
375
376 #define DOC_BASE 0x50000000
377 #define DOC_SIZE (32 * 1024)
378
379 #define FPGA_BASE 0x60000000
380 #define FPGA_SIZE (64 * 1024 * 1024)
381
382 #define SELECTMAP_BASE 0x70000000
383 #define SELECTMAP_SIZE (32 * 1024)
384
385 #define M1553_BASE 0x80000000
386 #define M1553_SIZE (64 * 1024)
387
388 /*
389 * Definitions for initial stack pointer and data area (in DPRAM)
390 */
391 #define CFG_INIT_RAM_ADDR CFG_IMMR
392 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
393 #define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
394 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
395 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
396
397 /*
398 * Start addresses for the final memory configuration
399 * (Set up by the startup code)
400 * Please note that CFG_SDRAM_BASE _must_ start at 0
401 */
402 #define CFG_SDRAM_BASE SDRAM_BASE
403
404 /*
405 * FLASH organization
406 */
407 #define CFG_FLASH_BASE FLASH_BASE
408 #define CFG_FLASH_SIZE FLASH_SIZE
409 #define CFG_FLASH_SECT_SIZE (128 * 1024)
410 #define CFG_MAX_FLASH_BANKS 1
411 #define CFG_MAX_FLASH_SECT 128
412
413 /*
414 * The timeout values are for an entire chip and are in milliseconds.
415 * Yes I know that the write timeout is huge. Accroding to the
416 * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
417 * case VCC and temp after 100K programming cycles. It works out
418 * to 280 minutes (might as well be forever).
419 */
420 #define CFG_FLASH_ERASE_TOUT (CFG_MAX_FLASH_SECT * 5000)
421 #define CFG_FLASH_WRITE_TOUT (CFG_MAX_FLASH_SECT * 128 * 1024 * 1)
422
423 /*
424 * Allow direct writes to FLASH from tftp transfers (** dangerous **)
425 */
426 #define CFG_DIRECT_FLASH_TFTP
427
428 /*
429 * Reserve memory for U-Boot.
430 */
431 #define CFG_MAX_UBOOT_SECTS 4
432 #define CFG_MONITOR_LEN (CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)
433 #define CFG_MONITOR_BASE CFG_FLASH_BASE
434
435 /*
436 * Select environment placement. NOTE that u-boot.lds must
437 * be edited if this is changed!
438 */
439 #undef CFG_ENV_IS_IN_FLASH
440 #define CFG_ENV_IS_IN_EEPROM
441
442 #if defined(CFG_ENV_IS_IN_EEPROM)
443 #define CFG_ENV_SIZE (2 * 1024)
444 #define CFG_ENV_OFFSET (CFG_ENV_EEPROM_SIZE - (8 * 1024))
445 #else
446 #define CFG_ENV_SIZE 0x1000
447 #define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SIZE
448
449 /*
450 * This ultimately gets passed right into the linker script, so we have to
451 * use a number :(
452 */
453 #define CFG_ENV_OFFSET 0x060000
454 #endif
455
456 /*
457 * Reserve memory for malloc()
458 */
459 #define CFG_MALLOC_LEN (128 * 1024)
460
461 /*
462 * For booting Linux, the board info and command line data
463 * have to be in the first 8 MB of memory, since this is
464 * the maximum mapped by the Linux kernel during initialization.
465 */
466 #define CFG_BOOTMAPSZ (8 * 1024 * 1024)
467
468 /*
469 * Cache Configuration
470 */
471 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
472 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
473 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */
474 #endif
475
476 /*------------------------------------------------------------------------
477 * SYPCR - System Protection Control UM 11-9
478 * -----------------------------------------------------------------------
479 * SYPCR can only be written once after reset!
480 *
481 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
482 */
483 #if defined(CONFIG_WATCHDOG)
484 #define CFG_SYPCR ( SYPCR_SWTC | \
485 SYPCR_BMT | \
486 SYPCR_BME | \
487 SYPCR_SWF | \
488 SYPCR_SWE | \
489 SYPCR_SWRI | \
490 SYPCR_SWP \
491 )
492 #else
493 #define CFG_SYPCR ( SYPCR_SWTC | \
494 SYPCR_BMT | \
495 SYPCR_BME | \
496 SYPCR_SWF | \
497 SYPCR_SWP \
498 )
499 #endif
500
501 /*-----------------------------------------------------------------------
502 * SIUMCR - SIU Module Configuration UM 11-6
503 *-----------------------------------------------------------------------
504 * Set debug pin mux, enable SPKROUT and GPLB5*.
505 */
506 #define CFG_SIUMCR ( SIUMCR_DBGC11 | \
507 SIUMCR_DBPC11 | \
508 SIUMCR_MLRC11 | \
509 SIUMCR_GB5E \
510 )
511
512 /*-----------------------------------------------------------------------
513 * TBSCR - Time Base Status and Control UM 11-26
514 *-----------------------------------------------------------------------
515 * Clear Reference Interrupt Status, Timebase freeze enabled
516 */
517 #define CFG_TBSCR ( TBSCR_REFA | \
518 TBSCR_REFB | \
519 TBSCR_TBF \
520 )
521
522 /*-----------------------------------------------------------------------
523 * RTCSC - Real-Time Clock Status and Control Register UM 11-27
524 *-----------------------------------------------------------------------
525 */
526 #define CFG_RTCSC ( RTCSC_SEC | \
527 RTCSC_ALR | \
528 RTCSC_RTF | \
529 RTCSC_RTE \
530 )
531
532 /*-----------------------------------------------------------------------
533 * PISCR - Periodic Interrupt Status and Control UM 11-31
534 *-----------------------------------------------------------------------
535 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
536 */
537 #define CFG_PISCR ( PISCR_PS | \
538 PISCR_PITF \
539 )
540
541 /*-----------------------------------------------------------------------
542 * PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30
543 *-----------------------------------------------------------------------
544 * Reset PLL lock status sticky bit, timer expired status bit and timer
545 * interrupt status bit. Set MF for 1:2:1 mode.
546 */
547 #define CFG_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \
548 PLPRCR_SPLSS | \
549 PLPRCR_TEXPS | \
550 PLPRCR_TMIST \
551 )
552
553 /*-----------------------------------------------------------------------
554 * SCCR - System Clock and reset Control Register UM 15-27
555 *-----------------------------------------------------------------------
556 * Set clock output, timebase and RTC source and divider,
557 * power management and some other internal clocks
558 */
559 #define SCCR_MASK SCCR_EBDF11
560
561 #if !defined(CONFIG_SC)
562 #define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
563 SCCR_COM00 | /* full strength CLKOUT */ \
564 SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
565 SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
566 SCCR_DFNL000 | \
567 SCCR_DFNH000 \
568 )
569 #else
570 #define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
571 SCCR_COM00 | /* full strength CLKOUT */ \
572 SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
573 SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
574 SCCR_DFNL000 | \
575 SCCR_DFNH000 | \
576 SCCR_RTDIV | \
577 SCCR_RTSEL \
578 )
579 #endif
580
581 /*-----------------------------------------------------------------------
582 * DER - Debug Enable Register UM 37-46
583 *-----------------------------------------------------------------------
584 * Mask all events that can cause entry into debug mode
585 */
586 #define CFG_DER 0
587
588 /*
589 * Initialize Memory Controller:
590 *
591 * BR0 and OR0 (FLASH memory)
592 */
593 #define FLASH_BASE0_PRELIM FLASH_BASE
594
595 /*
596 * Flash address mask
597 */
598 #define CFG_PRELIM_OR_AM 0xfe000000
599
600 /*
601 * FLASH timing:
602 * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
603 */
604 #define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | \
605 OR_ACS_DIV2 | \
606 OR_BI | \
607 OR_SCY_2_CLK | \
608 OR_TRLX | \
609 OR_EHTR \
610 )
611
612 #define CFG_OR0_PRELIM ( CFG_PRELIM_OR_AM | \
613 CFG_OR_TIMING_FLASH \
614 )
615
616 #define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \
617 BR_MS_GPCM | \
618 BR_PS_8 | \
619 BR_V \
620 )
621
622 /*
623 * SDRAM configuration
624 */
625 #define CFG_OR1_AM 0xfc000000
626 #define CFG_OR1 ( (CFG_OR1_AM & OR_AM_MSK) | \
627 OR_CSNT_SAM \
628 )
629
630 #define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \
631 BR_MS_UPMA | \
632 BR_PS_32 | \
633 BR_V \
634 )
635
636 /*
637 * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
638 * of 256 MBit SDRAM
639 */
640 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16
641
642 /*
643 * Periodic timer for refresh @ 33 MHz system clock
644 */
645 #define CFG_MAMR_PTA 64
646
647 /*
648 * MAMR settings for SDRAM
649 */
650 #define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
651 MAMR_PTAE | \
652 MAMR_AMA_TYPE_1 | \
653 MAMR_DSA_1_CYCL | \
654 MAMR_G0CLA_A10 | \
655 MAMR_RLFA_1X | \
656 MAMR_WLFA_1X | \
657 MAMR_TLFA_4X \
658 )
659
660 /*
661 * CS2* configuration for Disk On Chip:
662 * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
663 * no burst.
664 */
665 #define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
666 OR_CSNT_SAM | \
667 OR_ACS_DIV2 | \
668 OR_BI | \
669 OR_SCY_2_CLK | \
670 OR_TRLX | \
671 OR_EHTR \
672 )
673
674 #define CFG_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \
675 BR_PS_8 | \
676 BR_MS_GPCM | \
677 BR_V \
678 )
679
680 /*
681 * CS3* configuration for FPGA:
682 * 33 MHz bus with SCY=15, no burst.
683 * The FPGA uses TA and TEA to terminate bus cycles, but we
684 * clear SETA and set the cycle length to a large number so that
685 * the cycle will still complete even if there is a configuration
686 * error that prevents TA from asserting on FPGA accesss.
687 */
688 #define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \
689 OR_SCY_15_CLK | \
690 OR_BI \
691 )
692
693 #define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \
694 BR_PS_32 | \
695 BR_MS_GPCM | \
696 BR_V \
697 )
698 /*
699 * CS4* configuration for FPGA SelectMap configuration interface.
700 * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
701 * of GCLK1_50
702 */
703 #define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
704 OR_G5LS | \
705 OR_BI \
706 )
707
708 #define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \
709 BR_PS_8 | \
710 BR_MS_UPMB | \
711 BR_V \
712 )
713
714 /*
715 * CS5* configuration for Mil-Std 1553 databus interface.
716 * 33 MHz bus, GPCM, no burst.
717 * The 1553 interface uses TA and TEA to terminate bus cycles,
718 * but we clear SETA and set the cycle length to a large number so that
719 * the cycle will still complete even if there is a configuration
720 * error that prevents TA from asserting on FPGA accesss.
721 */
722 #define CFG_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
723 OR_SCY_15_CLK | \
724 OR_EHTR | \
725 OR_TRLX | \
726 OR_CSNT_SAM | \
727 OR_BI \
728 )
729
730 #define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \
731 BR_PS_16 | \
732 BR_MS_GPCM | \
733 BR_V \
734 )
735
736 /*
737 * Boot Flags
738 */
739 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
740 #define BOOTFLAG_WARM 0x02 /* Software reboot */
741
742 /*
743 * Disk On Chip (millenium) configuration
744 */
745 #if !defined(CONFIG_SC)
746 #define CFG_MAX_DOC_DEVICE 1
747 #undef CFG_DOC_SUPPORT_2000
748 #define CFG_DOC_SUPPORT_MILLENNIUM
749 #undef CFG_DOC_PASSIVE_PROBE
750 #endif
751
752 /*
753 * FEC interrupt assignment
754 */
755 #define FEC_INTERRUPT SIU_LEVEL1
756
757 /*
758 * Sanity checks
759 */
760 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
761 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
762 #endif
763
764 #endif /* __CONFIG_GEN860T_H */
765
766 /* vim: set ts=4 tw=78 ai shiftwidth=4: */
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