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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/ISPAN.h
2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
5 * Support for Interphase iSPAN Communications Controllers
6 * (453x and others). Tested on 4532.
8 * Derived from iSPAN 4539 port (iphase4539) by
9 * Wolfgang Grandegger <wg@denx.de>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #define CONFIG_MPC8260 /* This is an MPC8260 CPU */
33 #define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
34 #define CONFIG_CPM2 1 /* Has a CPM2 */
36 /*-----------------------------------------------------------------------
37 * Select serial console configuration
39 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
40 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
43 * If CONFIG_CONS_NONE is defined, then the serial console routines must be
44 * defined elsewhere (for example, on the cogent platform, there are serial
45 * ports on the motherboard which are used for the serial console - see
46 * cogent/cma101/serial.[ch]).
48 #define CONFIG_CONS_ON_SMC /* Define if console on SMC */
49 #undef CONFIG_CONS_ON_SCC /* Define if console on SCC */
50 #undef CONFIG_CONS_NONE /* Define if console on something else */
51 #define CONFIG_CONS_INDEX 1 /* Which serial channel for console */
53 /*-----------------------------------------------------------------------
54 * Select Ethernet configuration
56 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
57 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
60 * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
61 * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
63 #undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */
64 #define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */
65 #undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */
66 #define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */
68 #ifdef CONFIG_ETHER_ON_FCC
70 #if CONFIG_ETHER_INDEX == 3
72 #define CONFIG_SYS_PHY_ADDR 0
73 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
74 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
76 #endif /* CONFIG_ETHER_INDEX == 3 */
78 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
79 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
81 #define CONFIG_MII /* MII PHY management */
82 #define CONFIG_BITBANGMII /* Bit-bang MII PHY management */
84 * GPIO pins used for bit-banged MII communications
86 #define MDIO_PORT 3 /* Port D */
88 #define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */
89 #define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */
91 #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
92 #define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
93 #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
95 #define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
96 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
98 #define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
99 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
101 #define MIIDELAY udelay(1)
103 #endif /* CONFIG_ETHER_ON_FCC */
105 #define CONFIG_8260_CLKIN 65536000 /* in Hz */
106 #define CONFIG_BAUDRATE 38400
112 #define CONFIG_BOOTP_BOOTFILESIZE
113 #define CONFIG_BOOTP_BOOTPATH
114 #define CONFIG_BOOTP_GATEWAY
115 #define CONFIG_BOOTP_HOSTNAME
119 * Command line configuration.
121 #include <config_cmd_default.h>
123 #define CONFIG_CMD_ASKENV
124 #define CONFIG_CMD_DHCP
125 #define CONFIG_CMD_IMMAP
126 #define CONFIG_CMD_MII
127 #define CONFIG_CMD_PING
128 #define CONFIG_CMD_REGINFO
131 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
132 #define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */
133 #define CONFIG_BOOTARGS "root=/dev/ram rw"
135 #define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
136 #undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
138 /*-----------------------------------------------------------------------
139 * Miscellaneous configurable options
141 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
142 #define CONFIG_SYS_HUSH_PARSER
143 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
144 #define CONFIG_SYS_LONGHELP /* #undef to save memory */
145 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
146 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
147 #define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
148 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
150 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
151 #define CONFIG_SYS_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */
153 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* Default load address */
155 #define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */
157 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
159 #define CONFIG_SYS_RESET_ADDRESS 0x09900000
161 #define CONFIG_MISC_INIT_R /* We need misc_init_r() */
163 /*-----------------------------------------------------------------------
164 * For booting Linux, the board info and command line data
165 * have to be in the first 8 MB of memory, since this is
166 * the maximum mapped by the Linux kernel during initialization.
168 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
170 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
171 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
173 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
175 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
176 #endif /* CONFIG_BZIP2 */
178 /*-----------------------------------------------------------------------
181 #define CONFIG_SYS_FLASH_BASE 0xFE000000
182 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
183 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
184 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max num of memory banks */
185 #define CONFIG_SYS_MAX_FLASH_SECT 142 /* Max num of sects on one chip */
187 /* Environment is in flash, there is little space left in Serial EEPROM */
188 #define CONFIG_ENV_IS_IN_FLASH
189 #define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
190 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
191 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
192 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
193 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
195 /*-----------------------------------------------------------------------
196 * Hard Reset Configuration Words
198 * If you change bits in the HRCW, you must also change the CONFIG_SYS_*
199 * defines for the various registers affected by the HRCW e.g. changing
200 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
203 #define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\
204 HRCW_L2CPC10 | HRCW_ISB110 |\
205 HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\
206 HRCW_CS10PC01 | HRCW_MODCK_H0101 \
209 #define CONFIG_SYS_HRCW_SLAVE1 0
210 #define CONFIG_SYS_HRCW_SLAVE2 0
211 #define CONFIG_SYS_HRCW_SLAVE3 0
212 #define CONFIG_SYS_HRCW_SLAVE4 0
213 #define CONFIG_SYS_HRCW_SLAVE5 0
214 #define CONFIG_SYS_HRCW_SLAVE6 0
215 #define CONFIG_SYS_HRCW_SLAVE7 0
217 /*-----------------------------------------------------------------------
218 * Internal Memory Mapped Register
220 #define CONFIG_SYS_IMMR 0xF0F00000
221 #ifdef CONFIG_SYS_REV_B
222 #define CONFIG_SYS_DEFAULT_IMMR 0xFF000000
223 #endif /* CONFIG_SYS_REV_B */
224 /*-----------------------------------------------------------------------
225 * Definitions for initial stack pointer and data area (in DPRAM)
227 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
228 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
229 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
230 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
231 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
233 /*-----------------------------------------------------------------------
234 * Internal Definitions
238 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
239 #define BOOTFLAG_WARM 0x02 /* Software reboot */
241 /*-----------------------------------------------------------------------
242 * Cache Configuration
244 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
246 /*-----------------------------------------------------------------------
247 * HIDx - Hardware Implementation-dependent Registers 2-11
248 *-----------------------------------------------------------------------
249 * HID0 also contains cache control.
251 * HID1 has only read-only information - nothing to set.
253 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
255 #define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
256 #define CONFIG_SYS_HID2 0
258 /*-----------------------------------------------------------------------
259 * RMR - Reset Mode Register 5-5
260 *-----------------------------------------------------------------------
261 * turn on Checkstop Reset Enable
263 #define CONFIG_SYS_RMR RMR_CSRE
265 /*-----------------------------------------------------------------------
266 * BCR - Bus Configuration 4-25
267 *-----------------------------------------------------------------------
269 #define CONFIG_SYS_BCR 0xA01C0000
271 /*-----------------------------------------------------------------------
272 * SIUMCR - SIU Module Configuration 4-31
273 *-----------------------------------------------------------------------
275 #define CONFIG_SYS_SIUMCR 0x42250000/* 0x4205C000 */
277 /*-----------------------------------------------------------------------
278 * SYPCR - System Protection Control 4-35
279 * SYPCR can only be written once after reset!
280 *-----------------------------------------------------------------------
281 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
283 #if defined (CONFIG_WATCHDOG)
284 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
285 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
287 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
288 SYPCR_SWRI|SYPCR_SWP)
289 #endif /* CONFIG_WATCHDOG */
291 /*-----------------------------------------------------------------------
292 * TMCNTSC - Time Counter Status and Control 4-40
293 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
294 * and enable Time Counter
295 *-----------------------------------------------------------------------
297 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
299 /*-----------------------------------------------------------------------
300 * PISCR - Periodic Interrupt Status and Control 4-42
301 *-----------------------------------------------------------------------
302 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
305 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
307 /*-----------------------------------------------------------------------
308 * SCCR - System Clock Control 9-8
309 *-----------------------------------------------------------------------
310 * Ensure DFBRG is Divide by 16
312 #define CONFIG_SYS_SCCR SCCR_DFBRG01
314 /*-----------------------------------------------------------------------
315 * RCCR - RISC Controller Configuration 13-7
316 *-----------------------------------------------------------------------
318 #define CONFIG_SYS_RCCR 0
320 /*-----------------------------------------------------------------------
321 * Init Memory Controller:
323 * Bank Bus Machine PortSize Device
324 * ---- --- ------- ----------------------------- ------
325 * 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash
326 * 1 60x SDRAM 64 bit SDRAM
327 * 2 Local SDRAM 32 bit SDRAM
329 #define CONFIG_SYS_USE_FIRMWARE /* If defined - do not initialise memory
330 controller, rely on initialisation
331 performed by the Interphase boot firmware.
334 #define CONFIG_SYS_OR0_PRELIM 0xFE000882
335 #ifdef CONFIG_SYS_REV_B
336 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_8 | BRx_V)
338 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V)
339 #endif /* CONFIG_SYS_REV_B */
341 #define CONFIG_SYS_MPTPR 0x7F00
343 /* Please note that 60x SDRAM MUST start at 0 */
344 #define CONFIG_SYS_SDRAM_BASE 0x00000000
345 #define CONFIG_SYS_60x_BR 0x00000041
346 #define CONFIG_SYS_60x_OR 0xF0002CD0
347 #define CONFIG_SYS_PSDMR 0x0049929A
348 #define CONFIG_SYS_PSRT 0x07
350 #define CONFIG_SYS_LSDRAM_BASE 0xF7000000
351 #define CONFIG_SYS_LOC_BR 0x00001861
352 #define CONFIG_SYS_LOC_OR 0xFF803280
353 #define CONFIG_SYS_LSDMR 0x8285A552
354 #define CONFIG_SYS_LSRT 0x07
356 #endif /* __CONFIG_H */