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Add support for multiple PHYs.
[people/ms/u-boot.git] / include / configs / IceCube.h
1 /*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 /*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_ICECUBE 1 /* ... on IceCube board */
34
35 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
36
37 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
38 #define BOOTFLAG_WARM 0x02 /* Software reboot */
39
40 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
41 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
42 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
43 #endif
44
45 /*
46 * Serial console configuration
47 */
48 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
50 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
51
52
53 #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
54 /*
55 * PCI Mapping:
56 * 0x40000000 - 0x4fffffff - PCI Memory
57 * 0x50000000 - 0x50ffffff - PCI IO Space
58 */
59 #define CONFIG_PCI 1
60 #define CONFIG_PCI_PNP 1
61 #define CONFIG_PCI_SCAN_SHOW 1
62
63 #define CONFIG_PCI_MEM_BUS 0x40000000
64 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
65 #define CONFIG_PCI_MEM_SIZE 0x10000000
66
67 #define CONFIG_PCI_IO_BUS 0x50000000
68 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
69 #define CONFIG_PCI_IO_SIZE 0x01000000
70
71 #define CFG_XLB_PIPELINING 1
72
73 #define CONFIG_NET_MULTI 1
74 #define CONFIG_MII 1
75 #define CONFIG_EEPRO100 1
76 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
77 #define CONFIG_NS8382X 1
78
79 #define ADD_PCI_CMD CFG_CMD_PCI
80
81 #else /* MPC5100 */
82
83 #define CONFIG_MII 1
84 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
85
86 #endif
87
88 /* Partitions */
89 #define CONFIG_MAC_PARTITION
90 #define CONFIG_DOS_PARTITION
91 #define CONFIG_ISO_PARTITION
92
93 /* USB */
94 #if 1
95 #define CONFIG_USB_OHCI
96 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
97 #define CONFIG_USB_STORAGE
98 #else
99 #define ADD_USB_CMD 0
100 #endif
101
102 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
103
104 /*
105 * Supported commands
106 */
107 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
108 CFG_CMD_EEPROM | \
109 CFG_CMD_FAT | \
110 CFG_CMD_I2C | \
111 CFG_CMD_IDE | \
112 CFG_CMD_NFS | \
113 CFG_CMD_SNTP | \
114 ADD_PCI_CMD | \
115 ADD_USB_CMD )
116
117 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
118 #include <cmd_confdefs.h>
119
120 #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
121 # define CFG_LOWBOOT 1
122 # define CFG_LOWBOOT16 1
123 #endif
124 #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
125 # define CFG_LOWBOOT 1
126 # define CFG_LOWBOOT08 1
127 #endif
128
129 /*
130 * Autobooting
131 */
132 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
133
134 #define CONFIG_PREBOOT "echo;" \
135 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
136 "echo"
137
138 #undef CONFIG_BOOTARGS
139
140 #define CONFIG_EXTRA_ENV_SETTINGS \
141 "netdev=eth0\0" \
142 "nfsargs=setenv bootargs root=/dev/nfs rw " \
143 "nfsroot=$(serverip):$(rootpath)\0" \
144 "ramargs=setenv bootargs root=/dev/ram rw\0" \
145 "addip=setenv bootargs $(bootargs) " \
146 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
147 ":$(hostname):$(netdev):off panic=1\0" \
148 "flash_nfs=run nfsargs addip;" \
149 "bootm $(kernel_addr)\0" \
150 "flash_self=run ramargs addip;" \
151 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
152 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
153 "rootpath=/opt/eldk/ppc_82xx\0" \
154 "bootfile=/tftpboot/MPC5200/uImage\0" \
155 ""
156
157 #define CONFIG_BOOTCOMMAND "run flash_self"
158
159 #if defined(CONFIG_MPC5200)
160 /*
161 * IPB Bus clocking configuration.
162 */
163 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
164 #endif
165 /*
166 * I2C configuration
167 */
168 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
169 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
170
171 #define CFG_I2C_SPEED 100000 /* 100 kHz */
172 #define CFG_I2C_SLAVE 0x7F
173
174 /*
175 * EEPROM configuration
176 */
177 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
178 #define CFG_I2C_EEPROM_ADDR_LEN 1
179 #define CFG_EEPROM_PAGE_WRITE_BITS 3
180 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
181
182 /*
183 * Flash configuration
184 */
185 #define CFG_FLASH_BASE 0xFF000000
186 #define CFG_FLASH_SIZE 0x01000000
187 #if !defined(CFG_LOWBOOT)
188 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000)
189 #else /* CFG_LOWBOOT */
190 #if defined(CFG_LOWBOOT08)
191 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000 + 0x00800000)
192 #endif
193 #if defined(CFG_LOWBOOT16)
194 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
195 #endif
196 #endif /* CFG_LOWBOOT */
197 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
198
199 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
200
201 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
202 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
203
204 #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
205
206
207 /*
208 * Environment settings
209 */
210 #define CFG_ENV_IS_IN_FLASH 1
211 #define CFG_ENV_SIZE 0x10000
212 #define CFG_ENV_SECT_SIZE 0x10000
213 #define CONFIG_ENV_OVERWRITE 1
214
215 /*
216 * Memory map
217 */
218 #define CFG_MBAR 0xF0000000
219 #define CFG_SDRAM_BASE 0x00000000
220 #define CFG_DEFAULT_MBAR 0x80000000
221
222 /* Use SRAM until RAM will be available */
223 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
224 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
225
226
227 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
228 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
229 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
230
231 #define CFG_MONITOR_BASE TEXT_BASE
232 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
233 # define CFG_RAMBOOT 1
234 #endif
235
236 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
237 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
238 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
239
240 /*
241 * Ethernet configuration
242 */
243 #define CONFIG_MPC5xxx_FEC 1
244 /*
245 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
246 */
247 /* #define CONFIG_FEC_10MBIT 1 */
248 #define CONFIG_PHY_ADDR 0x00
249
250 /*
251 * GPIO configuration
252 */
253 #ifdef CONFIG_MPC5200_DDR
254 #define CFG_GPS_PORT_CONFIG 0x90000004
255 #else
256 #define CFG_GPS_PORT_CONFIG 0x10000004
257 #endif
258
259 /*
260 * Miscellaneous configurable options
261 */
262 #define CFG_LONGHELP /* undef to save memory */
263 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
264 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
265 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
266 #else
267 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
268 #endif
269 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
270 #define CFG_MAXARGS 16 /* max number of command args */
271 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
272
273 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
274 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
275
276 #define CFG_LOAD_ADDR 0x100000 /* default load address */
277
278 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
279
280 /*
281 * Various low-level settings
282 */
283 #if defined(CONFIG_MPC5200)
284 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
285 #define CFG_HID0_FINAL HID0_ICE
286 #else
287 #define CFG_HID0_INIT 0
288 #define CFG_HID0_FINAL 0
289 #endif
290
291 #ifdef CONFIG_MPC5200_DDR
292
293 #define CFG_BOOTCS_START (CFG_CS1_START + CFG_CS1_SIZE)
294 #define CFG_BOOTCS_SIZE 0x00800000
295 #define CFG_BOOTCS_CFG 0x00047801
296 #define CFG_CS1_START CFG_FLASH_BASE
297 #define CFG_CS1_SIZE 0x00800000
298 #define CFG_CS1_CFG 0x00047800
299
300 #else /* !CONFIG_MPC5200_DDR */
301
302 #define CFG_BOOTCS_START CFG_FLASH_BASE
303 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
304 #define CFG_BOOTCS_CFG 0x00047801
305 #define CFG_CS0_START CFG_FLASH_BASE
306 #define CFG_CS0_SIZE CFG_FLASH_SIZE
307
308 #endif /* CONFIG_MPC5200_DDR */
309
310 #define CFG_CS_BURST 0x00000000
311 #define CFG_CS_DEADCYCLE 0x33333333
312
313 #define CFG_RESET_ADDRESS 0xff000000
314
315 /*-----------------------------------------------------------------------
316 * USB stuff
317 *-----------------------------------------------------------------------
318 */
319 #define CONFIG_USB_CLOCK 0x0001BBBB
320 #define CONFIG_USB_CONFIG 0x00001000
321
322 /*-----------------------------------------------------------------------
323 * IDE/ATA stuff Supports IDE harddisk
324 *-----------------------------------------------------------------------
325 */
326
327 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
328
329 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
330 #undef CONFIG_IDE_LED /* LED for ide not supported */
331
332 #define CONFIG_IDE_RESET /* reset for ide supported */
333 #define CONFIG_IDE_PREINIT
334
335 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
336 #define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
337
338 #define CFG_ATA_IDE0_OFFSET 0x0000
339
340 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
341
342 /* Offset for data I/O */
343 #define CFG_ATA_DATA_OFFSET (0x0060)
344
345 /* Offset for normal register accesses */
346 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
347
348 /* Offset for alternate registers */
349 #define CFG_ATA_ALT_OFFSET (0x005C)
350
351 /* Interval between registers */
352 #define CFG_ATA_STRIDE 4
353
354 #define CONFIG_ATAPI 1
355
356 #endif /* __CONFIG_H */