include/configs/JSE.h

   1 /*
   2  * (C) Copyright 2003 Picture Elements, Inc.
   3  * Stephen Williams <steve@icarus.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options for the JSE board
  17  * (Theoretically easy to change, but the board is fixed.)
  18  */
  19
  20 #define CONFIG_JSE 1
  21   /* JSE has a PPC405GPr */
  22 #define CONFIG_405GP 1
  23   /* ... which is a 4xxx series */
  24 #define CONFIG_4x   1
  25   /* ... with a 33MHz OSC. connected to the SysCLK input */
  26 #define CONFIG_SYS_CLK_FREQ     33333333
  27   /* ... with on-chip memory here (4KBytes) */
  28 #define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
  29 #define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
  30   /* Do not set up locked dcache as init ram. */
  31 #undef CONFIG_SYS_INIT_DCACHE_CS
  32
  33 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  34
  35   /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
  36 #define CONFIG_SYSTEMACE 1
  37 #define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
  38 #define CONFIG_SYS_SYSTEMACE_WIDTH 8
  39 #define CONFIG_DOS_PARTITION 1
  40
  41   /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
  42 #define CONFIG_SYS_TEMP_STACK_OCM 1
  43   /* ... place INIT RAM in the OCM address */
  44 # define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_OCM_DATA_ADDR
  45   /* ... give it the whole init ram */
  46 # define CONFIG_SYS_INIT_RAM_SIZE       CONFIG_SYS_OCM_DATA_SIZE
  47   /* ... Shave a bit off the end for global data */
  48 # define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  49   /* ... and place the stack pointer at the top of what's left. */
  50 # define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
  51
  52   /* Enable board_pre_init function */
  53 #define CONFIG_BOARD_PRE_INIT   1
  54 #define CONFIG_BOARD_EARLY_INIT_F 1
  55   /* Disable post-clk setup init function */
  56 #undef CONFIG_BOARD_POSTCLK_INIT
  57   /* Disable call to post_init_f: late init function. */
  58 #undef CONFIG_POST
  59   /* Enable DRAM test. */
  60 #define CONFIG_SYS_DRAM_TEST 1
  61   /* Enable misc_init_r function. */
  62 #define CONFIG_MISC_INIT_R 1
  63
  64   /* JSE has EEPROM chips that are good for environment. */
  65 #undef  CONFIG_ENV_IS_IN_NVRAM
  66 #undef  CONFIG_ENV_IS_IN_FLASH
  67 #define CONFIG_ENV_IS_IN_EEPROM 1
  68 #undef  CONFIG_ENV_IS_NOWHERE
  69
  70   /* This is the 7bit address of the device, not including P. */
  71 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  72   /* After the device address, need one more address byte. */
  73 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  74   /* The EEPROM is 512 bytes. */
  75 #define CONFIG_SYS_EEPROM_SIZE 512
  76   /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
  77 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
  78 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  79   /* Put the environment in the second half. */
  80 #define CONFIG_ENV_OFFSET       0x00
  81 #define CONFIG_ENV_SIZE 512
  82
  83   /* The JSE connects UART1 to the console tap connector. */
  84 #define CONFIG_CONS_INDEX       2
  85 #define CONFIG_SYS_NS16550
  86 #define CONFIG_SYS_NS16550_SERIAL
  87 #define CONFIG_SYS_NS16550_REG_SIZE     1
  88 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  89
  90   /* Set console baudrate to 9600 */
  91 #define CONFIG_BAUDRATE         9600
  92
  93 /*
  94  * Configuration related to auto-boot.
  95  *
  96  * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait
  97  * before resorting to autoboot. This value can be overridden by the
  98  * bootdelay environment variable.
  99  *
 100  * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the
 101  * user that an autoboot will happen.
 102  *
 103  * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will
 104  * execute to boot the JSE. This loads the uimage and initrd.img files
 105  * from CompactFlash into memory, then boots them from memory.
 106  *
 107  * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get
 108  * it going on the JSE.
 109  */
 110 #define CONFIG_BOOTDELAY        5
 111 #define CONFIG_BOOTARGS         "root=/dev/ram0 init=/linuxrc rw"
 112 #define CONFIG_BOOTCOMMAND      "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000"
 113
 114
 115 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 116 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 117
 118 #define CONFIG_PPC4xx_EMAC
 119 #define CONFIG_MII              1       /* MII PHY management           */
 120 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 121
 122
 123 /*
 124  * BOOTP options
 125  */
 126 #define CONFIG_BOOTP_BOOTFILESIZE
 127 #define CONFIG_BOOTP_BOOTPATH
 128 #define CONFIG_BOOTP_GATEWAY
 129 #define CONFIG_BOOTP_HOSTNAME
 130
 131
 132 /*
 133  * Command line configuration.
 134  */
 135 #include <config_cmd_default.h>
 136
 137 #define CONFIG_CMD_DHCP
 138 #define CONFIG_CMD_EEPROM
 139 #define CONFIG_CMD_ELF
 140 #define CONFIG_CMD_FAT
 141 #define CONFIG_CMD_FLASH
 142 #define CONFIG_CMD_IRQ
 143 #define CONFIG_CMD_MII
 144 #define CONFIG_CMD_NET
 145 #define CONFIG_CMD_PCI
 146 #define CONFIG_CMD_PING
 147
 148
 149   /* watchdog disabled */
 150 #undef CONFIG_WATCHDOG
 151   /* SPD EEPROM (sdram speed config) disabled */
 152 #undef CONFIG_SPD_EEPROM
 153 #undef SPD_EEPROM_ADDRESS
 154
 155 /*
 156  * Miscellaneous configurable options
 157  */
 158 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 159 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 160
 161 #define CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
 162
 163 #if defined(CONFIG_CMD_KGDB)
 164 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 165 #else
 166 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 167 #endif
 168 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 169 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 170 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 171
 172 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 173 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 174
 175 /*
 176  * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 177  * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
 178  * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
 179  * The Linux BASE_BAUD define should match this configuration.
 180  *    baseBaud = cpuClock/(uartDivisor*16)
 181  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 182  * set Linux BASE_BAUD to 403200.
 183  */
 184 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* external serial clock */
 185 #undef  CONFIG_SYS_405_UART_ERRATA_59          /* 405GP/CR Rev. D silicon */
 186 #define CONFIG_SYS_BASE_BAUD        691200
 187
 188 /* The following table includes the supported baudrates */
 189 #define CONFIG_SYS_BAUDRATE_TABLE  \
 190     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 191
 192 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 193 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 194
 195 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 196
 197 #define CONFIG_SYS_I2C
 198 #define CONFIG_SYS_I2C_PPC4XX
 199 #define CONFIG_SYS_I2C_PPC4XX_CH0
 200 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 201 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 202
 203
 204 /*-----------------------------------------------------------------------
 205  * PCI stuff
 206  *-----------------------------------------------------------------------
 207  */
 208 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 209 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 210 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 211
 212 #define CONFIG_PCI                      /* include pci support          */
 213 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 214 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 215 #undef  CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 216                                         /* resource configuration       */
 217
 218 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000   /* PCI Vendor ID: to-do!!!      */
 219 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: to-do!!!      */
 220 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 221 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 222 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 223 #define CONFIG_SYS_PCI_PTM2LA   0x00000000      /* disabled                     */
 224 #define CONFIG_SYS_PCI_PTM2MS   0x00000000      /* disabled                     */
 225 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000       /* Host: use this pci address   */
 226
 227 /*-----------------------------------------------------------------------
 228  * External peripheral base address
 229  *-----------------------------------------------------------------------
 230  */
 231 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 232 #undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 233
 234 #define CONFIG_SYS_KEY_REG_BASE_ADDR    0xF0100000
 235 #define CONFIG_SYS_IR_REG_BASE_ADDR     0xF0200000
 236 #define CONFIG_SYS_FPGA_REG_BASE_ADDR   0xF0300000
 237
 238 /*-----------------------------------------------------------------------
 239  * Start addresses for the final memory configuration
 240  * (Set up by the startup code)
 241  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 242  */
 243 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 244 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 245 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 246 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 247 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 248
 249 /*
 250  * For booting Linux, the board info and command line data
 251  * have to be in the first 8 MB of memory, since this is
 252  * the maximum mapped by the Linux kernel during initialization.
 253  */
 254 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 255
 256 /*-----------------------------------------------------------------------
 257  * FLASH organization
 258  */
 259 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 260 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 261
 262 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 263 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 264
 265 /*
 266  * Init Memory Controller:
 267  *
 268  * BR0/1 and OR0/1 (FLASH)
 269  */
 270
 271 #define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* FLASH bank #0        */
 272 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 273
 274
 275 /* Configuration Port location */
 276 #define CONFIG_PORT_ADDR        0xF0000500
 277
 278 #if defined(CONFIG_CMD_KGDB)
 279 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 280 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 281 #endif
 282 #endif  /* __CONFIG_H */