include/configs/M5253DEMO.h

   1 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   2  * Hayden Fraser (Hayden.Fraser@freescale.com)
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _M5253DEMO_H
   8 #define _M5253DEMO_H
   9
  10 #define CONFIG_M5253DEMO        /* define board type */
  11
  12 #define CONFIG_MCFTMR
  13
  14 #define CONFIG_MCFUART
  15 #define CONFIG_SYS_UART_PORT            (0)
  16 #define CONFIG_BAUDRATE         115200
  17
  18 #undef CONFIG_WATCHDOG          /* disable watchdog */
  19
  20
  21 /* Configuration for environment
  22  * Environment is embedded in u-boot in the second sector of the flash
  23  */
  24 #ifdef CONFIG_MONITOR_IS_IN_RAM
  25 #       define CONFIG_ENV_OFFSET                0x4000
  26 #       define CONFIG_ENV_SECT_SIZE     0x1000
  27 #       define CONFIG_ENV_IS_IN_FLASH   1
  28 #else
  29 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x4000)
  30 #       define CONFIG_ENV_SECT_SIZE     0x1000
  31 #       define CONFIG_ENV_IS_IN_FLASH   1
  32 #endif
  33
  34 #define LDS_BOARD_TEXT \
  35         . = DEFINED(env_offset) ? env_offset : .; \
  36         common/env_embedded.o (.text*);
  37
  38 /*
  39  * Command line configuration.
  40  */
  41 #define CONFIG_CMD_IDE
  42
  43 #ifdef CONFIG_CMD_IDE
  44 /* ATA */
  45 #       define CONFIG_IDE_RESET         1
  46 #       define CONFIG_IDE_PREINIT       1
  47 #       define CONFIG_ATAPI
  48 #       undef CONFIG_LBA48
  49
  50 #       define CONFIG_SYS_IDE_MAXBUS            1
  51 #       define CONFIG_SYS_IDE_MAXDEVICE 2
  52
  53 #       define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
  54 #       define CONFIG_SYS_ATA_IDE0_OFFSET       0
  55
  56 #       define CONFIG_SYS_ATA_DATA_OFFSET       0xA0    /* Offset for data I/O */
  57 #       define CONFIG_SYS_ATA_REG_OFFSET        0xA0    /* Offset for normal register accesses */
  58 #       define CONFIG_SYS_ATA_ALT_OFFSET        0xC0    /* Offset for alternate registers */
  59 #       define CONFIG_SYS_ATA_STRIDE            4       /* Interval between registers */
  60 #endif
  61
  62 #define CONFIG_DRIVER_DM9000
  63 #ifdef CONFIG_DRIVER_DM9000
  64 #       define CONFIG_DM9000_BASE       (CONFIG_SYS_CS1_BASE | 0x300)
  65 #       define DM9000_IO                CONFIG_DM9000_BASE
  66 #       define DM9000_DATA              (CONFIG_DM9000_BASE + 4)
  67 #       undef CONFIG_DM9000_DEBUG
  68 #       define CONFIG_DM9000_BYTE_SWAPPED
  69
  70 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  71
  72 #       define CONFIG_EXTRA_ENV_SETTINGS                \
  73                 "netdev=eth0\0"                         \
  74                 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  75                 "loadaddr=10000\0"                      \
  76                 "u-boot=u-boot.bin\0"                   \
  77                 "load=tftp ${loadaddr) ${u-boot}\0"     \
  78                 "upd=run load; run prog\0"              \
  79                 "prog=prot off 0xff800000 0xff82ffff;"  \
  80                 "era 0xff800000 0xff82ffff;"            \
  81                 "cp.b ${loadaddr} 0xff800000 ${filesize};"      \
  82                 "save\0"                                \
  83                 ""
  84 #endif
  85
  86 #define CONFIG_HOSTNAME         M5253DEMO
  87
  88 /* I2C */
  89 #define CONFIG_SYS_I2C
  90 #define CONFIG_SYS_I2C_FSL
  91 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  92 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  93 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000280
  94 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
  95 #define CONFIG_SYS_I2C_PINMUX_REG       (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
  96 #define CONFIG_SYS_I2C_PINMUX_CLR       (0xFFFFE7FF)
  97 #define CONFIG_SYS_I2C_PINMUX_SET       (0)
  98
  99 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 100
 101 #if defined(CONFIG_CMD_KGDB)
 102 #       define CONFIG_SYS_CBSIZE                1024    /* Console I/O Buffer Size */
 103 #else
 104 #       define CONFIG_SYS_CBSIZE                256     /* Console I/O Buffer Size */
 105 #endif
 106 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 107 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 108 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 109
 110 #define CONFIG_SYS_LOAD_ADDR            0x00100000
 111
 112 #define CONFIG_SYS_MEMTEST_START        0x400
 113 #define CONFIG_SYS_MEMTEST_END          0x380000
 114
 115 #undef CONFIG_SYS_PLL_BYPASS            /* bypass PLL for test purpose */
 116 #define CONFIG_SYS_FAST_CLK
 117 #ifdef CONFIG_SYS_FAST_CLK
 118 #       define CONFIG_SYS_PLLCR 0x1243E054
 119 #       define CONFIG_SYS_CLK           140000000
 120 #else
 121 #       define CONFIG_SYS_PLLCR 0x135a4140
 122 #       define CONFIG_SYS_CLK           70000000
 123 #endif
 124
 125 /*
 126  * Low Level Configuration Settings
 127  * (address mappings, register initial values, etc.)
 128  * You should know what you are doing if you make changes here.
 129  */
 130
 131 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
 132 #define CONFIG_SYS_MBAR2                0x80000000      /* Module Base Addrs 2 */
 133
 134 /*
 135  * Definitions for initial stack pointer and data area (in DPRAM)
 136  */
 137 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 138 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
 139 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 140 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 141
 142 /*
 143  * Start addresses for the final memory configuration
 144  * (Set up by the startup code)
 145  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 146  */
 147 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 148 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 149
 150 #ifdef CONFIG_MONITOR_IS_IN_RAM
 151 #       define CONFIG_SYS_MONITOR_BASE  0x20000
 152 #else
 153 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 154 #endif
 155
 156 #define CONFIG_SYS_MONITOR_LEN          0x40000
 157 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 158 #define CONFIG_SYS_BOOTPARAMS_LEN       (64*1024)
 159
 160 /*
 161  * For booting Linux, the board info and command line data
 162  * have to be in the first 8 MB of memory, since this is
 163  * the maximum mapped by the Linux kernel during initialization ??
 164  */
 165 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 166 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 167
 168 /* FLASH organization */
 169 #define CONFIG_SYS_FLASH_BASE           (CONFIG_SYS_CS0_BASE)
 170 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 171 #define CONFIG_SYS_MAX_FLASH_SECT       2048    /* max number of sectors on one chip */
 172 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 173
 174 #define FLASH_SST6401B          0x200
 175 #define SST_ID_xF6401B          0x236D236D
 176
 177 #undef CONFIG_SYS_FLASH_CFI
 178 #ifdef CONFIG_SYS_FLASH_CFI
 179 /*
 180  * Unable to use CFI driver, due to incompatible sector erase command by SST.
 181  * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
 182  * 0x30 is block erase in SST
 183  */
 184 #       define CONFIG_FLASH_CFI_DRIVER  1
 185 #       define CONFIG_SYS_FLASH_SIZE            0x800000
 186 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 187 #       define CONFIG_FLASH_CFI_LEGACY
 188 #else
 189 #       define CONFIG_SYS_SST_SECT              2048
 190 #       define CONFIG_SYS_SST_SECTSZ            0x1000
 191 #       define CONFIG_SYS_FLASH_WRITE_TOUT      500
 192 #endif
 193
 194 /* Cache Configuration */
 195 #define CONFIG_SYS_CACHELINE_SIZE       16
 196
 197 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 198                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 199 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 200                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 201 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_DCM)
 202 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_FLASH_BASE | \
 203                                          CF_ADDRMASK(8) | \
 204                                          CF_ACR_EN | CF_ACR_SM_ALL)
 205 #define CONFIG_SYS_CACHE_ACR1           (CONFIG_SYS_SDRAM_BASE | \
 206                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 207                                          CF_ACR_EN | CF_ACR_SM_ALL)
 208 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CEIB | \
 209                                          CF_CACR_DBWE)
 210
 211 /* Port configuration */
 212 #define CONFIG_SYS_FECI2C               0xF0
 213
 214 #define CONFIG_SYS_CS0_BASE             0xFF800000
 215 #define CONFIG_SYS_CS0_MASK             0x007F0021
 216 #define CONFIG_SYS_CS0_CTRL             0x00001D80
 217
 218 #define CONFIG_SYS_CS1_BASE             0xE0000000
 219 #define CONFIG_SYS_CS1_MASK             0x00000001
 220 #define CONFIG_SYS_CS1_CTRL             0x00003DD8
 221
 222 /*-----------------------------------------------------------------------
 223  * Port configuration
 224  */
 225 #define CONFIG_SYS_GPIO_FUNC            0x00000008      /* Set gpio pins: none */
 226 #define CONFIG_SYS_GPIO1_FUNC           0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54 */
 227 #define CONFIG_SYS_GPIO_EN              0x00000008      /* Set gpio output enable */
 228 #define CONFIG_SYS_GPIO1_EN             0x00c70000      /* Set gpio output enable */
 229 #define CONFIG_SYS_GPIO_OUT             0x00000008      /* Set outputs to default state */
 230 #define CONFIG_SYS_GPIO1_OUT            0x00c70000      /* Set outputs to default state */
 231 #define CONFIG_SYS_GPIO1_LED            0x00400000      /* user led */
 232
 233 #endif                          /* _M5253DEMO_H */