include/configs/M5282EVB.h

   1 /*
   2  * Configuation settings for the Motorola MC5282EVB board.
   3  *
   4  * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * board/config.h - configuration options, board specific
  11  */
  12
  13 #ifndef _CONFIG_M5282EVB_H
  14 #define _CONFIG_M5282EVB_H
  15
  16 /*
  17  * High Level Configuration Options
  18  * (easy to change)
  19  */
  20 #define CONFIG_MCFTMR
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24 #define CONFIG_BAUDRATE         115200
  25
  26 #undef  CONFIG_MONITOR_IS_IN_RAM        /* define if monitor is started from a pre-loader */
  27
  28 /* Configuration for environment
  29  * Environment is embedded in u-boot in the second sector of the flash
  30  */
  31 #define CONFIG_ENV_ADDR         0xffe04000
  32 #define CONFIG_ENV_SIZE         0x2000
  33 #define CONFIG_ENV_IS_IN_FLASH  1
  34
  35 /*
  36  * BOOTP options
  37  */
  38 #define CONFIG_BOOTP_BOOTFILESIZE
  39 #define CONFIG_BOOTP_BOOTPATH
  40 #define CONFIG_BOOTP_GATEWAY
  41 #define CONFIG_BOOTP_HOSTNAME
  42
  43 /*
  44  * Command line configuration.
  45  */
  46 #include <config_cmd_default.h>
  47 #define CONFIG_CMD_CACHE
  48 #define CONFIG_CMD_NET
  49 #define CONFIG_CMD_PING
  50 #define CONFIG_CMD_MII
  51
  52 #undef CONFIG_CMD_LOADS
  53 #undef CONFIG_CMD_LOADB
  54
  55 #define CONFIG_MCFFEC
  56 #ifdef CONFIG_MCFFEC
  57 #       define CONFIG_MII               1
  58 #       define CONFIG_MII_INIT          1
  59 #       define CONFIG_SYS_DISCOVER_PHY
  60 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  61 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  62
  63 #       define CONFIG_SYS_FEC0_PINMUX           0
  64 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  65 #       define MCFFEC_TOUT_LOOP         50000
  66 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  67 #       ifndef CONFIG_SYS_DISCOVER_PHY
  68 #               define FECDUPLEX        FULL
  69 #               define FECSPEED         _100BASET
  70 #       else
  71 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  72 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  73 #               endif
  74 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  75 #endif
  76
  77 #define CONFIG_BOOTDELAY        5
  78 #ifdef CONFIG_MCFFEC
  79 #       define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
  80 #       define CONFIG_IPADDR    192.162.1.2
  81 #       define CONFIG_NETMASK   255.255.255.0
  82 #       define CONFIG_SERVERIP  192.162.1.1
  83 #       define CONFIG_GATEWAYIP 192.162.1.1
  84 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  85 #endif                          /* CONFIG_MCFFEC */
  86
  87 #define CONFIG_HOSTNAME         M5282EVB
  88 #define CONFIG_EXTRA_ENV_SETTINGS               \
  89         "netdev=eth0\0"                         \
  90         "loadaddr=10000\0"                      \
  91         "u-boot=u-boot.bin\0"                   \
  92         "load=tftp ${loadaddr) ${u-boot}\0"     \
  93         "upd=run load; run prog\0"              \
  94         "prog=prot off ffe00000 ffe3ffff;"      \
  95         "era ffe00000 ffe3ffff;"                \
  96         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  97         "save\0"                                \
  98         ""
  99
 100 #define CONFIG_SYS_PROMPT               "-> "
 101 #define CONFIG_SYS_LONGHELP             /* undef to save memory         */
 102
 103 #if defined(CONFIG_CMD_KGDB)
 104 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 105 #else
 106 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 107 #endif
 108 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 109 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 110 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 111
 112 #define CONFIG_SYS_LOAD_ADDR            0x20000
 113
 114 #define CONFIG_SYS_MEMTEST_START        0x400
 115 #define CONFIG_SYS_MEMTEST_END          0x380000
 116
 117 #define CONFIG_SYS_CLK                  64000000
 118
 119 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
 120
 121 #define CONFIG_SYS_MFD                  0x02    /* PLL Multiplication Factor Devider */
 122 #define CONFIG_SYS_RFD                  0x00    /* PLL Reduce Frecuency Devider */
 123
 124 /*
 125  * Low Level Configuration Settings
 126  * (address mappings, register initial values, etc.)
 127  * You should know what you are doing if you make changes here.
 128  */
 129 #define CONFIG_SYS_MBAR         0x40000000
 130
 131 /*-----------------------------------------------------------------------
 132  * Definitions for initial stack pointer and data area (in DPRAM)
 133  */
 134 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 135 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM    */
 136 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 137 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 138
 139 /*-----------------------------------------------------------------------
 140  * Start addresses for the final memory configuration
 141  * (Set up by the startup code)
 142  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 143  */
 144 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 145 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 146 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 147 #define CONFIG_SYS_INT_FLASH_BASE       0xf0000000
 148 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 149
 150 /* If M5282 port is fully implemented the monitor base will be behind
 151  * the vector table. */
 152 #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
 153 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 154 #else
 155 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418)  /* 24 Byte for CFM-Config */
 156 #endif
 157
 158 #define CONFIG_SYS_MONITOR_LEN          0x20000
 159 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 160 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 161
 162 /*
 163  * For booting Linux, the board info and command line data
 164  * have to be in the first 8 MB of memory, since this is
 165  * the maximum mapped by the Linux kernel during initialization ??
 166  */
 167 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 168
 169 /*-----------------------------------------------------------------------
 170  * FLASH organization
 171  */
 172 #define CONFIG_SYS_FLASH_CFI
 173 #ifdef CONFIG_SYS_FLASH_CFI
 174
 175 #       define CONFIG_FLASH_CFI_DRIVER  1
 176 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 177 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 178 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 179 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 180 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 181 #       define CONFIG_SYS_FLASH_CHECKSUM
 182 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_FLASH_BASE }
 183 #endif
 184
 185 /*-----------------------------------------------------------------------
 186  * Cache Configuration
 187  */
 188 #define CONFIG_SYS_CACHELINE_SIZE       16
 189
 190 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 191                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 192 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 193                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 194 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 195 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 196                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 197                                          CF_ACR_EN | CF_ACR_SM_ALL)
 198 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 199                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 200                                          CF_CACR_EUSP)
 201
 202 /*-----------------------------------------------------------------------
 203  * Memory bank definitions
 204  */
 205 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 206 #define CONFIG_SYS_CS0_CTRL             0x00001980
 207 #define CONFIG_SYS_CS0_MASK             0x001F0001
 208
 209 /*-----------------------------------------------------------------------
 210  * Port configuration
 211  */
 212 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 213 #define CONFIG_SYS_PADDR                0x0000000
 214 #define CONFIG_SYS_PADAT                0x0000000
 215
 216 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 217 #define CONFIG_SYS_PBDDR                0x0000000
 218 #define CONFIG_SYS_PBDAT                0x0000000
 219
 220 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 221 #define CONFIG_SYS_PCDDR                0x0000000
 222 #define CONFIG_SYS_PCDAT                0x0000000
 223
 224 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 225 #define CONFIG_SYS_PCDDR                0x0000000
 226 #define CONFIG_SYS_PCDAT                0x0000000
 227
 228 #define CONFIG_SYS_PEHLPAR              0xC0
 229 #define CONFIG_SYS_PUAPAR               0x0F    /* UA0..UA3 = Uart 0 +1 */
 230 #define CONFIG_SYS_DDRUA                0x05
 231 #define CONFIG_SYS_PJPAR                0xFF
 232
 233 #endif                          /* _CONFIG_M5282EVB_H */