include/configs/MOUSSE.h

   1 /*
   2  * (C) Copyright 2000, 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2001
   6  * James F. Dougherty (jfd@cs.stanford.edu)
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  *
  29  * Configuration settings for the MOUSSE board.
  30  * See also: http://www.vooha.com/
  31  *
  32  */
  33
  34 /* ------------------------------------------------------------------------- */
  35
  36 /*
  37  * board/config.h - configuration options, board specific
  38  */
  39
  40 #ifndef __CONFIG_H
  41 #define __CONFIG_H
  42
  43 /*
  44  * High Level Configuration Options
  45  * (easy to change)
  46  */
  47
  48 #define CONFIG_MPC824X      1
  49 #define CONFIG_MPC8240      1
  50 #define CONFIG_MOUSSE       1
  51 #define CFG_ADDR_MAP_B      1
  52 #define CONFIG_CONS_INDEX   1
  53 #define CONFIG_BAUDRATE     9600
  54 #if 1
  55 #define CONFIG_BOOTCOMMAND  "tftp 100000 vmlinux.img;bootm"    /* autoboot command */
  56 #else
  57 #define CONFIG_BOOTCOMMAND  "bootm ffe10000"
  58 #endif
  59 #define CONFIG_BOOTARGS      "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
  60 #define CONFIG_BOOTDELAY     3
  61 #define CONFIG_COMMANDS      (CONFIG_CMD_DFL|CFG_CMD_ASKENV|CFG_CMD_DATE)
  62 #define CONFIG_ENV_OVERWRITE 1
  63 #define CONFIG_ETH_ADDR      "00:10:18:10:00:06"
  64
  65 #define CONFIG_DOS_PARTITION  1 /* MSDOS bootable partitiion support */
  66 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
  67  */
  68 #include <cmd_confdefs.h>
  69 #include "../board/mousse/mousse.h"
  70
  71 /*
  72  * Miscellaneous configurable options
  73  */
  74 #undef CFG_LONGHELP                /* undef to save memory     */
  75 #define CFG_PROMPT      "=>"  /* Monitor Command Prompt   */
  76 #define CFG_CBSIZE      256        /* Console I/O Buffer Size  */
  77 #define CFG_PBSIZE      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
  78 #define CFG_MAXARGS     8           /* Max number of command args   */
  79
  80 #define CFG_BARGSIZE    CFG_CBSIZE  /* Boot Argument Buffer Size    */
  81 #define CFG_LOAD_ADDR   0x00100000  /* Default load address         */
  82
  83 /*-----------------------------------------------------------------------
  84  * Start addresses for the final memory configuration
  85  * (Set up by the startup code)
  86  * Please note that CFG_SDRAM_BASE _must_ start at 0
  87  */
  88 #define CFG_SDRAM_BASE      0x00000000
  89
  90 #ifdef DEBUG
  91 #define CFG_MONITOR_BASE    CFG_SDRAM_BASE
  92 #else
  93 #define CFG_MONITOR_BASE    CFG_FLASH_BASE
  94 #endif
  95
  96 #ifdef DEBUG
  97 #define CFG_MONITOR_LEN     (4 << 20)   /* lots of mem ... */
  98 #else
  99 #define CFG_MONITOR_LEN     (512 << 10) /* 512K PLCC bootrom */
 100 #endif
 101 #define CFG_MALLOC_LEN      (2*(4096 << 10))    /* 2*4096kB for malloc()  */
 102
 103 #define CFG_MEMTEST_START   0x00004000  /* memtest works on      */
 104 #define CFG_MEMTEST_END     0x02000000  /* 0 ... 32 MB in DRAM   */
 105
 106
 107 #define CFG_EUMB_ADDR       0xFC000000
 108
 109 #define CFG_ISA_MEM         0xFD000000
 110 #define CFG_ISA_IO          0xFE000000
 111
 112 #define CFG_FLASH_BASE      0xFFF00000
 113 #define CFG_FLASH_SIZE      ((uint)(512 * 1024))
 114 #define CFG_RESET_ADDRESS   0xFFF00100
 115 #define FLASH_BASE0_PRELIM  0xFFF00000  /* 512K PLCC FLASH/AM29F040*/
 116 #define FLASH_BASE0_SIZE    0x80000     /* 512K */
 117 #define FLASH_BASE1_PRELIM  0xFFE10000  /* AMD 29LV160DB
 118                                            1MB - 64K FLASH0 SEG =960K
 119                                            (size=0xf0000)*/
 120
 121 #define CFG_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
 122
 123 /*
 124  * NS16550 Configuration
 125  */
 126 #define CFG_NS16550
 127 #define CFG_NS16550_SERIAL
 128
 129 #define CFG_NS16550_REG_SIZE    1
 130
 131 #define CFG_NS16550_CLK         18432000
 132
 133 #define CFG_NS16550_COM1        0xFFE08080
 134
 135 /*-----------------------------------------------------------------------
 136  * Definitions for initial stack pointer and data area (in DPRAM)
 137  */
 138 #define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN
 139 #define CFG_INIT_RAM_END   0x2F00  /* End of used area in DPRAM  */
 140 #define CFG_GBL_DATA_SIZE  64  /* size in bytes reserved for initial data */
 141 #define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 142 #define CFG_INIT_SP_OFFSET  CFG_GBL_DATA_OFFSET
 143
 144 /*
 145  * Low Level Configuration Settings
 146  * (address mappings, register initial values, etc.)
 147  * You should know what you are doing if you make changes here.
 148  * For the detail description refer to the MPC8240 user's manual.
 149  */
 150
 151 #define CONFIG_SYS_CLK_FREQ  33000000   /* external frequency to pll */
 152 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2
 153 #define CFG_HZ               1000
 154
 155 #define CFG_ETH_DEV_FN       0x00
 156 #define CFG_ETH_IOBASE       0x00104000
 157
 158
 159         /* Bit-field values for MCCR1.
 160          */
 161 #define CFG_ROMNAL          8
 162 #define CFG_ROMFAL          8
 163
 164         /* Bit-field values for MCCR2.
 165          */
 166 #define CFG_REFINT          0xf5     /* Refresh interval               */
 167
 168         /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 169          */
 170 #define CFG_BSTOPRE         0x79
 171
 172 #ifdef INCLUDE_ECC
 173 #define USE_ECC                         1
 174 #else /* INCLUDE_ECC */
 175 #define USE_ECC                         0
 176 #endif /* INCLUDE_ECC */
 177
 178
 179         /* Bit-field values for MCCR3.
 180          */
 181 #define CFG_REFREC          8       /* Refresh to activate interval   */
 182 #define CFG_RDLAT           (4+USE_ECC)   /* Data latancy from read command */
 183
 184         /* Bit-field values for MCCR4.
 185          */
 186 #define CFG_PRETOACT        3       /* Precharge to activate interval */
 187 #define CFG_ACTTOPRE        5       /* Activate to Precharge interval */
 188 #define CFG_SDMODE_CAS_LAT  3       /* SDMODE CAS latancy             */
 189 #define CFG_SDMODE_WRAP     0       /* SDMODE wrap type               */
 190 #define CFG_SDMODE_BURSTLEN 2       /* SDMODE Burst length            */
 191 #define CFG_ACTORW          2
 192 #define CFG_REGISTERD_TYPE_BUFFER (1-USE_ECC)
 193
 194 /* Memory bank settings.
 195  * Only bits 20-29 are actually used from these vales to set the
 196  * start/end addresses. The upper two bits will always be 0, and the lower
 197  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 198  * address. Refer to the MPC8240 book.
 199  */
 200 #define CFG_RAM_SIZE        0x04000000  /* 64MB */
 201
 202
 203 #define CFG_BANK0_START     0x00000000
 204 #define CFG_BANK0_END       (CFG_RAM_SIZE - 1)
 205 #define CFG_BANK0_ENABLE    1
 206 #define CFG_BANK1_START     0x3ff00000
 207 #define CFG_BANK1_END       0x3fffffff
 208 #define CFG_BANK1_ENABLE    0
 209 #define CFG_BANK2_START     0x3ff00000
 210 #define CFG_BANK2_END       0x3fffffff
 211 #define CFG_BANK2_ENABLE    0
 212 #define CFG_BANK3_START     0x3ff00000
 213 #define CFG_BANK3_END       0x3fffffff
 214 #define CFG_BANK3_ENABLE    0
 215 #define CFG_BANK4_START     0x3ff00000
 216 #define CFG_BANK4_END       0x3fffffff
 217 #define CFG_BANK4_ENABLE    0
 218 #define CFG_BANK5_START     0x3ff00000
 219 #define CFG_BANK5_END       0x3fffffff
 220 #define CFG_BANK5_ENABLE    0
 221 #define CFG_BANK6_START     0x3ff00000
 222 #define CFG_BANK6_END       0x3fffffff
 223 #define CFG_BANK6_ENABLE    0
 224 #define CFG_BANK7_START     0x3ff00000
 225 #define CFG_BANK7_END       0x3fffffff
 226 #define CFG_BANK7_ENABLE    0
 227
 228 #define CFG_ODCR            0x7f
 229
 230
 231 #define CFG_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory
 232                                     see 8240 book for details*/
 233 #define PCI_MEM_SPACE1_START    0x80000000
 234 #define PCI_MEM_SPACE2_START    0xfd000000
 235
 236 /* IBAT/DBAT Configuration */
 237 /* Ram: 64MB, starts at address-0, r/w instruction/data */
 238 #define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
 239 #define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 240 #define CFG_DBAT0U      CFG_IBAT0U
 241 #define CFG_DBAT0L      CFG_IBAT0L
 242
 243 /* MPLD/Port-X I/O Space : data and instruction read/write,  cache-inhibit */
 244 #define CFG_IBAT1U      (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 245 #if 0
 246 #define CFG_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10  | BATL_MEMCOHERENCE |\
 247                          BATL_WRITETHROUGH | BATL_CACHEINHIBIT)
 248 #else
 249 #define CFG_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
 250 #endif
 251 #define CFG_DBAT1U      CFG_IBAT1U
 252 #define CFG_DBAT1L      CFG_IBAT1L
 253
 254 /* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
 255 #define CFG_IBAT2U      (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
 256 #define CFG_IBAT2L      (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
 257 #define CFG_DBAT2U      CFG_IBAT2U
 258 #define CFG_DBAT2L      CFG_IBAT2L
 259
 260 /* PCI Memory region 2: PCI Devices in 0xFD space */
 261 #define CFG_IBAT3U      (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
 262 #define CFG_IBAT3L      (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
 263 #define CFG_DBAT3U      CFG_IBAT3U
 264 #define CFG_DBAT3L      CFG_IBAT3L
 265
 266
 267 /*
 268  * For booting Linux, the board info and command line data
 269  * have to be in the first 8 MB of memory, since this is
 270  * the maximum mapped by the Linux kernel during initialization.
 271  */
 272 #define CFG_BOOTMAPSZ       (8 << 20)   /* Initial Memory map for Linux */
 273
 274 /*-----------------------------------------------------------------------
 275  * FLASH organization
 276  */
 277 #define CFG_MAX_FLASH_BANKS     3       /* Max number of flash banks         */
 278 #define CFG_MAX_FLASH_SECT      64      /* Max number of sectors in one bank */
 279
 280 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)   */
 281 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)   */
 282
 283 #if 0
 284 #define CFG_ENV_IS_IN_FLASH         1
 285 #define CFG_ENV_OFFSET          0x8000  /* Offset of the Environment Sector      */
 286 #define CFG_ENV_SIZE            0x4000  /* Size of the Environment Sector    */
 287 #else
 288 #define CFG_ENV_IS_IN_NVRAM          1
 289 #define CFG_ENV_ADDR            NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/
 290 #define CFG_ENV_OFFSET          CFG_ENV_ADDR
 291 #define CFG_ENV_SIZE            NV_U_BOOT_ENV_SIZE /* 2K */
 292 #endif
 293 /*-----------------------------------------------------------------------
 294  * Cache Configuration
 295  */
 296 #define CFG_CACHELINE_SIZE  16
 297
 298
 299 /*
 300  * Internal Definitions
 301  *
 302  * Boot Flags
 303  */
 304 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 305 #define BOOTFLAG_WARM           0x02    /* Software reboot                  */
 306
 307 /* Localizations */
 308 #if 0
 309 #define CONFIG_ETHADDR          0:0:0:0:1:d
 310 #define CONFIG_IPADDR           172.16.40.113
 311 #define CONFIG_SERVERIP         172.16.40.111
 312 #else
 313 #define CONFIG_ETHADDR          0:0:0:0:1:d
 314 #define CONFIG_IPADDR           209.128.93.138
 315 #define CONFIG_SERVERIP         209.128.93.133
 316 #endif
 317
 318 /*-----------------------------------------------------------------------
 319  * PCI stuff
 320  *-----------------------------------------------------------------------
 321  */
 322 #define CONFIG_PCI                      /* include pci support                  */
 323 #undef CONFIG_PCI_PNP
 324
 325 #define CONFIG_NET_MULTI                /* Multi ethernet cards support         */
 326
 327 #define CONFIG_TULIP
 328
 329 #endif  /* __CONFIG_H */