include/configs/MPC8260ADS.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stuart Hughes <stuarth@lineo.com>
   4  * This file is based on similar values for other boards found in other
   5  * U-Boot config files, and some that I found in the mpc8260ads manual.
   6  *
   7  * Note: my board is a PILOT rev.
   8  * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
   9  *
  10  * (C) Copyright 2003-2004 Arabella Software Ltd.
  11  * Yuli Barcohen <yuli@arabellasw.com>
  12  * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
  13  * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
  14  * Ported to MPC8272ADS board.
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /*
  39  * High Level Configuration Options
  40  * (easy to change)
  41  */
  42
  43 #define CONFIG_MPC8260ADS       1       /* Motorola PQ2 ADS family board */
  44
  45 #define CONFIG_CPM2             1       /* Has a CPM2 */
  46
  47 /*
  48  * Figure out if we are booting low via flash HRCW or high via the BCSR.
  49  */
  50 #if (TEXT_BASE != 0xFFF00000)           /* Boot low (flash HRCW) */
  51 #   define CFG_LOWBOOT          1
  52 #endif
  53
  54
  55 /* ADS flavours */
  56 #define CFG_8260ADS             1       /* MPC8260ADS */
  57 #define CFG_8266ADS             2       /* MPC8266ADS */
  58 #define CFG_PQ2FADS             3       /* PQ2FADS-ZU or PQ2FADS-VR */
  59 #define CFG_8272ADS             4       /* MPC8272ADS */
  60
  61 #ifndef CONFIG_ADSTYPE
  62 #define CONFIG_ADSTYPE          CFG_8260ADS
  63 #endif /* CONFIG_ADSTYPE */
  64
  65 #if CONFIG_ADSTYPE == CFG_8272ADS
  66 #define CONFIG_MPC8272          1
  67 #else
  68 #define CONFIG_MPC8260          1
  69 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
  70
  71 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  72
  73 /* allow serial and ethaddr to be overwritten */
  74 #define CONFIG_ENV_OVERWRITE
  75
  76 /*
  77  * select serial console configuration
  78  *
  79  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  80  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  81  * for SCC).
  82  *
  83  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  84  * defined elsewhere (for example, on the cogent platform, there are serial
  85  * ports on the motherboard which are used for the serial console - see
  86  * cogent/cma101/serial.[ch]).
  87  */
  88 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  89 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  90 #undef  CONFIG_CONS_NONE                /* define if console on something else */
  91 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  92
  93 /*
  94  * select ethernet configuration
  95  *
  96  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  97  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  98  * for FCC)
  99  *
 100  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 101  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 102  * from CONFIG_COMMANDS to remove support for networking.
 103  */
 104 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
 105 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
 106 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 107
 108 #ifdef CONFIG_ETHER_ON_FCC
 109
 110 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
 111
 112 #if   CONFIG_ETHER_INDEX == 1
 113
 114 # define CFG_PHY_ADDR           0
 115 # define CFG_CMXFCR_VALUE       (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
 116 # define CFG_CMXFCR_MASK        (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
 117
 118 #elif CONFIG_ETHER_INDEX == 2
 119
 120 #if CONFIG_ADSTYPE == CFG_8272ADS       /* RxCLK is CLK15, TxCLK is CLK16 */
 121 # define CFG_PHY_ADDR           3
 122 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
 123 #else                                   /* RxCLK is CLK13, TxCLK is CLK14 */
 124 # define CFG_PHY_ADDR           0
 125 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 126 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
 127
 128 # define CFG_CMXFCR_MASK        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 129
 130 #endif  /* CONFIG_ETHER_INDEX */
 131
 132 #define CFG_CPMFCR_RAMTYPE      0               /* BDs and buffers on 60x bus */
 133 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)  /* Full duplex */
 134
 135 #define CONFIG_MII                      /* MII PHY management           */
 136 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 137 /*
 138  * GPIO pins used for bit-banged MII communications
 139  */
 140 #define MDIO_PORT       2               /* Port C */
 141
 142 #if CONFIG_ADSTYPE == CFG_8272ADS
 143 #define CFG_MDIO_PIN    0x00002000      /* PC18 */
 144 #define CFG_MDC_PIN     0x00001000      /* PC19 */
 145 #else
 146 #define CFG_MDIO_PIN    0x00400000      /* PC9  */
 147 #define CFG_MDC_PIN     0x00200000      /* PC10 */
 148 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
 149
 150 #define MDIO_ACTIVE     (iop->pdir |=  CFG_MDIO_PIN)
 151 #define MDIO_TRISTATE   (iop->pdir &= ~CFG_MDIO_PIN)
 152 #define MDIO_READ       ((iop->pdat &  CFG_MDIO_PIN) != 0)
 153
 154 #define MDIO(bit)       if(bit) iop->pdat |=  CFG_MDIO_PIN; \
 155                         else    iop->pdat &= ~CFG_MDIO_PIN
 156
 157 #define MDC(bit)        if(bit) iop->pdat |=  CFG_MDC_PIN; \
 158                         else    iop->pdat &= ~CFG_MDC_PIN
 159
 160 #define MIIDELAY        udelay(1)
 161
 162 #endif /* CONFIG_ETHER_ON_FCC */
 163
 164 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
 165 #undef CONFIG_SPD_EEPROM        /* On new boards, SDRAM is soldered */
 166 #else
 167 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 168 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address  */
 169 #define CFG_I2C_SLAVE           0x7F
 170
 171 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
 172 #define CONFIG_SPD_ADDR         0x50
 173 #endif
 174 #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
 175
 176 #ifndef CONFIG_SDRAM_PBI
 177 #define CONFIG_SDRAM_PBI        0 /* By default, use bank-based interleaving */
 178 #endif
 179
 180 #ifndef CONFIG_8260_CLKIN
 181 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
 182 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 183 #else
 184 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 185 #endif
 186 #endif
 187
 188 #define CONFIG_BAUDRATE         115200
 189
 190 #define CFG_EXCLUDE             CFG_CMD_BEDBUG | \
 191                                 CFG_CMD_BMP     | \
 192                                 CFG_CMD_BSP     | \
 193                                 CFG_CMD_DATE    | \
 194                                 CFG_CMD_DOC     | \
 195                                 CFG_CMD_DTT     | \
 196                                 CFG_CMD_EEPROM | \
 197                                 CFG_CMD_ELF    | \
 198                                 CFG_CMD_EXT2    | \
 199                                 CFG_CMD_FAT    | \
 200                                 CFG_CMD_FDC     | \
 201                                 CFG_CMD_FDOS    | \
 202                                 CFG_CMD_HWFLOW  | \
 203                                 CFG_CMD_IDE     | \
 204                                 CFG_CMD_KGDB    | \
 205                                 CFG_CMD_MMC     | \
 206                                 CFG_CMD_NAND    | \
 207                                 CFG_CMD_PCI     | \
 208                                 CFG_CMD_PCMCIA | \
 209                                 CFG_CMD_REISER  | \
 210                                 CFG_CMD_SCSI    | \
 211                                 CFG_CMD_SPI     | \
 212                                 CFG_CMD_SNTP    | \
 213                                 CFG_CMD_UNIVERSE | \
 214                                 CFG_CMD_USB     | \
 215                                 CFG_CMD_VFD     | \
 216                                 CFG_CMD_XIMG
 217
 218 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
 219 #define CONFIG_COMMANDS         (CFG_CMD_ALL & ~( \
 220                                  CFG_CMD_SDRAM  | \
 221                                  CFG_CMD_I2C    | \
 222                                  CFG_EXCLUDE    ) )
 223 #else
 224 #define CONFIG_COMMANDS         (CFG_CMD_ALL & ~( \
 225                                  CFG_EXCLUDE    ) )
 226 #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
 227
 228 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 229 #include <cmd_confdefs.h>
 230
 231 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds */
 232 #define CONFIG_BOOTCOMMAND      "bootm fff80000"        /* autoboot command */
 233 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2"
 234
 235 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 236 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 237 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 238 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 239 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 240 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 241 #endif
 242
 243 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 244 #undef  CONFIG_WATCHDOG /* disable platform specific watchdog */
 245
 246 /*
 247  * Miscellaneous configurable options
 248  */
 249 #define CFG_HUSH_PARSER
 250 #define CFG_PROMPT_HUSH_PS2 "> "
 251 #define CFG_LONGHELP                    /* undef to save memory     */
 252 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt   */
 253 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 254 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size  */
 255 #else
 256 #define CFG_CBSIZE      256                     /* Console I/O Buffer Size  */
 257 #endif
 258 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 259 #define CFG_MAXARGS     16                      /* max number of command args   */
 260 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 261
 262 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 263 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 264
 265 #define CFG_LOAD_ADDR           0x400000        /* default load address */
 266
 267 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 268
 269 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 270
 271 #define CFG_FLASH_BASE          0xff800000
 272 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 273 #define CFG_MAX_FLASH_SECT      32      /* max num of sects on one chip */
 274 #define CFG_FLASH_SIZE          8
 275 #define CFG_FLASH_ERASE_TOUT    8000    /* Timeout for Flash Erase (in ms)    */
 276 #define CFG_FLASH_WRITE_TOUT    5       /* Timeout for Flash Write (in ms)    */
 277 #define CFG_FLASH_LOCK_TOUT     5       /* Timeout for Flash Set Lock Bit (in ms) */
 278 #define CFG_FLASH_UNLOCK_TOUT   10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 279 #define CFG_FLASH_PROTECTION            /* "Real" (hardware) sectors protection */
 280
 281 /*
 282  * JFFS2 partitions
 283  *
 284  * Note: fake mtd_id used, no linux mtd map file
 285  */
 286 #define MTDIDS_DEFAULT          "nor0=mpc8260ads-0"
 287 #define MTDPARTS_DEFAULT        "mtdparts=mpc8260ads-0:-@1m(jffs2)"
 288 #define CFG_JFFS2_SORT_FRAGMENTS
 289
 290 /* this is stuff came out of the Motorola docs */
 291 #ifndef CFG_LOWBOOT
 292 #define CFG_DEFAULT_IMMR        0x0F010000
 293 #endif
 294
 295 #define CFG_IMMR                0xF0000000
 296 #define CFG_BCSR                0xF4500000
 297 #define CFG_SDRAM_BASE          0x00000000
 298 #define CFG_LSDRAM_BASE         0xFD000000
 299
 300 #define RS232EN_1               0x02000002
 301 #define RS232EN_2               0x01000001
 302 #define FETHIEN1                0x08000008
 303 #define FETH1_RST               0x04000004
 304 #define FETHIEN2                0x10000000
 305 #define FETH2_RST               0x08000000
 306 #define BCSR_PCI_MODE           0x01000000
 307
 308 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 309 #define CFG_INIT_RAM_END        0x2000  /* End of used area in DPRAM    */
 310 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 311 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 312 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 313
 314
 315 #ifdef CFG_LOWBOOT
 316 /* PQ2FADS flash HRCW = 0x0EB4B645 */
 317 #define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                       |\
 318                             ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 )    |\
 319                             ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
 320                             ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )             \
 321                         )
 322 #else
 323 /* PQ2FADS BCSR HRCW = 0x0CB23645 */
 324 #define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )                       |\
 325                             ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
 326                             ( HRCW_BMS | HRCW_APPC10 )                      |\
 327                             ( HRCW_MODCK_H0101 )                             \
 328                         )
 329 #endif
 330 /* no slaves */
 331 #define CFG_HRCW_SLAVE1 0
 332 #define CFG_HRCW_SLAVE2 0
 333 #define CFG_HRCW_SLAVE3 0
 334 #define CFG_HRCW_SLAVE4 0
 335 #define CFG_HRCW_SLAVE5 0
 336 #define CFG_HRCW_SLAVE6 0
 337 #define CFG_HRCW_SLAVE7 0
 338
 339 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 340 #define BOOTFLAG_WARM   0x02    /* Software reboot           */
 341
 342 #define CFG_MONITOR_BASE    TEXT_BASE
 343 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 344 #   define CFG_RAMBOOT
 345 #endif
 346
 347 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 348 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 349
 350 #ifdef CONFIG_BZIP2
 351 #define CFG_MALLOC_LEN          (4096 << 10)    /* Reserve 4 MB for malloc()    */
 352 #else
 353 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 KB for malloc()  */
 354 #endif /* CONFIG_BZIP2 */
 355
 356 #ifndef CFG_RAMBOOT
 357 #  define CFG_ENV_IS_IN_FLASH   1
 358 #  define CFG_ENV_SECT_SIZE     0x40000
 359 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
 360 #else
 361 #  define CFG_ENV_IS_IN_NVRAM   1
 362 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE - 0x1000)
 363 #  define CFG_ENV_SIZE          0x200
 364 #endif /* CFG_RAMBOOT */
 365
 366
 367 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 368 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 369 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 370 #endif
 371
 372
 373 #define CFG_HID0_INIT           0
 374 #define CFG_HID0_FINAL          (HID0_ICE | HID0_IFEM | HID0_ABE )
 375
 376 #define CFG_HID2                0
 377
 378 #define CFG_SYPCR               0xFFFFFFC3
 379 #define CFG_BCR                 0x100C0000
 380 #define CFG_SIUMCR              0x0A200000
 381 #define CFG_SCCR                SCCR_DFBRG01
 382 #define CFG_BR0_PRELIM          CFG_FLASH_BASE | 0x00001801
 383 #define CFG_OR0_PRELIM          0xFF800876
 384 #define CFG_BR1_PRELIM          CFG_BCSR | 0x00001801
 385 #define CFG_OR1_PRELIM          0xFFFF8010
 386
 387 #define CFG_RMR                 RMR_CSRE
 388 #define CFG_TMCNTSC             (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 389 #define CFG_PISCR               (PISCR_PS|PISCR_PTF|PISCR_PTE)
 390 #define CFG_RCCR                0
 391
 392 #if (CONFIG_ADSTYPE == CFG_8266ADS) || (CONFIG_ADSTYPE == CFG_8272ADS)
 393 #undef CFG_LSDRAM_BASE          /* No local bus SDRAM on these boards */
 394 #endif /* CONFIG_ADSTYPE == CFG_8266ADS */
 395
 396 #if CONFIG_ADSTYPE == CFG_PQ2FADS
 397 #define CFG_OR2                 0xFE002EC0
 398 #define CFG_PSDMR               0x824B36A3
 399 #define CFG_PSRT                0x13
 400 #define CFG_LSDMR               0x828737A3
 401 #define CFG_LSRT                0x13
 402 #define CFG_MPTPR               0x2800
 403 #elif CONFIG_ADSTYPE == CFG_8272ADS
 404 #define CFG_OR2                 0xFC002CC0
 405 #define CFG_PSDMR               0x834E24A3
 406 #define CFG_PSRT                0x13
 407 #define CFG_MPTPR               0x2800
 408 #else
 409 #define CFG_OR2                 0xFF000CA0
 410 #define CFG_PSDMR               0x016EB452
 411 #define CFG_PSRT                0x21
 412 #define CFG_LSDMR               0x0086A522
 413 #define CFG_LSRT                0x21
 414 #define CFG_MPTPR               0x1900
 415 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 416
 417 #define CFG_RESET_ADDRESS       0x04400000
 418
 419 #endif /* __CONFIG_H */