include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1       /* E300 family */
  16 #define CONFIG_QE               1       /* Has QE */
  17 #define CONFIG_MPC83XX          1       /* MPC83xx family */
  18 #define CONFIG_MPC832X          1       /* MPC832x CPU specific */
  19
  20 #define CONFIG_PCI              1
  21 #define CONFIG_83XX_GENERIC_PCI 1
  22
  23 /*
  24  * System Clock Setup
  25  */
  26 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  27
  28 #ifndef CONFIG_SYS_CLK_FREQ
  29 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  30 #endif
  31
  32 /*
  33  * Hardware Reset Configuration Word
  34  */
  35 #define CONFIG_SYS_HRCW_LOW (\
  36         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  37         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  38         HRCWL_VCO_1X2 |\
  39         HRCWL_CSB_TO_CLKIN_2X1 |\
  40         HRCWL_CORE_TO_CSB_2_5X1 |\
  41         HRCWL_CE_PLL_VCO_DIV_2 |\
  42         HRCWL_CE_PLL_DIV_1X1 |\
  43         HRCWL_CE_TO_PLL_1X3)
  44
  45 #define CONFIG_SYS_HRCW_HIGH (\
  46         HRCWH_PCI_HOST |\
  47         HRCWH_PCI1_ARBITER_ENABLE |\
  48         HRCWH_CORE_ENABLE |\
  49         HRCWH_FROM_0X00000100 |\
  50         HRCWH_BOOTSEQ_DISABLE |\
  51         HRCWH_SW_WATCHDOG_DISABLE |\
  52         HRCWH_ROM_LOC_LOCAL_16BIT |\
  53         HRCWH_BIG_ENDIAN |\
  54         HRCWH_LALE_NORMAL)
  55
  56 /*
  57  * System IO Config
  58  */
  59 #define CONFIG_SYS_SICRL                0x00000000
  60
  61 #define CONFIG_BOARD_EARLY_INIT_F       /* call board_pre_init */
  62
  63 /*
  64  * IMMR new address
  65  */
  66 #define CONFIG_SYS_IMMR         0xE0000000
  67
  68 /*
  69  * System performance
  70  */
  71 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  72 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  73 #define CONFIG_SYS_SPCR_OPT             1       /* (0-1) Optimize transactions between  CSB and the SEC and QUICC Engine block */
  74
  75 /*
  76  * DDR Setup
  77  */
  78 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory */
  79 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  80 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  81 #define CONFIG_SYS_DDRCDR               0x73000002      /* DDR II voltage is 1.8V */
  82
  83 #undef CONFIG_SPD_EEPROM
  84 #if defined(CONFIG_SPD_EEPROM)
  85 /* Determine DDR configuration from I2C interface
  86  */
  87 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  88 #else
  89 /* Manually set up DDR parameters
  90  */
  91 #define CONFIG_SYS_DDR_SIZE             64      /* MB */
  92 #define CONFIG_SYS_DDR_CS0_CONFIG       ( CSCONFIG_EN \
  93                                 | CSCONFIG_ODT_WR_ACS \
  94                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 )
  95                                 /* 0x80010101 */
  96 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
  97                                 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
  98                                 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
  99                                 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
 100                                 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
 101                                 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
 102                                 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
 103                                 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 104                                 /* 0x00220802 */
 105 #define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
 106                                 | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
 107                                 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
 108                                 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
 109                                 | ( 3 << TIMING_CFG1_REFREC_SHIFT ) \
 110                                 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
 111                                 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 112                                 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
 113                                 /* 0x26253222 */
 114 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
 115                                 | (31 << TIMING_CFG2_CPO_SHIFT ) \
 116                                 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 117                                 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
 118                                 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
 119                                 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
 120                                 | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
 121                                 /* 0x1f9048c7 */
 122 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 123 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 124                                 /* 0x02000000 */
 125 #define CONFIG_SYS_DDR_MODE             ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
 126                                 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
 127                                 /* 0x44480232 */
 128 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 129 #define CONFIG_SYS_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
 130                                 | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
 131                                 /* 0x03200064 */
 132 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
 133 #define CONFIG_SYS_DDR_SDRAM_CFG        ( SDRAM_CFG_SREN \
 134                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 135                                 | SDRAM_CFG_32_BE )
 136                                 /* 0x43080000 */
 137 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 138 #endif
 139
 140 /*
 141  * Memory test
 142  */
 143 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 144 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
 145 #define CONFIG_SYS_MEMTEST_END          0x03f00000
 146
 147 /*
 148  * The reserved memory
 149  */
 150 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 151
 152 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 153 #define CONFIG_SYS_RAMBOOT
 154 #else
 155 #undef  CONFIG_SYS_RAMBOOT
 156 #endif
 157
 158 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 159 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 160 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 161
 162 /*
 163  * Initial RAM Base Address Setup
 164  */
 165 #define CONFIG_SYS_INIT_RAM_LOCK        1
 166 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000      /* Initial RAM address */
 167 #define CONFIG_SYS_INIT_RAM_END 0x1000          /* End of used area in RAM */
 168 #define CONFIG_SYS_GBL_DATA_SIZE        0x100           /* num bytes initial data */
 169 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 170
 171 /*
 172  * Local Bus Configuration & Clock Setup
 173  */
 174 #define CONFIG_SYS_LCRR         (LCRR_DBYP | LCRR_CLKDIV_2)
 175 #define CONFIG_SYS_LBC_LBCR             0x00000000
 176
 177 /*
 178  * FLASH on the Local Bus
 179  */
 180 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 181 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 182 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* FLASH base address */
 183 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 184 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use h/w Flash protection. */
 185
 186 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE   /* Window base at flash base */
 187 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018      /* 32MB window size */
 188
 189 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE |        /* Flash Base address */ \
 190                         (2 << BR_PS_SHIFT) |    /* 16 bit port size */ \
 191                         BR_V)                   /* valid */
 192 #define CONFIG_SYS_OR0_PRELIM           0xfe006ff7      /* 16MB Flash size */
 193
 194 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 195 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 196
 197 #undef CONFIG_SYS_FLASH_CHECKSUM
 198
 199 /*
 200  * SDRAM on the Local Bus
 201  */
 202 #undef CONFIG_SYS_LB_SDRAM              /* The board has not SRDAM on local bus */
 203
 204 #ifdef CONFIG_SYS_LB_SDRAM
 205 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* SDRAM base address */
 206 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 207
 208 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 209 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000019      /* 64MB */
 210
 211 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
 212 /*
 213  * Base Register 2 and Option Register 2 configure SDRAM.
 214  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 215  *
 216  * For BR2, need:
 217  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 218  *    port size = 32-bits = BR2[19:20] = 11
 219  *    no parity checking = BR2[21:22] = 00
 220  *    SDRAM for MSEL = BR2[24:26] = 011
 221  *    Valid = BR[31] = 1
 222  *
 223  * 0    4    8    12   16   20   24   28
 224  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 225  *
 226  * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 227  * the top 17 bits of BR2.
 228  */
 229
 230 #define CONFIG_SYS_BR2_PRELIM   0xf0001861      /*Port size=32bit, MSEL=SDRAM */
 231
 232 /*
 233  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 234  *
 235  * For OR2, need:
 236  *    64MB mask for AM, OR2[0:7] = 1111 1100
 237  *                 XAM, OR2[17:18] = 11
 238  *    9 columns OR2[19-21] = 010
 239  *    13 rows   OR2[23-25] = 100
 240  *    EAD set for extra time OR[31] = 1
 241  *
 242  * 0    4    8    12   16   20   24   28
 243  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 244  */
 245
 246 #define CONFIG_SYS_OR2_PRELIM   0xfc006901
 247
 248 #define CONFIG_SYS_LBC_LSRT     0x32000000      /* LB sdram refresh timer, about 6us */
 249 #define CONFIG_SYS_LBC_MRTPR    0x20000000      /* LB refresh timer prescal, 266MHz/32 */
 250
 251 #define CONFIG_SYS_LBC_LSDMR_COMMON     0x0063b723
 252
 253 #endif
 254
 255 /*
 256  * Windows to access PIB via local bus
 257  */
 258 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0xf8008000      /* windows base 0xf8008000 */
 259 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000f      /* windows size 64KB */
 260
 261 /*
 262  * Serial Port
 263  */
 264 #define CONFIG_CONS_INDEX       1
 265 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 266 #define CONFIG_SYS_NS16550
 267 #define CONFIG_SYS_NS16550_SERIAL
 268 #define CONFIG_SYS_NS16550_REG_SIZE     1
 269 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 270
 271 #define CONFIG_SYS_BAUDRATE_TABLE  \
 272         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 273
 274 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 275 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 276
 277 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 278 /* Use the HUSH parser */
 279 #define CONFIG_SYS_HUSH_PARSER
 280 #ifdef CONFIG_SYS_HUSH_PARSER
 281 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 282 #endif
 283
 284 /* pass open firmware flat tree */
 285 #define CONFIG_OF_LIBFDT        1
 286 #define CONFIG_OF_BOARD_SETUP   1
 287 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 288
 289 /* I2C */
 290 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 291 #undef CONFIG_SOFT_I2C          /* I2C bit-banged */
 292 #define CONFIG_FSL_I2C
 293 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 294 #define CONFIG_SYS_I2C_SLAVE    0x7F
 295 #define CONFIG_SYS_I2C_NOPROBES {0x51}  /* Don't probe these addrs */
 296 #define CONFIG_SYS_I2C_OFFSET   0x3000
 297
 298 /*
 299  * Config on-board EEPROM
 300  */
 301 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 302 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 303 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 304 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 305
 306 /*
 307  * General PCI
 308  * Addresses are mapped 1-1.
 309  */
 310 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 311 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 312 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 313 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 314 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 315 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 316 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 317 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 318 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 319
 320 #ifdef CONFIG_PCI
 321 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 322 #define CONFIG_NET_MULTI
 323 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 324
 325 #undef CONFIG_EEPRO100
 326 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 327 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 328
 329 #endif  /* CONFIG_PCI */
 330
 331
 332 #ifndef CONFIG_NET_MULTI
 333 #define CONFIG_NET_MULTI        1
 334 #endif
 335
 336 /*
 337  * QE UEC ethernet configuration
 338  */
 339 #define CONFIG_UEC_ETH
 340 #define CONFIG_ETHPRIME         "FSL UEC0"
 341
 342 #define CONFIG_UEC_ETH1         /* ETH3 */
 343
 344 #ifdef CONFIG_UEC_ETH1
 345 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 346 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 347 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 348 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 349 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 350 #define CONFIG_SYS_UEC1_INTERFACE_MODE  ENET_100_MII
 351 #endif
 352
 353 #define CONFIG_UEC_ETH2         /* ETH4 */
 354
 355 #ifdef CONFIG_UEC_ETH2
 356 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 357 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 358 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 359 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 360 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 361 #define CONFIG_SYS_UEC2_INTERFACE_MODE  ENET_100_MII
 362 #endif
 363
 364 /*
 365  * Environment
 366  */
 367 #ifndef CONFIG_SYS_RAMBOOT
 368         #define CONFIG_ENV_IS_IN_FLASH  1
 369         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 370         #define CONFIG_ENV_SECT_SIZE    0x20000
 371         #define CONFIG_ENV_SIZE         0x2000
 372 #else
 373         #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 374         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 375         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 376         #define CONFIG_ENV_SIZE         0x2000
 377 #endif
 378
 379 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 380 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 381
 382 /*
 383  * BOOTP options
 384  */
 385 #define CONFIG_BOOTP_BOOTFILESIZE
 386 #define CONFIG_BOOTP_BOOTPATH
 387 #define CONFIG_BOOTP_GATEWAY
 388 #define CONFIG_BOOTP_HOSTNAME
 389
 390 /*
 391  * Command line configuration.
 392  */
 393 #include <config_cmd_default.h>
 394
 395 #define CONFIG_CMD_PING
 396 #define CONFIG_CMD_I2C
 397 #define CONFIG_CMD_EEPROM
 398 #define CONFIG_CMD_ASKENV
 399
 400 #if defined(CONFIG_PCI)
 401         #define CONFIG_CMD_PCI
 402 #endif
 403 #if defined(CONFIG_SYS_RAMBOOT)
 404         #undef CONFIG_CMD_SAVEENV
 405         #undef CONFIG_CMD_LOADS
 406 #endif
 407
 408 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 409
 410 /*
 411  * Miscellaneous configurable options
 412  */
 413 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 414 #define CONFIG_SYS_LOAD_ADDR            0x2000000       /* default load address */
 415 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 416
 417 #if (CONFIG_CMD_KGDB)
 418         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 419 #else
 420         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 421 #endif
 422
 423 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 424 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 425 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 426 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 427
 428 /*
 429  * For booting Linux, the board info and command line data
 430  * have to be in the first 8 MB of memory, since this is
 431  * the maximum mapped by the Linux kernel during initialization.
 432  */
 433 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 434
 435 /*
 436  * Core HID Setup
 437  */
 438 #define CONFIG_SYS_HID0_INIT            0x000000000
 439 #define CONFIG_SYS_HID0_FINAL           HID0_ENABLE_MACHINE_CHECK
 440 #define CONFIG_SYS_HID2         HID2_HBE
 441
 442 /*
 443  * MMU Setup
 444  */
 445 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 446
 447 /* DDR: cache cacheable */
 448 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 449 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 450 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 451 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 452
 453 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 454 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 455                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 456 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 457 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 458 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 459
 460 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 461 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 462 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 463 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 464                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 465 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 466
 467 #define CONFIG_SYS_IBAT3L       (0)
 468 #define CONFIG_SYS_IBAT3U       (0)
 469 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 470 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 471
 472 /* Stack in dcache: cacheable, no memory coherence */
 473 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 474 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 475 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 476 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 477
 478 #ifdef CONFIG_PCI
 479 /* PCI MEM space: cacheable */
 480 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 481 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 482 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 483 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 484 /* PCI MMIO space: cache-inhibit and guarded */
 485 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
 486                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 487 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 488 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 489 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 490 #else
 491 #define CONFIG_SYS_IBAT5L       (0)
 492 #define CONFIG_SYS_IBAT5U       (0)
 493 #define CONFIG_SYS_IBAT6L       (0)
 494 #define CONFIG_SYS_IBAT6U       (0)
 495 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 496 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 497 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 498 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 499 #endif
 500
 501 /* Nothing in BAT7 */
 502 #define CONFIG_SYS_IBAT7L       (0)
 503 #define CONFIG_SYS_IBAT7U       (0)
 504 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 505 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 506
 507 /*
 508  * Internal Definitions
 509  *
 510  * Boot Flags
 511  */
 512 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 513 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 514
 515 #if (CONFIG_CMD_KGDB)
 516 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 517 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 518 #endif
 519
 520 /*
 521  * Environment Configuration
 522  */
 523 #define CONFIG_ENV_OVERWRITE
 524
 525 #define CONFIG_HAS_ETH0                         /* add support for "ethaddr" */
 526 #define CONFIG_ETHADDR  00:04:9f:ef:03:01
 527 #define CONFIG_HAS_ETH1                         /* add support for "eth1addr" */
 528 #define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
 529
 530 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
 531 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00  /* MAC address offset in I2C EEPROM */
 532
 533 #define CONFIG_IPADDR           10.0.0.2
 534 #define CONFIG_SERVERIP         10.0.0.1
 535 #define CONFIG_GATEWAYIP        10.0.0.1
 536 #define CONFIG_NETMASK          255.0.0.0
 537 #define CONFIG_NETDEV           eth1
 538
 539 #define CONFIG_HOSTNAME         mpc8323erdb
 540 #define CONFIG_ROOTPATH         /nfsroot
 541 #define CONFIG_RAMDISKFILE      rootfs.ext2.gz.uboot
 542 #define CONFIG_BOOTFILE         uImage
 543 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 544 #define CONFIG_FDTFILE          mpc832x_rdb.dtb
 545
 546 #define CONFIG_LOADADDR         500000  /* default location for tftp and bootm */
 547 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 548 #define CONFIG_BAUDRATE         115200
 549
 550 #define XMK_STR(x)      #x
 551 #define MK_STR(x)       XMK_STR(x)
 552
 553 #define CONFIG_EXTRA_ENV_SETTINGS \
 554         "netdev=" MK_STR(CONFIG_NETDEV) "\0"                            \
 555         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 556         "tftpflash=tftp $loadaddr $uboot;"                              \
 557                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 558                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 559                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 560                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 561                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 562         "fdtaddr=400000\0"                                              \
 563         "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"                          \
 564         "ramdiskaddr=1000000\0"                                         \
 565         "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0"                  \
 566         "console=ttyS0\0"                                               \
 567         "setbootargs=setenv bootargs "                                  \
 568                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 569         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 570                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 571                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 572
 573 #define CONFIG_NFSBOOTCOMMAND                                           \
 574         "setenv rootdev /dev/nfs;"                                      \
 575         "run setbootargs;"                                              \
 576         "run setipargs;"                                                \
 577         "tftp $loadaddr $bootfile;"                                     \
 578         "tftp $fdtaddr $fdtfile;"                                       \
 579         "bootm $loadaddr - $fdtaddr"
 580
 581 #define CONFIG_RAMBOOTCOMMAND                                           \
 582         "setenv rootdev /dev/ram;"                                      \
 583         "run setbootargs;"                                              \
 584         "tftp $ramdiskaddr $ramdiskfile;"                               \
 585         "tftp $loadaddr $bootfile;"                                     \
 586         "tftp $fdtaddr $fdtfile;"                                       \
 587         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 588
 589 #undef MK_STR
 590 #undef XMK_STR
 591
 592 #endif  /* __CONFIG_H */