include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define CONFIG_DISPLAY_BOARDINFO
  13
  14 /*
  15  * High Level Configuration Options
  16  */
  17 #define CONFIG_E300             1       /* E300 family */
  18 #define CONFIG_QE               1       /* Has QE */
  19 #define CONFIG_MPC832x          1       /* MPC832x CPU specific */
  20
  21 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  22
  23 #define CONFIG_PCI              1
  24
  25 /*
  26  * System Clock Setup
  27  */
  28 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  29
  30 #ifndef CONFIG_SYS_CLK_FREQ
  31 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  32 #endif
  33
  34 /*
  35  * Hardware Reset Configuration Word
  36  */
  37 #define CONFIG_SYS_HRCW_LOW (\
  38         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  39         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  40         HRCWL_VCO_1X2 |\
  41         HRCWL_CSB_TO_CLKIN_2X1 |\
  42         HRCWL_CORE_TO_CSB_2_5X1 |\
  43         HRCWL_CE_PLL_VCO_DIV_2 |\
  44         HRCWL_CE_PLL_DIV_1X1 |\
  45         HRCWL_CE_TO_PLL_1X3)
  46
  47 #define CONFIG_SYS_HRCW_HIGH (\
  48         HRCWH_PCI_HOST |\
  49         HRCWH_PCI1_ARBITER_ENABLE |\
  50         HRCWH_CORE_ENABLE |\
  51         HRCWH_FROM_0X00000100 |\
  52         HRCWH_BOOTSEQ_DISABLE |\
  53         HRCWH_SW_WATCHDOG_DISABLE |\
  54         HRCWH_ROM_LOC_LOCAL_16BIT |\
  55         HRCWH_BIG_ENDIAN |\
  56         HRCWH_LALE_NORMAL)
  57
  58 /*
  59  * System IO Config
  60  */
  61 #define CONFIG_SYS_SICRL                0x00000000
  62
  63 /*
  64  * IMMR new address
  65  */
  66 #define CONFIG_SYS_IMMR         0xE0000000
  67
  68 /*
  69  * System performance
  70  */
  71 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  72 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  73 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
  74 #define CONFIG_SYS_SPCR_OPT     1
  75
  76 /*
  77  * DDR Setup
  78  */
  79 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  80 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  81 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  82
  83 #undef CONFIG_SPD_EEPROM
  84 #if defined(CONFIG_SPD_EEPROM)
  85 /* Determine DDR configuration from I2C interface
  86  */
  87 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  88 #else
  89 /* Manually set up DDR parameters
  90  */
  91 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
  92 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  93                                 | CSCONFIG_ROW_BIT_13 \
  94                                 | CSCONFIG_COL_BIT_9)
  95                                 /* 0x80010101 */
  96 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  97                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  98                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  99                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 100                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 101                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 102                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 103                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 104                                 /* 0x00220802 */
 105 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 106                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 107                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 108                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 109                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
 110                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 111                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 112                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 113                                 /* 0x26253222 */
 114 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 115                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
 116                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 117                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 118                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 119                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 120                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
 121                                 /* 0x1f9048c7 */
 122 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 123 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 124                                 /* 0x02000000 */
 125 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 126                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 127                                 /* 0x44480232 */
 128 #define CONFIG_SYS_DDR_MODE2    0x8000c000
 129 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
 130                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 131                                 /* 0x03200064 */
 132 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
 133 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 134                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 135                                 | SDRAM_CFG_32_BE)
 136                                 /* 0x43080000 */
 137 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 138 #endif
 139
 140 /*
 141  * Memory test
 142  */
 143 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 144 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
 145 #define CONFIG_SYS_MEMTEST_END          0x03f00000
 146
 147 /*
 148  * The reserved memory
 149  */
 150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 151
 152 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 153 #define CONFIG_SYS_RAMBOOT
 154 #else
 155 #undef  CONFIG_SYS_RAMBOOT
 156 #endif
 157
 158 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 159 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)    /* Reserve 384 kB for Mon */
 160 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 161
 162 /*
 163  * Initial RAM Base Address Setup
 164  */
 165 #define CONFIG_SYS_INIT_RAM_LOCK        1
 166 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 167 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 168 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 169                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 170
 171 /*
 172  * Local Bus Configuration & Clock Setup
 173  */
 174 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 175 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 176 #define CONFIG_SYS_LBC_LBCR             0x00000000
 177
 178 /*
 179  * FLASH on the Local Bus
 180  */
 181 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 182 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 183 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 184 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 185 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 186
 187                                         /* Window base at flash base */
 188 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 189 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 190
 191 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 192                                 | BR_PS_16      /* 16 bit port */ \
 193                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 194                                 | BR_V)         /* valid */
 195 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 196                                 | OR_GPCM_XAM \
 197                                 | OR_GPCM_CSNT \
 198                                 | OR_GPCM_ACS_DIV2 \
 199                                 | OR_GPCM_XACS \
 200                                 | OR_GPCM_SCY_15 \
 201                                 | OR_GPCM_TRLX_SET \
 202                                 | OR_GPCM_EHTR_SET \
 203                                 | OR_GPCM_EAD)
 204                                 /* 0xFE006FF7 */
 205
 206 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 207 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 208
 209 #undef CONFIG_SYS_FLASH_CHECKSUM
 210
 211 /*
 212  * Serial Port
 213  */
 214 #define CONFIG_CONS_INDEX       1
 215 #define CONFIG_SYS_NS16550
 216 #define CONFIG_SYS_NS16550_SERIAL
 217 #define CONFIG_SYS_NS16550_REG_SIZE     1
 218 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 219
 220 #define CONFIG_SYS_BAUDRATE_TABLE  \
 221                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 222
 223 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 224 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 225
 226 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 227 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 228 /* Use the HUSH parser */
 229 #define CONFIG_SYS_HUSH_PARSER
 230
 231 /* pass open firmware flat tree */
 232 #define CONFIG_OF_LIBFDT        1
 233 #define CONFIG_OF_BOARD_SETUP   1
 234 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 235
 236 /* I2C */
 237 #define CONFIG_SYS_I2C
 238 #define CONFIG_SYS_I2C_FSL
 239 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 240 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 241 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 242 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 243
 244 /*
 245  * Config on-board EEPROM
 246  */
 247 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 248 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 249 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 250 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 251
 252 /*
 253  * General PCI
 254  * Addresses are mapped 1-1.
 255  */
 256 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 257 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 258 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 259 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 260 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 261 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 262 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 263 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 264 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 265
 266 #ifdef CONFIG_PCI
 267 #define CONFIG_PCI_INDIRECT_BRIDGE
 268 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 269 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 270
 271 #undef CONFIG_EEPRO100
 272 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 273 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 274
 275 #endif  /* CONFIG_PCI */
 276
 277 /*
 278  * QE UEC ethernet configuration
 279  */
 280 #define CONFIG_UEC_ETH
 281 #define CONFIG_ETHPRIME         "UEC0"
 282
 283 #define CONFIG_UEC_ETH1         /* ETH3 */
 284
 285 #ifdef CONFIG_UEC_ETH1
 286 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 287 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 288 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 289 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 290 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 291 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 292 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 293 #endif
 294
 295 #define CONFIG_UEC_ETH2         /* ETH4 */
 296
 297 #ifdef CONFIG_UEC_ETH2
 298 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 299 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 300 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 301 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 302 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 303 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 304 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 305 #endif
 306
 307 /*
 308  * Environment
 309  */
 310 #ifndef CONFIG_SYS_RAMBOOT
 311         #define CONFIG_ENV_IS_IN_FLASH  1
 312         #define CONFIG_ENV_ADDR         \
 313                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 314         #define CONFIG_ENV_SECT_SIZE    0x20000
 315         #define CONFIG_ENV_SIZE         0x2000
 316 #else
 317         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 318         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 319         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 320         #define CONFIG_ENV_SIZE         0x2000
 321 #endif
 322
 323 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 324 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 325
 326 /*
 327  * BOOTP options
 328  */
 329 #define CONFIG_BOOTP_BOOTFILESIZE
 330 #define CONFIG_BOOTP_BOOTPATH
 331 #define CONFIG_BOOTP_GATEWAY
 332 #define CONFIG_BOOTP_HOSTNAME
 333
 334 /*
 335  * Command line configuration.
 336  */
 337 #define CONFIG_CMD_PING
 338 #define CONFIG_CMD_I2C
 339 #define CONFIG_CMD_EEPROM
 340 #define CONFIG_CMD_ASKENV
 341
 342 #if defined(CONFIG_PCI)
 343         #define CONFIG_CMD_PCI
 344 #endif
 345
 346 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 347
 348 /*
 349  * Miscellaneous configurable options
 350  */
 351 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 352 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 353
 354 #if (CONFIG_CMD_KGDB)
 355         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 356 #else
 357         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 358 #endif
 359
 360                                 /* Print Buffer Size */
 361 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 362 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 363                                 /* Boot Argument Buffer Size */
 364 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 365
 366 /*
 367  * For booting Linux, the board info and command line data
 368  * have to be in the first 256 MB of memory, since this is
 369  * the maximum mapped by the Linux kernel during initialization.
 370  */
 371                                         /* Initial Memory map for Linux */
 372 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 373
 374 /*
 375  * Core HID Setup
 376  */
 377 #define CONFIG_SYS_HID0_INIT    0x000000000
 378 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 379                                  HID0_ENABLE_INSTRUCTION_CACHE)
 380 #define CONFIG_SYS_HID2         HID2_HBE
 381
 382 /*
 383  * MMU Setup
 384  */
 385 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 386
 387 /* DDR: cache cacheable */
 388 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 389                                 | BATL_PP_RW \
 390                                 | BATL_MEMCOHERENCE)
 391 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 392                                 | BATU_BL_256M \
 393                                 | BATU_VS \
 394                                 | BATU_VP)
 395 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 396 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 397
 398 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 399 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 400                                 | BATL_PP_RW \
 401                                 | BATL_CACHEINHIBIT \
 402                                 | BATL_GUARDEDSTORAGE)
 403 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 404                                 | BATU_BL_4M \
 405                                 | BATU_VS \
 406                                 | BATU_VP)
 407 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 408 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 409
 410 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 411 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE \
 412                                 | BATL_PP_RW \
 413                                 | BATL_MEMCOHERENCE)
 414 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE \
 415                                 | BATU_BL_32M \
 416                                 | BATU_VS \
 417                                 | BATU_VP)
 418 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE \
 419                                 | BATL_PP_RW \
 420                                 | BATL_CACHEINHIBIT \
 421                                 | BATL_GUARDEDSTORAGE)
 422 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 423
 424 #define CONFIG_SYS_IBAT3L       (0)
 425 #define CONFIG_SYS_IBAT3U       (0)
 426 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 427 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 428
 429 /* Stack in dcache: cacheable, no memory coherence */
 430 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 431 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR \
 432                                 | BATU_BL_128K \
 433                                 | BATU_VS \
 434                                 | BATU_VP)
 435 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 436 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 437
 438 #ifdef CONFIG_PCI
 439 /* PCI MEM space: cacheable */
 440 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_MEM_PHYS \
 441                                 | BATL_PP_RW \
 442                                 | BATL_MEMCOHERENCE)
 443 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_MEM_PHYS \
 444                                 | BATU_BL_256M \
 445                                 | BATU_VS \
 446                                 | BATU_VP)
 447 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 448 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 449 /* PCI MMIO space: cache-inhibit and guarded */
 450 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 451                                 | BATL_PP_RW \
 452                                 | BATL_CACHEINHIBIT \
 453                                 | BATL_GUARDEDSTORAGE)
 454 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 455                                 | BATU_BL_256M \
 456                                 | BATU_VS \
 457                                 | BATU_VP)
 458 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 459 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 460 #else
 461 #define CONFIG_SYS_IBAT5L       (0)
 462 #define CONFIG_SYS_IBAT5U       (0)
 463 #define CONFIG_SYS_IBAT6L       (0)
 464 #define CONFIG_SYS_IBAT6U       (0)
 465 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 466 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 467 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 468 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 469 #endif
 470
 471 /* Nothing in BAT7 */
 472 #define CONFIG_SYS_IBAT7L       (0)
 473 #define CONFIG_SYS_IBAT7U       (0)
 474 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 475 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 476
 477 #if (CONFIG_CMD_KGDB)
 478 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 479 #endif
 480
 481 /*
 482  * Environment Configuration
 483  */
 484 #define CONFIG_ENV_OVERWRITE
 485
 486 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
 487 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
 488
 489 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 490  * (see CONFIG_SYS_I2C_EEPROM) */
 491                                         /* MAC address offset in I2C EEPROM */
 492 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
 493
 494 #define CONFIG_NETDEV           "eth1"
 495
 496 #define CONFIG_HOSTNAME         mpc8323erdb
 497 #define CONFIG_ROOTPATH         "/nfsroot"
 498 #define CONFIG_BOOTFILE         "uImage"
 499                                 /* U-Boot image on TFTP server */
 500 #define CONFIG_UBOOTPATH        "u-boot.bin"
 501 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
 502 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 503
 504                                 /* default location for tftp and bootm */
 505 #define CONFIG_LOADADDR         800000
 506 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 507 #define CONFIG_BAUDRATE         115200
 508
 509 #define CONFIG_EXTRA_ENV_SETTINGS \
 510         "netdev=" CONFIG_NETDEV "\0"                                    \
 511         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 512         "tftpflash=tftp $loadaddr $uboot;"                              \
 513                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 514                         " +$filesize; " \
 515                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 516                         " +$filesize; " \
 517                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 518                         " $filesize; "  \
 519                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 520                         " +$filesize; " \
 521                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 522                         " $filesize\0"  \
 523         "fdtaddr=780000\0"                                              \
 524         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 525         "ramdiskaddr=1000000\0"                                         \
 526         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 527         "console=ttyS0\0"                                               \
 528         "setbootargs=setenv bootargs "                                  \
 529                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
 530         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 531                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 532                                                                 "$netdev:off "\
 533                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 534
 535 #define CONFIG_NFSBOOTCOMMAND                                           \
 536         "setenv rootdev /dev/nfs;"                                      \
 537         "run setbootargs;"                                              \
 538         "run setipargs;"                                                \
 539         "tftp $loadaddr $bootfile;"                                     \
 540         "tftp $fdtaddr $fdtfile;"                                       \
 541         "bootm $loadaddr - $fdtaddr"
 542
 543 #define CONFIG_RAMBOOTCOMMAND                                           \
 544         "setenv rootdev /dev/ram;"                                      \
 545         "run setbootargs;"                                              \
 546         "tftp $ramdiskaddr $ramdiskfile;"                               \
 547         "tftp $loadaddr $bootfile;"                                     \
 548         "tftp $fdtaddr $fdtfile;"                                       \
 549         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 550
 551 #endif  /* __CONFIG_H */