include/configs/MPC832XEMDS.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 #undef DEBUG
  24
  25 /*
  26  * High Level Configuration Options
  27  */
  28 #define CONFIG_E300             1       /* E300 family */
  29 #define CONFIG_QE               1       /* Has QE */
  30 #define CONFIG_MPC83XX          1       /* MPC83xx family */
  31 #define CONFIG_MPC832X          1       /* MPC832x CPU specific */
  32 #define CONFIG_MPC832XEMDS      1       /* MPC832XEMDS board specific */
  33 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
  34 #undef CONFIG_PQ_MDS_PIB_ATM    /* QOC3 ATM card */
  35
  36 /*
  37  * System Clock Setup
  38  */
  39 #ifdef CONFIG_PCISLAVE
  40 #define CONFIG_83XX_PCICLK      66000000        /* in HZ */
  41 #else
  42 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  43 #endif
  44
  45 #ifndef CONFIG_SYS_CLK_FREQ
  46 #define CONFIG_SYS_CLK_FREQ     66000000
  47 #endif
  48
  49 /*
  50  * Hardware Reset Configuration Word
  51  */
  52 #define CFG_HRCW_LOW (\
  53         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  54         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  55         HRCWL_VCO_1X2 |\
  56         HRCWL_CSB_TO_CLKIN_2X1 |\
  57         HRCWL_CORE_TO_CSB_2X1 |\
  58         HRCWL_CE_PLL_VCO_DIV_2 |\
  59         HRCWL_CE_PLL_DIV_1X1 |\
  60         HRCWL_CE_TO_PLL_1X3)
  61
  62 #ifdef CONFIG_PCISLAVE
  63 #define CFG_HRCW_HIGH (\
  64         HRCWH_PCI_AGENT |\
  65         HRCWH_PCI1_ARBITER_DISABLE |\
  66         HRCWH_CORE_ENABLE |\
  67         HRCWH_FROM_0XFFF00100 |\
  68         HRCWH_BOOTSEQ_DISABLE |\
  69         HRCWH_SW_WATCHDOG_DISABLE |\
  70         HRCWH_ROM_LOC_LOCAL_16BIT |\
  71         HRCWH_BIG_ENDIAN |\
  72         HRCWH_LALE_NORMAL)
  73 #else
  74 #define CFG_HRCW_HIGH (\
  75         HRCWH_PCI_HOST |\
  76         HRCWH_PCI1_ARBITER_ENABLE |\
  77         HRCWH_CORE_ENABLE |\
  78         HRCWH_FROM_0X00000100 |\
  79         HRCWH_BOOTSEQ_DISABLE |\
  80         HRCWH_SW_WATCHDOG_DISABLE |\
  81         HRCWH_ROM_LOC_LOCAL_16BIT |\
  82         HRCWH_BIG_ENDIAN |\
  83         HRCWH_LALE_NORMAL)
  84 #endif
  85
  86 /*
  87  * System IO Config
  88  */
  89 #define CFG_SICRL               0x00000000
  90
  91 #define CONFIG_BOARD_EARLY_INIT_F       /* call board_pre_init */
  92 #define CONFIG_BOARD_EARLY_INIT_R
  93
  94 /*
  95  * IMMR new address
  96  */
  97 #define CFG_IMMR                0xE0000000
  98
  99 /*
 100  * DDR Setup
 101  */
 102 #define CFG_DDR_BASE            0x00000000      /* DDR is system memory */
 103 #define CFG_SDRAM_BASE          CFG_DDR_BASE
 104 #define CFG_DDR_SDRAM_BASE      CFG_DDR_BASE
 105 #define CFG_DDRCDR              0x73000002      /* DDR II voltage is 1.8V */
 106
 107 #undef CONFIG_SPD_EEPROM
 108 #if defined(CONFIG_SPD_EEPROM)
 109 /* Determine DDR configuration from I2C interface
 110  */
 111 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
 112 #else
 113 /* Manually set up DDR parameters
 114  */
 115 #define CFG_DDR_SIZE            128     /* MB */
 116 #define CFG_DDR_CS0_CONFIG      0x80840102
 117 #define CFG_DDR_TIMING_0        0x00220802
 118 #define CFG_DDR_TIMING_1        0x3935d322
 119 #define CFG_DDR_TIMING_2        0x0f9048ca
 120 #define CFG_DDR_TIMING_3        0x00000000
 121 #define CFG_DDR_CLK_CNTL        0x02000000
 122 #define CFG_DDR_MODE            0x44400232
 123 #define CFG_DDR_MODE2           0x8000c000
 124 #define CFG_DDR_INTERVAL        0x03200064
 125 #define CFG_DDR_CS0_BNDS        0x00000007
 126 #define CFG_DDR_SDRAM_CFG       0x43080000
 127 #define CFG_DDR_SDRAM_CFG2      0x00401000
 128 #endif
 129
 130 /*
 131  * Memory test
 132  */
 133 #undef CFG_DRAM_TEST            /* memory test, takes time */
 134 #define CFG_MEMTEST_START       0x00000000      /* memtest region */
 135 #define CFG_MEMTEST_END         0x00100000
 136
 137 /*
 138  * The reserved memory
 139  */
 140 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 141
 142 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 143 #define CFG_RAMBOOT
 144 #else
 145 #undef  CFG_RAMBOOT
 146 #endif
 147
 148 /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
 149 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 150 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 151
 152 /*
 153  * Initial RAM Base Address Setup
 154  */
 155 #define CFG_INIT_RAM_LOCK       1
 156 #define CFG_INIT_RAM_ADDR       0xE6000000      /* Initial RAM address */
 157 #define CFG_INIT_RAM_END        0x1000          /* End of used area in RAM */
 158 #define CFG_GBL_DATA_SIZE       0x100           /* num bytes initial data */
 159 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 160
 161 /*
 162  * Local Bus Configuration & Clock Setup
 163  */
 164 #define CFG_LCRR                (LCRR_DBYP | LCRR_CLKDIV_2)
 165 #define CFG_LBC_LBCR            0x00000000
 166
 167 /*
 168  * FLASH on the Local Bus
 169  */
 170 #define CFG_FLASH_CFI           /* use the Common Flash Interface */
 171 #define CFG_FLASH_CFI_DRIVER    /* use the CFI driver */
 172 #define CFG_FLASH_BASE          0xFE000000      /* FLASH base address */
 173 #define CFG_FLASH_SIZE          16      /* FLASH size is 16M */
 174
 175 #define CFG_LBLAWBAR0_PRELIM    CFG_FLASH_BASE  /* Window base at flash base */
 176 #define CFG_LBLAWAR0_PRELIM     0x80000018      /* 32MB window size */
 177
 178 #define CFG_BR0_PRELIM  (CFG_FLASH_BASE |       /* Flash Base address */ \
 179                         (2 << BR_PS_SHIFT) |    /* 16 bit port size */ \
 180                         BR_V)                   /* valid */
 181 #define CFG_OR0_PRELIM          0xfe006ff7      /* 16MB Flash size */
 182
 183 #define CFG_MAX_FLASH_BANKS     1               /* number of banks */
 184 #define CFG_MAX_FLASH_SECT      128             /* sectors per device */
 185
 186 #undef CFG_FLASH_CHECKSUM
 187
 188 /*
 189  * BCSR on the Local Bus
 190  */
 191 #define CFG_BCSR                0xF8000000
 192 #define CFG_LBLAWBAR1_PRELIM    CFG_BCSR        /* Access window base at BCSR base */
 193 #define CFG_LBLAWAR1_PRELIM     0x8000000E      /* Access window size 32K */
 194
 195 #define CFG_BR1_PRELIM          (CFG_BCSR|0x00000801)   /* Port size=8bit, MSEL=GPCM */
 196 #define CFG_OR1_PRELIM          0xFFFFE9f7      /* length 32K */
 197
 198 /*
 199  * SDRAM on the Local Bus
 200  */
 201 #undef CFG_LB_SDRAM             /* The board has not SRDAM on local bus */
 202
 203 #ifdef CFG_LB_SDRAM
 204 #define CFG_LBC_SDRAM_BASE      0xF0000000      /* SDRAM base address */
 205 #define CFG_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 64MB */
 206
 207 #define CFG_LBLAWBAR2_PRELIM    CFG_LBC_SDRAM_BASE
 208 #define CFG_LBLAWAR2_PRELIM     0x80000019      /* 64MB */
 209
 210 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
 211 /*
 212  * Base Register 2 and Option Register 2 configure SDRAM.
 213  * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 214  *
 215  * For BR2, need:
 216  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 217  *    port size = 32-bits = BR2[19:20] = 11
 218  *    no parity checking = BR2[21:22] = 00
 219  *    SDRAM for MSEL = BR2[24:26] = 011
 220  *    Valid = BR[31] = 1
 221  *
 222  * 0    4    8    12   16   20   24   28
 223  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 224  *
 225  * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 226  * the top 17 bits of BR2.
 227  */
 228
 229 #define CFG_BR2_PRELIM  0xf0001861      /*Port size=32bit, MSEL=SDRAM */
 230
 231 /*
 232  * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 233  *
 234  * For OR2, need:
 235  *    64MB mask for AM, OR2[0:7] = 1111 1100
 236  *                 XAM, OR2[17:18] = 11
 237  *    9 columns OR2[19-21] = 010
 238  *    13 rows   OR2[23-25] = 100
 239  *    EAD set for extra time OR[31] = 1
 240  *
 241  * 0    4    8    12   16   20   24   28
 242  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 243  */
 244
 245 #define CFG_OR2_PRELIM  0xfc006901
 246
 247 #define CFG_LBC_LSRT    0x32000000      /* LB sdram refresh timer, about 6us */
 248 #define CFG_LBC_MRTPR   0x20000000      /* LB refresh timer prescal, 266MHz/32 */
 249
 250 /*
 251  * LSDMR masks
 252  */
 253 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
 254 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
 255 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
 256 #define CFG_LBC_LSDMR_OP_MRW    (3 << (31 - 4))
 257 #define CFG_LBC_LSDMR_OP_PRECH  (4 << (31 - 4))
 258 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
 259 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
 260 #define CFG_LBC_LSDMR_OP_RWINV  (7 << (31 - 4))
 261
 262 #define CFG_LBC_LSDMR_COMMON    0x0063b723
 263
 264 /*
 265  * SDRAM Controller configuration sequence.
 266  */
 267 #define CFG_LBC_LSDMR_1         ( CFG_LBC_LSDMR_COMMON \
 268                                 | CFG_LBC_LSDMR_OP_PCHALL)
 269 #define CFG_LBC_LSDMR_2         ( CFG_LBC_LSDMR_COMMON \
 270                                 | CFG_LBC_LSDMR_OP_ARFRSH)
 271 #define CFG_LBC_LSDMR_3         ( CFG_LBC_LSDMR_COMMON \
 272                                 | CFG_LBC_LSDMR_OP_ARFRSH)
 273 #define CFG_LBC_LSDMR_4         ( CFG_LBC_LSDMR_COMMON \
 274                                 | CFG_LBC_LSDMR_OP_MRW)
 275 #define CFG_LBC_LSDMR_5         ( CFG_LBC_LSDMR_COMMON \
 276                                 | CFG_LBC_LSDMR_OP_NORMAL)
 277
 278 #endif
 279
 280 /*
 281  * Windows to access PIB via local bus
 282  */
 283 #define CFG_LBLAWBAR3_PRELIM    0xf8008000      /* windows base 0xf8008000 */
 284 #define CFG_LBLAWAR3_PRELIM     0x8000000f      /* windows size 64KB */
 285
 286 /*
 287  * CS2 on Local Bus, to PIB
 288  */
 289 #define CFG_BR2_PRELIM  0xf8008801      /* CS2 base address at 0xf8008000 */
 290 #define CFG_OR2_PRELIM  0xffffe9f7      /* size 32KB, port size 8bit, GPCM */
 291
 292 /*
 293  * CS3 on Local Bus, to PIB
 294  */
 295 #define CFG_BR3_PRELIM  0xf8010801      /* CS3 base address at 0xf8010000 */
 296 #define CFG_OR3_PRELIM  0xffffe9f7      /* size 32KB, port size 8bit, GPCM */
 297
 298 /*
 299  * Serial Port
 300  */
 301 #define CONFIG_CONS_INDEX       1
 302 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 303 #define CFG_NS16550
 304 #define CFG_NS16550_SERIAL
 305 #define CFG_NS16550_REG_SIZE    1
 306 #define CFG_NS16550_CLK         get_bus_freq(0)
 307
 308 #define CFG_BAUDRATE_TABLE  \
 309         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 310
 311 #define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
 312 #define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
 313
 314 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 315 /* Use the HUSH parser */
 316 #define CFG_HUSH_PARSER
 317 #ifdef CFG_HUSH_PARSER
 318 #define CFG_PROMPT_HUSH_PS2 "> "
 319 #endif
 320
 321 /* pass open firmware flat tree */
 322 #define CONFIG_OF_LIBFDT        1
 323 #define CONFIG_OF_BOARD_SETUP   1
 324 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 325
 326 /* I2C */
 327 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 328 #undef CONFIG_SOFT_I2C          /* I2C bit-banged */
 329 #define CONFIG_FSL_I2C
 330 #define CFG_I2C_SPEED   400000  /* I2C speed and slave address */
 331 #define CFG_I2C_SLAVE   0x7F
 332 #define CFG_I2C_NOPROBES        {0x51}  /* Don't probe these addrs */
 333 #define CFG_I2C_OFFSET  0x3000
 334
 335 /*
 336  * Config on-board RTC
 337  */
 338 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 339 #define CFG_I2C_RTC_ADDR        0x68    /* at address 0x68 */
 340
 341 /*
 342  * General PCI
 343  * Addresses are mapped 1-1.
 344  */
 345 #define CFG_PCI_MEM_BASE        0x80000000
 346 #define CFG_PCI_MEM_PHYS        CFG_PCI_MEM_BASE
 347 #define CFG_PCI_MEM_SIZE        0x10000000      /* 256M */
 348 #define CFG_PCI_MMIO_BASE       0x90000000
 349 #define CFG_PCI_MMIO_PHYS       CFG_PCI_MMIO_BASE
 350 #define CFG_PCI_MMIO_SIZE       0x10000000      /* 256M */
 351 #define CFG_PCI_IO_BASE         0xE0300000
 352 #define CFG_PCI_IO_PHYS         0xE0300000
 353 #define CFG_PCI_IO_SIZE         0x100000        /* 1M */
 354
 355 #define CFG_PCI_SLV_MEM_LOCAL   CFG_SDRAM_BASE
 356 #define CFG_PCI_SLV_MEM_BUS     0x00000000
 357 #define CFG_PCI_SLV_MEM_SIZE    0x80000000
 358
 359
 360 #ifdef CONFIG_PCI
 361
 362 #define CONFIG_NET_MULTI
 363 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 364
 365 #undef CONFIG_EEPRO100
 366 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 367 #define CFG_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 368
 369 #endif  /* CONFIG_PCI */
 370
 371
 372 #ifndef CONFIG_NET_MULTI
 373 #define CONFIG_NET_MULTI        1
 374 #endif
 375
 376 /*
 377  * QE UEC ethernet configuration
 378  */
 379 #define CONFIG_UEC_ETH
 380 #define CONFIG_ETHPRIME         "Freescale GETH"
 381
 382 #define CONFIG_UEC_ETH1         /* ETH3 */
 383
 384 #ifdef CONFIG_UEC_ETH1
 385 #define CFG_UEC1_UCC_NUM        2       /* UCC3 */
 386 #define CFG_UEC1_RX_CLK         QE_CLK9
 387 #define CFG_UEC1_TX_CLK         QE_CLK10
 388 #define CFG_UEC1_ETH_TYPE       FAST_ETH
 389 #define CFG_UEC1_PHY_ADDR       3
 390 #define CFG_UEC1_INTERFACE_MODE ENET_100_MII
 391 #endif
 392
 393 #define CONFIG_UEC_ETH2         /* ETH4 */
 394
 395 #ifdef CONFIG_UEC_ETH2
 396 #define CFG_UEC2_UCC_NUM        3       /* UCC4 */
 397 #define CFG_UEC2_RX_CLK         QE_CLK7
 398 #define CFG_UEC2_TX_CLK         QE_CLK8
 399 #define CFG_UEC2_ETH_TYPE       FAST_ETH
 400 #define CFG_UEC2_PHY_ADDR       4
 401 #define CFG_UEC2_INTERFACE_MODE ENET_100_MII
 402 #endif
 403
 404 /*
 405  * Environment
 406  */
 407 #ifndef CFG_RAMBOOT
 408         #define CFG_ENV_IS_IN_FLASH     1
 409         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 410         #define CFG_ENV_SECT_SIZE       0x20000
 411         #define CFG_ENV_SIZE            0x2000
 412 #else
 413         #define CFG_NO_FLASH            1       /* Flash is not usable now */
 414         #define CFG_ENV_IS_NOWHERE      1       /* Store ENV in memory only */
 415         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - 0x1000)
 416         #define CFG_ENV_SIZE            0x2000
 417 #endif
 418
 419 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 420 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 421
 422 /*
 423  * BOOTP options
 424  */
 425 #define CONFIG_BOOTP_BOOTFILESIZE
 426 #define CONFIG_BOOTP_BOOTPATH
 427 #define CONFIG_BOOTP_GATEWAY
 428 #define CONFIG_BOOTP_HOSTNAME
 429
 430
 431 /*
 432  * Command line configuration.
 433  */
 434 #include <config_cmd_default.h>
 435
 436 #define CONFIG_CMD_PING
 437 #define CONFIG_CMD_I2C
 438 #define CONFIG_CMD_ASKENV
 439
 440 #if defined(CONFIG_PCI)
 441     #define CONFIG_CMD_PCI
 442 #endif
 443
 444 #if defined(CFG_RAMBOOT)
 445     #undef CONFIG_CMD_ENV
 446     #undef CONFIG_CMD_LOADS
 447 #endif
 448
 449
 450 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 451
 452 /*
 453  * Miscellaneous configurable options
 454  */
 455 #define CFG_LONGHELP            /* undef to save memory */
 456 #define CFG_LOAD_ADDR           0x2000000       /* default load address */
 457 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
 458
 459 #if defined(CONFIG_CMD_KGDB)
 460         #define CFG_CBSIZE      1024    /* Console I/O Buffer Size */
 461 #else
 462         #define CFG_CBSIZE      256     /* Console I/O Buffer Size */
 463 #endif
 464
 465 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 466 #define CFG_MAXARGS     16              /* max number of command args */
 467 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 468 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 469
 470 /*
 471  * For booting Linux, the board info and command line data
 472  * have to be in the first 8 MB of memory, since this is
 473  * the maximum mapped by the Linux kernel during initialization.
 474  */
 475 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 476
 477 /*
 478  * Core HID Setup
 479  */
 480 #define CFG_HID0_INIT           0x000000000
 481 #define CFG_HID0_FINAL          HID0_ENABLE_MACHINE_CHECK
 482 #define CFG_HID2                HID2_HBE
 483
 484 /*
 485  * Cache Config
 486  */
 487 #define CFG_DCACHE_SIZE         16384
 488 #define CFG_CACHELINE_SIZE      32
 489 #if defined(CONFIG_CMD_KGDB)
 490 #define CFG_CACHELINE_SHIFT     5       /*log base 2 of the above value */
 491 #endif
 492
 493 /*
 494  * MMU Setup
 495  */
 496
 497 /* DDR: cache cacheable */
 498 #define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 499 #define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 500 #define CFG_DBAT0L      CFG_IBAT0L
 501 #define CFG_DBAT0U      CFG_IBAT0U
 502
 503 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 504 #define CFG_IBAT1L      (CFG_IMMR | BATL_PP_10 | \
 505                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 506 #define CFG_IBAT1U      (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 507 #define CFG_DBAT1L      CFG_IBAT1L
 508 #define CFG_DBAT1U      CFG_IBAT1U
 509
 510 /* BCSR: cache-inhibit and guarded */
 511 #define CFG_IBAT2L      (CFG_BCSR | BATL_PP_10 | \
 512                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 513 #define CFG_IBAT2U      (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
 514 #define CFG_DBAT2L      CFG_IBAT2L
 515 #define CFG_DBAT2U      CFG_IBAT2U
 516
 517 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 518 #define CFG_IBAT3L      (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 519 #define CFG_IBAT3U      (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 520 #define CFG_DBAT3L      (CFG_FLASH_BASE | BATL_PP_10 | \
 521                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 522 #define CFG_DBAT3U      CFG_IBAT3U
 523
 524 #define CFG_IBAT4L      (0)
 525 #define CFG_IBAT4U      (0)
 526 #define CFG_DBAT4L      CFG_IBAT4L
 527 #define CFG_DBAT4U      CFG_IBAT4U
 528
 529 /* Stack in dcache: cacheable, no memory coherence */
 530 #define CFG_IBAT5L      (CFG_INIT_RAM_ADDR | BATL_PP_10)
 531 #define CFG_IBAT5U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 532 #define CFG_DBAT5L      CFG_IBAT5L
 533 #define CFG_DBAT5U      CFG_IBAT5U
 534
 535 #ifdef CONFIG_PCI
 536 /* PCI MEM space: cacheable */
 537 #define CFG_IBAT6L      (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 538 #define CFG_IBAT6U      (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 539 #define CFG_DBAT6L      CFG_IBAT6L
 540 #define CFG_DBAT6U      CFG_IBAT6U
 541 /* PCI MMIO space: cache-inhibit and guarded */
 542 #define CFG_IBAT7L      (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
 543                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 544 #define CFG_IBAT7U      (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 545 #define CFG_DBAT7L      CFG_IBAT7L
 546 #define CFG_DBAT7U      CFG_IBAT7U
 547 #else
 548 #define CFG_IBAT6L      (0)
 549 #define CFG_IBAT6U      (0)
 550 #define CFG_IBAT7L      (0)
 551 #define CFG_IBAT7U      (0)
 552 #define CFG_DBAT6L      CFG_IBAT6L
 553 #define CFG_DBAT6U      CFG_IBAT6U
 554 #define CFG_DBAT7L      CFG_IBAT7L
 555 #define CFG_DBAT7U      CFG_IBAT7U
 556 #endif
 557
 558 /*
 559  * Internal Definitions
 560  *
 561  * Boot Flags
 562  */
 563 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 564 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 565
 566 #if defined(CONFIG_CMD_KGDB)
 567 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 568 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 569 #endif
 570
 571 /*
 572  * Environment Configuration
 573  */
 574
 575 #define CONFIG_ENV_OVERWRITE
 576
 577 #if defined(CONFIG_UEC_ETH)
 578 #define CONFIG_ETHADDR  00:04:9f:ef:03:01
 579 #define CONFIG_HAS_ETH1
 580 #define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
 581 #endif
 582
 583 #define CONFIG_BAUDRATE 115200
 584
 585 #define CONFIG_LOADADDR 200000  /* default location for tftp and bootm */
 586
 587 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 588 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 589
 590 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 591    "netdev=eth0\0"                                                      \
 592    "consoledev=ttyS0\0"                                                 \
 593    "ramdiskaddr=1000000\0"                                              \
 594    "ramdiskfile=ramfs.83xx\0"                                           \
 595    "fdtaddr=400000\0"                                                   \
 596    "fdtfile=mpc832xemds.dtb\0"                                          \
 597    ""
 598
 599 #define CONFIG_NFSBOOTCOMMAND                                           \
 600    "setenv bootargs root=/dev/nfs rw "                                  \
 601       "nfsroot=$serverip:$rootpath "                                    \
 602       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 603       "console=$consoledev,$baudrate $othbootargs;"                     \
 604    "tftp $loadaddr $bootfile;"                                          \
 605    "tftp $fdtaddr $fdtfile;"                                            \
 606    "bootm $loadaddr - $fdtaddr"
 607
 608 #define CONFIG_RAMBOOTCOMMAND                                           \
 609    "setenv bootargs root=/dev/ram rw "                                  \
 610       "console=$consoledev,$baudrate $othbootargs;"                     \
 611    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 612    "tftp $loadaddr $bootfile;"                                          \
 613    "tftp $fdtaddr $fdtfile;"                                            \
 614    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 615
 616
 617 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 618
 619 #endif  /* __CONFIG_H */