include/configs/MPC832XEMDS.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 #undef DEBUG
  24
  25 /*
  26  * High Level Configuration Options
  27  */
  28 #define CONFIG_E300             1       /* E300 family */
  29 #define CONFIG_QE               1       /* Has QE */
  30 #define CONFIG_MPC83XX          1       /* MPC83xx family */
  31 #define CONFIG_MPC832X          1       /* MPC832x CPU specific */
  32 #define CONFIG_MPC832XEMDS      1       /* MPC832XEMDS board specific */
  33
  34 /*
  35  * System Clock Setup
  36  */
  37 #ifdef CONFIG_PCISLAVE
  38 #define CONFIG_83XX_PCICLK      66000000        /* in HZ */
  39 #else
  40 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  41 #endif
  42
  43 #ifndef CONFIG_SYS_CLK_FREQ
  44 #define CONFIG_SYS_CLK_FREQ     66000000
  45 #endif
  46
  47 /*
  48  * Hardware Reset Configuration Word
  49  */
  50 #define CFG_HRCW_LOW (\
  51         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  52         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  53         HRCWL_VCO_1X2 |\
  54         HRCWL_CSB_TO_CLKIN_2X1 |\
  55         HRCWL_CORE_TO_CSB_2X1 |\
  56         HRCWL_CE_PLL_VCO_DIV_2 |\
  57         HRCWL_CE_PLL_DIV_1X1 |\
  58         HRCWL_CE_TO_PLL_1X3)
  59
  60 #ifdef CONFIG_PCISLAVE
  61 #define CFG_HRCW_HIGH (\
  62         HRCWH_PCI_AGENT |\
  63         HRCWH_PCI1_ARBITER_DISABLE |\
  64         HRCWH_CORE_ENABLE |\
  65         HRCWH_FROM_0XFFF00100 |\
  66         HRCWH_BOOTSEQ_DISABLE |\
  67         HRCWH_SW_WATCHDOG_DISABLE |\
  68         HRCWH_ROM_LOC_LOCAL_16BIT |\
  69         HRCWH_BIG_ENDIAN |\
  70         HRCWH_LALE_NORMAL)
  71 #else
  72 #define CFG_HRCW_HIGH (\
  73         HRCWH_PCI_HOST |\
  74         HRCWH_PCI1_ARBITER_ENABLE |\
  75         HRCWH_CORE_ENABLE |\
  76         HRCWH_FROM_0X00000100 |\
  77         HRCWH_BOOTSEQ_DISABLE |\
  78         HRCWH_SW_WATCHDOG_DISABLE |\
  79         HRCWH_ROM_LOC_LOCAL_16BIT |\
  80         HRCWH_BIG_ENDIAN |\
  81         HRCWH_LALE_NORMAL)
  82 #endif
  83
  84 /*
  85  * System IO Config
  86  */
  87 #define CFG_SICRL               0x00000000
  88
  89 #define CONFIG_BOARD_EARLY_INIT_F       /* call board_pre_init */
  90
  91 /*
  92  * IMMR new address
  93  */
  94 #define CFG_IMMR                0xE0000000
  95
  96 /*
  97  * DDR Setup
  98  */
  99 #define CFG_DDR_BASE            0x00000000      /* DDR is system memory */
 100 #define CFG_SDRAM_BASE          CFG_DDR_BASE
 101 #define CFG_DDR_SDRAM_BASE      CFG_DDR_BASE
 102 #define CFG_DDRCDR              0x73000002      /* DDR II voltage is 1.8V */
 103
 104 #undef CONFIG_SPD_EEPROM
 105 #if defined(CONFIG_SPD_EEPROM)
 106 /* Determine DDR configuration from I2C interface
 107  */
 108 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
 109 #else
 110 /* Manually set up DDR parameters
 111  */
 112 #define CFG_DDR_SIZE            128     /* MB */
 113 #define CFG_DDR_CS0_CONFIG      0x80840102
 114 #define CFG_DDR_TIMING_0        0x00220802
 115 #define CFG_DDR_TIMING_1        0x3935d322
 116 #define CFG_DDR_TIMING_2        0x0f9048ca
 117 #define CFG_DDR_TIMING_3        0x00000000
 118 #define CFG_DDR_CLK_CNTL        0x02000000
 119 #define CFG_DDR_MODE            0x44400232
 120 #define CFG_DDR_MODE2           0x8000c000
 121 #define CFG_DDR_INTERVAL        0x03200064
 122 #define CFG_DDR_CS0_BNDS        0x00000007
 123 #define CFG_DDR_SDRAM_CFG       0x43080000
 124 #define CFG_DDR_SDRAM_CFG2      0x00401000
 125 #endif
 126
 127 /*
 128  * Memory test
 129  */
 130 #undef CFG_DRAM_TEST            /* memory test, takes time */
 131 #define CFG_MEMTEST_START       0x00000000      /* memtest region */
 132 #define CFG_MEMTEST_END         0x00100000
 133
 134 /*
 135  * The reserved memory
 136  */
 137 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 138
 139 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 140 #define CFG_RAMBOOT
 141 #else
 142 #undef  CFG_RAMBOOT
 143 #endif
 144
 145 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 146 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 147
 148 /*
 149  * Initial RAM Base Address Setup
 150  */
 151 #define CFG_INIT_RAM_LOCK       1
 152 #define CFG_INIT_RAM_ADDR       0xE6000000      /* Initial RAM address */
 153 #define CFG_INIT_RAM_END        0x1000          /* End of used area in RAM */
 154 #define CFG_GBL_DATA_SIZE       0x100           /* num bytes initial data */
 155 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 156
 157 /*
 158  * Local Bus Configuration & Clock Setup
 159  */
 160 #define CFG_LCRR                (LCRR_DBYP | LCRR_CLKDIV_2)
 161 #define CFG_LBC_LBCR            0x00000000
 162
 163 /*
 164  * FLASH on the Local Bus
 165  */
 166 #define CFG_FLASH_CFI           /* use the Common Flash Interface */
 167 #define CFG_FLASH_CFI_DRIVER    /* use the CFI driver */
 168 #define CFG_FLASH_BASE          0xFE000000      /* FLASH base address */
 169 #define CFG_FLASH_SIZE          16      /* FLASH size is 16M */
 170
 171 #define CFG_LBLAWBAR0_PRELIM    CFG_FLASH_BASE  /* Window base at flash base */
 172 #define CFG_LBLAWAR0_PRELIM     0x80000018      /* 32MB window size */
 173
 174 #define CFG_BR0_PRELIM  (CFG_FLASH_BASE |       /* Flash Base address */ \
 175                         (2 << BR_PS_SHIFT) |    /* 16 bit port size */ \
 176                         BR_V)                   /* valid */
 177 #define CFG_OR0_PRELIM          0xfe006ff7      /* 16MB Flash size */
 178
 179 #define CFG_MAX_FLASH_BANKS     1               /* number of banks */
 180 #define CFG_MAX_FLASH_SECT      128             /* sectors per device */
 181
 182 #undef CFG_FLASH_CHECKSUM
 183
 184 /*
 185  * BCSR on the Local Bus
 186  */
 187 #define CFG_BCSR                0xF8000000
 188 #define CFG_LBLAWBAR1_PRELIM    CFG_BCSR        /* Access window base at BCSR base */
 189 #define CFG_LBLAWAR1_PRELIM     0x8000000E      /* Access window size 32K */
 190
 191 #define CFG_BR1_PRELIM          (CFG_BCSR|0x00000801)   /* Port size=8bit, MSEL=GPCM */
 192 #define CFG_OR1_PRELIM          0xFFFFE9f7      /* length 32K */
 193
 194 /*
 195  * SDRAM on the Local Bus
 196  */
 197 #undef CFG_LB_SDRAM             /* The board has not SRDAM on local bus */
 198
 199 #ifdef CFG_LB_SDRAM
 200 #define CFG_LBC_SDRAM_BASE      0xF0000000      /* SDRAM base address */
 201 #define CFG_LBC_SDRAM_SIZE      64              /* LBC SDRAM is 64MB */
 202
 203 #define CFG_LBLAWBAR2_PRELIM    CFG_LBC_SDRAM_BASE
 204 #define CFG_LBLAWAR2_PRELIM     0x80000019      /* 64MB */
 205
 206 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
 207 /*
 208  * Base Register 2 and Option Register 2 configure SDRAM.
 209  * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 210  *
 211  * For BR2, need:
 212  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 213  *    port size = 32-bits = BR2[19:20] = 11
 214  *    no parity checking = BR2[21:22] = 00
 215  *    SDRAM for MSEL = BR2[24:26] = 011
 216  *    Valid = BR[31] = 1
 217  *
 218  * 0    4    8    12   16   20   24   28
 219  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 220  *
 221  * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 222  * the top 17 bits of BR2.
 223  */
 224
 225 #define CFG_BR2_PRELIM  0xf0001861      /*Port size=32bit, MSEL=SDRAM */
 226
 227 /*
 228  * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 229  *
 230  * For OR2, need:
 231  *    64MB mask for AM, OR2[0:7] = 1111 1100
 232  *                 XAM, OR2[17:18] = 11
 233  *    9 columns OR2[19-21] = 010
 234  *    13 rows   OR2[23-25] = 100
 235  *    EAD set for extra time OR[31] = 1
 236  *
 237  * 0    4    8    12   16   20   24   28
 238  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 239  */
 240
 241 #define CFG_OR2_PRELIM  0xfc006901
 242
 243 #define CFG_LBC_LSRT    0x32000000      /* LB sdram refresh timer, about 6us */
 244 #define CFG_LBC_MRTPR   0x20000000      /* LB refresh timer prescal, 266MHz/32 */
 245
 246 /*
 247  * LSDMR masks
 248  */
 249 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
 250 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
 251 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
 252 #define CFG_LBC_LSDMR_OP_MRW    (3 << (31 - 4))
 253 #define CFG_LBC_LSDMR_OP_PRECH  (4 << (31 - 4))
 254 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
 255 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
 256 #define CFG_LBC_LSDMR_OP_RWINV  (7 << (31 - 4))
 257
 258 #define CFG_LBC_LSDMR_COMMON    0x0063b723
 259
 260 /*
 261  * SDRAM Controller configuration sequence.
 262  */
 263 #define CFG_LBC_LSDMR_1         ( CFG_LBC_LSDMR_COMMON \
 264                                 | CFG_LBC_LSDMR_OP_PCHALL)
 265 #define CFG_LBC_LSDMR_2         ( CFG_LBC_LSDMR_COMMON \
 266                                 | CFG_LBC_LSDMR_OP_ARFRSH)
 267 #define CFG_LBC_LSDMR_3         ( CFG_LBC_LSDMR_COMMON \
 268                                 | CFG_LBC_LSDMR_OP_ARFRSH)
 269 #define CFG_LBC_LSDMR_4         ( CFG_LBC_LSDMR_COMMON \
 270                                 | CFG_LBC_LSDMR_OP_MRW)
 271 #define CFG_LBC_LSDMR_5         ( CFG_LBC_LSDMR_COMMON \
 272                                 | CFG_LBC_LSDMR_OP_NORMAL)
 273
 274 #endif
 275
 276 /*
 277  * Windows to access PIB via local bus
 278  */
 279 #define CFG_LBLAWBAR3_PRELIM    0xf8008000      /* windows base 0xf8008000 */
 280 #define CFG_LBLAWAR3_PRELIM     0x8000000f      /* windows size 64KB */
 281
 282 /*
 283  * CS2 on Local Bus, to PIB
 284  */
 285 #define CFG_BR2_PRELIM  0xf8008801      /* CS2 base address at 0xf8008000 */
 286 #define CFG_OR2_PRELIM  0xffffe9f7      /* size 32KB, port size 8bit, GPCM */
 287
 288 /*
 289  * CS3 on Local Bus, to PIB
 290  */
 291 #define CFG_BR3_PRELIM  0xf8010801      /* CS3 base address at 0xf8010000 */
 292 #define CFG_OR3_PRELIM  0xffffe9f7      /* size 32KB, port size 8bit, GPCM */
 293
 294 /*
 295  * Serial Port
 296  */
 297 #define CONFIG_CONS_INDEX       1
 298 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 299 #define CFG_NS16550
 300 #define CFG_NS16550_SERIAL
 301 #define CFG_NS16550_REG_SIZE    1
 302 #define CFG_NS16550_CLK         get_bus_freq(0)
 303
 304 #define CFG_BAUDRATE_TABLE  \
 305         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 306
 307 #define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
 308 #define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
 309
 310 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 311 /* Use the HUSH parser */
 312 #define CFG_HUSH_PARSER
 313 #ifdef CFG_HUSH_PARSER
 314 #define CFG_PROMPT_HUSH_PS2 "> "
 315 #endif
 316
 317 /* pass open firmware flat tree */
 318 #define CONFIG_OF_FLAT_TREE     1
 319 #define CONFIG_OF_BOARD_SETUP   1
 320
 321 /* maximum size of the flat tree (8K) */
 322 #define OF_FLAT_TREE_MAX_SIZE   8192
 323
 324 #define OF_CPU                  "PowerPC,8323@0"
 325 #define OF_SOC                  "soc8323@e0000000"
 326 #define OF_QE                   "qe@e0100000"
 327 #define OF_TBCLK                (bd->bi_busfreq / 4)
 328 #define OF_STDOUT_PATH          "/soc8323@e0000000/serial@4500"
 329
 330 /* I2C */
 331 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 332 #undef CONFIG_SOFT_I2C          /* I2C bit-banged */
 333 #define CONFIG_FSL_I2C
 334 #define CFG_I2C_SPEED   400000  /* I2C speed and slave address */
 335 #define CFG_I2C_SLAVE   0x7F
 336 #define CFG_I2C_NOPROBES        {0x51}  /* Don't probe these addrs */
 337 #define CFG_I2C_OFFSET  0x3000
 338
 339 /*
 340  * Config on-board RTC
 341  */
 342 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 343 #define CFG_I2C_RTC_ADDR        0x68    /* at address 0x68 */
 344
 345 /*
 346  * General PCI
 347  * Addresses are mapped 1-1.
 348  */
 349 #define CFG_PCI_MEM_BASE        0x80000000
 350 #define CFG_PCI_MEM_PHYS        CFG_PCI_MEM_BASE
 351 #define CFG_PCI_MEM_SIZE        0x10000000      /* 256M */
 352 #define CFG_PCI_MMIO_BASE       0x90000000
 353 #define CFG_PCI_MMIO_PHYS       CFG_PCI_MMIO_BASE
 354 #define CFG_PCI_MMIO_SIZE       0x10000000      /* 256M */
 355 #define CFG_PCI_IO_BASE         0xE0300000
 356 #define CFG_PCI_IO_PHYS         0xE0300000
 357 #define CFG_PCI_IO_SIZE         0x100000        /* 1M */
 358
 359 #define CFG_PCI_SLV_MEM_LOCAL   CFG_SDRAM_BASE
 360 #define CFG_PCI_SLV_MEM_BUS     0x00000000
 361 #define CFG_PCI_SLV_MEM_SIZE    0x80000000
 362
 363
 364 #ifdef CONFIG_PCI
 365
 366 #define CONFIG_NET_MULTI
 367 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 368
 369 #undef CONFIG_EEPRO100
 370 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 371 #define CFG_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 372
 373 #endif  /* CONFIG_PCI */
 374
 375
 376 #ifndef CONFIG_NET_MULTI
 377 #define CONFIG_NET_MULTI        1
 378 #endif
 379
 380 /*
 381  * QE UEC ethernet configuration
 382  */
 383 #define CONFIG_UEC_ETH
 384 #define CONFIG_ETHPRIME         "Freescale GETH"
 385
 386 #define CONFIG_UEC_ETH1         /* ETH3 */
 387
 388 #ifdef CONFIG_UEC_ETH1
 389 #define CFG_UEC1_UCC_NUM        2       /* UCC3 */
 390 #define CFG_UEC1_RX_CLK         QE_CLK9
 391 #define CFG_UEC1_TX_CLK         QE_CLK10
 392 #define CFG_UEC1_ETH_TYPE       FAST_ETH
 393 #define CFG_UEC1_PHY_ADDR       3
 394 #define CFG_UEC1_INTERFACE_MODE ENET_100_MII
 395 #endif
 396
 397 #define CONFIG_UEC_ETH2         /* ETH4 */
 398
 399 #ifdef CONFIG_UEC_ETH2
 400 #define CFG_UEC2_UCC_NUM        3       /* UCC4 */
 401 #define CFG_UEC2_RX_CLK         QE_CLK7
 402 #define CFG_UEC2_TX_CLK         QE_CLK8
 403 #define CFG_UEC2_ETH_TYPE       FAST_ETH
 404 #define CFG_UEC2_PHY_ADDR       4
 405 #define CFG_UEC2_INTERFACE_MODE ENET_100_MII
 406 #endif
 407
 408 /*
 409  * Environment
 410  */
 411 #ifndef CFG_RAMBOOT
 412         #define CFG_ENV_IS_IN_FLASH     1
 413         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + 0x40000)
 414         #define CFG_ENV_SECT_SIZE       0x40000 /* 256K(one sector) for env */
 415         #define CFG_ENV_SIZE            0x2000
 416 #else
 417         #define CFG_NO_FLASH            1       /* Flash is not usable now */
 418         #define CFG_ENV_IS_NOWHERE      1       /* Store ENV in memory only */
 419         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - 0x1000)
 420         #define CFG_ENV_SIZE            0x2000
 421 #endif
 422
 423 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 424 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 425
 426 /*
 427  * BOOTP options
 428  */
 429 #define CONFIG_BOOTP_BOOTFILESIZE
 430 #define CONFIG_BOOTP_BOOTPATH
 431 #define CONFIG_BOOTP_GATEWAY
 432 #define CONFIG_BOOTP_HOSTNAME
 433
 434
 435 /*
 436  * Command line configuration.
 437  */
 438 #include <config_cmd_default.h>
 439
 440 #define CONFIG_CMD_PING
 441 #define CONFIG_CMD_I2C
 442 #define CONFIG_CMD_ASKENV
 443
 444 #if defined(CONFIG_PCI)
 445     #define CONFIG_CMD_PCI
 446 #endif
 447
 448 #if defined(CFG_RAMBOOT)
 449     #undef CONFIG_CMD_ENV
 450     #undef CONFIG_CMD_LOADS
 451 #endif
 452
 453
 454 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 455
 456 /*
 457  * Miscellaneous configurable options
 458  */
 459 #define CFG_LONGHELP            /* undef to save memory */
 460 #define CFG_LOAD_ADDR           0x2000000       /* default load address */
 461 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
 462
 463 #if defined(CONFIG_CMD_KGDB)
 464         #define CFG_CBSIZE      1024    /* Console I/O Buffer Size */
 465 #else
 466         #define CFG_CBSIZE      256     /* Console I/O Buffer Size */
 467 #endif
 468
 469 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 470 #define CFG_MAXARGS     16              /* max number of command args */
 471 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 472 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 473
 474 /*
 475  * For booting Linux, the board info and command line data
 476  * have to be in the first 8 MB of memory, since this is
 477  * the maximum mapped by the Linux kernel during initialization.
 478  */
 479 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 480
 481 /*
 482  * Core HID Setup
 483  */
 484 #define CFG_HID0_INIT           0x000000000
 485 #define CFG_HID0_FINAL          HID0_ENABLE_MACHINE_CHECK
 486 #define CFG_HID2                HID2_HBE
 487
 488 /*
 489  * Cache Config
 490  */
 491 #define CFG_DCACHE_SIZE         16384
 492 #define CFG_CACHELINE_SIZE      32
 493 #if defined(CONFIG_CMD_KGDB)
 494 #define CFG_CACHELINE_SHIFT     5       /*log base 2 of the above value */
 495 #endif
 496
 497 /*
 498  * MMU Setup
 499  */
 500
 501 /* DDR: cache cacheable */
 502 #define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 503 #define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 504 #define CFG_DBAT0L      CFG_IBAT0L
 505 #define CFG_DBAT0U      CFG_IBAT0U
 506
 507 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 508 #define CFG_IBAT1L      (CFG_IMMR | BATL_PP_10 | \
 509                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 510 #define CFG_IBAT1U      (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 511 #define CFG_DBAT1L      CFG_IBAT1L
 512 #define CFG_DBAT1U      CFG_IBAT1U
 513
 514 /* BCSR: cache-inhibit and guarded */
 515 #define CFG_IBAT2L      (CFG_BCSR | BATL_PP_10 | \
 516                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 517 #define CFG_IBAT2U      (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
 518 #define CFG_DBAT2L      CFG_IBAT2L
 519 #define CFG_DBAT2U      CFG_IBAT2U
 520
 521 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 522 #define CFG_IBAT3L      (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 523 #define CFG_IBAT3U      (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 524 #define CFG_DBAT3L      (CFG_FLASH_BASE | BATL_PP_10 | \
 525                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 526 #define CFG_DBAT3U      CFG_IBAT3U
 527
 528 #define CFG_IBAT4L      (0)
 529 #define CFG_IBAT4U      (0)
 530 #define CFG_DBAT4L      CFG_IBAT4L
 531 #define CFG_DBAT4U      CFG_IBAT4U
 532
 533 /* Stack in dcache: cacheable, no memory coherence */
 534 #define CFG_IBAT5L      (CFG_INIT_RAM_ADDR | BATL_PP_10)
 535 #define CFG_IBAT5U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 536 #define CFG_DBAT5L      CFG_IBAT5L
 537 #define CFG_DBAT5U      CFG_IBAT5U
 538
 539 #ifdef CONFIG_PCI
 540 /* PCI MEM space: cacheable */
 541 #define CFG_IBAT6L      (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 542 #define CFG_IBAT6U      (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 543 #define CFG_DBAT6L      CFG_IBAT6L
 544 #define CFG_DBAT6U      CFG_IBAT6U
 545 /* PCI MMIO space: cache-inhibit and guarded */
 546 #define CFG_IBAT7L      (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
 547                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 548 #define CFG_IBAT7U      (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 549 #define CFG_DBAT7L      CFG_IBAT7L
 550 #define CFG_DBAT7U      CFG_IBAT7U
 551 #else
 552 #define CFG_IBAT6L      (0)
 553 #define CFG_IBAT6U      (0)
 554 #define CFG_IBAT7L      (0)
 555 #define CFG_IBAT7U      (0)
 556 #define CFG_DBAT6L      CFG_IBAT6L
 557 #define CFG_DBAT6U      CFG_IBAT6U
 558 #define CFG_DBAT7L      CFG_IBAT7L
 559 #define CFG_DBAT7U      CFG_IBAT7U
 560 #endif
 561
 562 /*
 563  * Internal Definitions
 564  *
 565  * Boot Flags
 566  */
 567 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 568 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 569
 570 #if defined(CONFIG_CMD_KGDB)
 571 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 572 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 573 #endif
 574
 575 /*
 576  * Environment Configuration
 577  */
 578
 579 #define CONFIG_ENV_OVERWRITE
 580
 581 #if defined(CONFIG_UEC_ETH)
 582 #define CONFIG_ETHADDR  00:04:9f:ef:03:01
 583 #define CONFIG_HAS_ETH1
 584 #define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
 585 #endif
 586
 587 #define CONFIG_BAUDRATE 115200
 588
 589 #define CONFIG_LOADADDR 200000  /* default location for tftp and bootm */
 590
 591 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 592 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 593
 594 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 595    "netdev=eth0\0"                                                      \
 596    "consoledev=ttyS0\0"                                                 \
 597    "ramdiskaddr=1000000\0"                                              \
 598    "ramdiskfile=ramfs.83xx\0"                                           \
 599    "fdtaddr=400000\0"                                                   \
 600    "fdtfile=mpc832xemds.dtb\0"                                          \
 601    ""
 602
 603 #define CONFIG_NFSBOOTCOMMAND                                           \
 604    "setenv bootargs root=/dev/nfs rw "                                  \
 605       "nfsroot=$serverip:$rootpath "                                    \
 606       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 607       "console=$consoledev,$baudrate $othbootargs;"                     \
 608    "tftp $loadaddr $bootfile;"                                          \
 609    "tftp $fdtaddr $fdtfile;"                                            \
 610    "bootm $loadaddr - $fdtaddr"
 611
 612 #define CONFIG_RAMBOOTCOMMAND                                           \
 613    "setenv bootargs root=/dev/ram rw "                                  \
 614       "console=$consoledev,$baudrate $othbootargs;"                     \
 615    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 616    "tftp $loadaddr $bootfile;"                                          \
 617    "tftp $fdtaddr $fdtfile;"                                            \
 618    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 619
 620
 621 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 622
 623 #endif  /* __CONFIG_H */