include/configs/MPC8360EMDS.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 /*
  26  * High Level Configuration Options
  27  */
  28 #define CONFIG_E300             1 /* E300 family */
  29 #define CONFIG_QE               1 /* Has QE */
  30 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  31 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  32 #define CONFIG_MPC8360EMDS      1 /* MPC8360EMDS board specific */
  33 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
  34 #undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
  35
  36 /*
  37  * System Clock Setup
  38  */
  39 #ifdef CONFIG_PCISLAVE
  40 #define CONFIG_83XX_PCICLK      66000000 /* in HZ */
  41 #else
  42 #define CONFIG_83XX_CLKIN       66000000 /* in Hz */
  43 #endif
  44
  45 #ifndef CONFIG_SYS_CLK_FREQ
  46 #define CONFIG_SYS_CLK_FREQ     66000000
  47 #endif
  48
  49 /*
  50  * Hardware Reset Configuration Word
  51  */
  52 #define CONFIG_SYS_HRCW_LOW (\
  53         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  54         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  55         HRCWL_CSB_TO_CLKIN_4X1 |\
  56         HRCWL_VCO_1X2 |\
  57         HRCWL_CE_PLL_VCO_DIV_4 |\
  58         HRCWL_CE_PLL_DIV_1X1 |\
  59         HRCWL_CE_TO_PLL_1X6 |\
  60         HRCWL_CORE_TO_CSB_2X1)
  61
  62 #ifdef CONFIG_PCISLAVE
  63 #define CONFIG_SYS_HRCW_HIGH (\
  64         HRCWH_PCI_AGENT |\
  65         HRCWH_PCI1_ARBITER_DISABLE |\
  66         HRCWH_PCICKDRV_DISABLE |\
  67         HRCWH_CORE_ENABLE |\
  68         HRCWH_FROM_0XFFF00100 |\
  69         HRCWH_BOOTSEQ_DISABLE |\
  70         HRCWH_SW_WATCHDOG_DISABLE |\
  71         HRCWH_ROM_LOC_LOCAL_16BIT)
  72 #else
  73 #define CONFIG_SYS_HRCW_HIGH (\
  74         HRCWH_PCI_HOST |\
  75         HRCWH_PCI1_ARBITER_ENABLE |\
  76         HRCWH_PCICKDRV_ENABLE |\
  77         HRCWH_CORE_ENABLE |\
  78         HRCWH_FROM_0X00000100 |\
  79         HRCWH_BOOTSEQ_DISABLE |\
  80         HRCWH_SW_WATCHDOG_DISABLE |\
  81         HRCWH_ROM_LOC_LOCAL_16BIT)
  82 #endif
  83
  84 /*
  85  * System IO Config
  86  */
  87 #define CONFIG_SYS_SICRH                0x00000000
  88 #define CONFIG_SYS_SICRL                0x40000000
  89
  90 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
  91 #define CONFIG_BOARD_EARLY_INIT_R
  92
  93 /*
  94  * IMMR new address
  95  */
  96 #define CONFIG_SYS_IMMR         0xE0000000
  97
  98 /*
  99  * DDR Setup
 100  */
 101 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 102 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 103 #define CONFIG_SYS_SDRAM_BASE2          (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* + 256M */
 104 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 105 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
 106                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 107
 108 #define CONFIG_SYS_83XX_DDR_USES_CS0
 109
 110 #define CONFIG_DDR_ECC          /* support DDR ECC function */
 111 #define CONFIG_DDR_ECC_CMD      /* Use DDR ECC user commands */
 112
 113 /*
 114  * DDRCDR - DDR Control Driver Register
 115  */
 116 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
 117
 118 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
 119 #if defined(CONFIG_SPD_EEPROM)
 120 /*
 121  * Determine DDR configuration from I2C interface.
 122  */
 123 #define SPD_EEPROM_ADDRESS      0x52 /* DDR SODIMM */
 124 #else
 125 /*
 126  * Manually set up DDR parameters
 127  */
 128 #define CONFIG_SYS_DDR_SIZE             256 /* MB */
 129 #if defined(CONFIG_DDR_II)
 130 #define CONFIG_SYS_DDRCDR               0x80080001
 131 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
 132 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80330102
 133 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
 134 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
 135 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
 136 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 137 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
 138 #define CONFIG_SYS_DDR_MODE             0x47d00432
 139 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 140 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
 141 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 142 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 143 #else
 144 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
 145 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
 146 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
 147 #define CONFIG_SYS_DDR_CONTROL          0x42008000 /* Self refresh,2T timing */
 148 #define CONFIG_SYS_DDR_MODE             0x20000162 /* DLL,normal,seq,4/2.5 */
 149 #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
 150 #endif
 151 #endif
 152
 153 /*
 154  * Memory test
 155  */
 156 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 157 #define CONFIG_SYS_MEMTEST_START        0x00000000 /* memtest region */
 158 #define CONFIG_SYS_MEMTEST_END          0x00100000
 159
 160 /*
 161  * The reserved memory
 162  */
 163
 164 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
 165
 166 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 167 #define CONFIG_SYS_RAMBOOT
 168 #else
 169 #undef  CONFIG_SYS_RAMBOOT
 170 #endif
 171
 172 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 173 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024) /* Reserve 384 kB for Mon */
 174 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024) /* Reserved for malloc */
 175
 176 /*
 177  * Initial RAM Base Address Setup
 178  */
 179 #define CONFIG_SYS_INIT_RAM_LOCK        1
 180 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 181 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
 182 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 183 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 184
 185 /*
 186  * Local Bus Configuration & Clock Setup
 187  */
 188 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 189 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 190 #define CONFIG_SYS_LBC_LBCR             0x00000000
 191
 192 /*
 193  * FLASH on the Local Bus
 194  */
 195 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 196 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 197 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 198 #define CONFIG_SYS_FLASH_SIZE           32 /* max FLASH size is 32M */
 199 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use h/w Flash protection. */
 200 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 201
 202 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 203 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018 /* 32MB window size */
 204
 205 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
 206                         (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 207                         BR_V)   /* valid */
 208 #define CONFIG_SYS_OR0_PRELIM           ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
 209                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
 210                                 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 211
 212 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 213 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 214
 215 #undef  CONFIG_SYS_FLASH_CHECKSUM
 216
 217 /*
 218  * BCSR on the Local Bus
 219  */
 220 #define CONFIG_SYS_BCSR         0xF8000000
 221 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR /* Access window base at BCSR base */
 222 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000F /* Access window size 64K */
 223
 224 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
 225 #define CONFIG_SYS_OR1_PRELIM           0xFFFFE9f7 /* length 32K */
 226
 227 /*
 228  * SDRAM on the Local Bus
 229  */
 230 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* SDRAM base address */
 231 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 232
 233 #define CONFIG_SYS_LB_SDRAM             /* if board has SRDAM on local bus */
 234
 235 #ifdef CONFIG_SYS_LB_SDRAM
 236 #define CONFIG_SYS_LBLAWBAR2            0
 237 #define CONFIG_SYS_LBLAWAR2             0x80000019 /* 64MB */
 238
 239 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
 240 /*
 241  * Base Register 2 and Option Register 2 configure SDRAM.
 242  *
 243  * For BR2, need:
 244  *    Base address = BR[0:16] = dynamic
 245  *    port size = 32-bits = BR2[19:20] = 11
 246  *    no parity checking = BR2[21:22] = 00
 247  *    SDRAM for MSEL = BR2[24:26] = 011
 248  *    Valid = BR[31] = 1
 249  *
 250  * 0    4    8    12   16   20   24   28
 251  * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
 252  */
 253
 254 #define CONFIG_SYS_BR2          0x00001861 /*Port size=32bit, MSEL=SDRAM */
 255
 256 /*
 257  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 258  *
 259  * For OR2, need:
 260  *    64MB mask for AM, OR2[0:7] = 1111 1100
 261  *                 XAM, OR2[17:18] = 11
 262  *    9 columns OR2[19-21] = 010
 263  *    13 rows   OR2[23-25] = 100
 264  *    EAD set for extra time OR[31] = 1
 265  *
 266  * 0    4    8    12   16   20   24   28
 267  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 268  */
 269
 270 #define CONFIG_SYS_OR2          0xfc006901
 271
 272 #define CONFIG_SYS_LBC_LSRT     0x32000000 /* LB sdram refresh timer, about 6us */
 273 #define CONFIG_SYS_LBC_MRTPR    0x20000000 /* LB refresh timer prescal, 266MHz/32 */
 274
 275 #define CONFIG_SYS_LBC_LSDMR_COMMON     0x0063b723
 276
 277 /*
 278  * SDRAM Controller configuration sequence.
 279  */
 280 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 281 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 282 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 283 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 284 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 285
 286 #endif
 287
 288 /*
 289  * Windows to access PIB via local bus
 290  */
 291 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0xf8010000 /* windows base 0xf8010000 */
 292 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000e /* windows size 32KB */
 293
 294 /*
 295  * CS4 on Local Bus, to PIB
 296  */
 297 #define CONFIG_SYS_BR4_PRELIM   0xf8010801 /* CS4 base address at 0xf8010000 */
 298 #define CONFIG_SYS_OR4_PRELIM   0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
 299
 300 /*
 301  * CS5 on Local Bus, to PIB
 302  */
 303 #define CONFIG_SYS_BR5_PRELIM   0xf8008801 /* CS5 base address at 0xf8008000 */
 304 #define CONFIG_SYS_OR5_PRELIM   0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
 305
 306 /*
 307  * Serial Port
 308  */
 309 #define CONFIG_CONS_INDEX       1
 310 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 311 #define CONFIG_SYS_NS16550
 312 #define CONFIG_SYS_NS16550_SERIAL
 313 #define CONFIG_SYS_NS16550_REG_SIZE     1
 314 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 315
 316 #define CONFIG_SYS_BAUDRATE_TABLE  \
 317         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 318
 319 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 320 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 321
 322 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 323 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 324 /* Use the HUSH parser */
 325 #define CONFIG_SYS_HUSH_PARSER
 326 #ifdef  CONFIG_SYS_HUSH_PARSER
 327 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 328 #endif
 329
 330 /* pass open firmware flat tree */
 331 #define CONFIG_OF_LIBFDT        1
 332 #define CONFIG_OF_BOARD_SETUP   1
 333 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 334
 335 /* I2C */
 336 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 337 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 338 #define CONFIG_FSL_I2C
 339 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 340 #define CONFIG_SYS_I2C_SLAVE    0x7F
 341 #define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */
 342 #define CONFIG_SYS_I2C_OFFSET   0x3000
 343 #define CONFIG_SYS_I2C2_OFFSET 0x3100
 344
 345 /*
 346  * Config on-board RTC
 347  */
 348 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 349 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 350
 351 /*
 352  * General PCI
 353  * Addresses are mapped 1-1.
 354  */
 355 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 356 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 357 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000 /* 256M */
 358 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 359 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 360 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000 /* 256M */
 361 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 362 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 363 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000 /* 1M */
 364
 365 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 366 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 367 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 368
 369
 370 #ifdef CONFIG_PCI
 371
 372 #define CONFIG_NET_MULTI
 373 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 374 #define CONFIG_83XX_PCI_STREAMING
 375
 376 #undef CONFIG_EEPRO100
 377 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 378 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 379
 380 #endif  /* CONFIG_PCI */
 381
 382
 383 #ifndef CONFIG_NET_MULTI
 384 #define CONFIG_NET_MULTI        1
 385 #endif
 386
 387 #define CONFIG_HWCONFIG         1
 388
 389 /*
 390  * QE UEC ethernet configuration
 391  */
 392 #define CONFIG_UEC_ETH
 393 #define CONFIG_ETHPRIME         "FSL UEC0"
 394 #define CONFIG_PHY_MODE_NEED_CHANGE
 395
 396 #define CONFIG_UEC_ETH1         /* GETH1 */
 397
 398 #ifdef CONFIG_UEC_ETH1
 399 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 400 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE
 401 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK9
 402 #define CONFIG_SYS_UEC1_ETH_TYPE        GIGA_ETH
 403 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 404 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
 405 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 406 #endif
 407
 408 #define CONFIG_UEC_ETH2         /* GETH2 */
 409
 410 #ifdef CONFIG_UEC_ETH2
 411 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 412 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE
 413 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK4
 414 #define CONFIG_SYS_UEC2_ETH_TYPE        GIGA_ETH
 415 #define CONFIG_SYS_UEC2_PHY_ADDR        1
 416 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
 417 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 418 #endif
 419
 420 /*
 421  * Environment
 422  */
 423
 424 #ifndef CONFIG_SYS_RAMBOOT
 425         #define CONFIG_ENV_IS_IN_FLASH  1
 426         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 427         #define CONFIG_ENV_SECT_SIZE    0x20000
 428         #define CONFIG_ENV_SIZE         0x2000
 429 #else
 430         #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 431         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 432         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 433         #define CONFIG_ENV_SIZE         0x2000
 434 #endif
 435
 436 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 437 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 438
 439 /*
 440  * BOOTP options
 441  */
 442 #define CONFIG_BOOTP_BOOTFILESIZE
 443 #define CONFIG_BOOTP_BOOTPATH
 444 #define CONFIG_BOOTP_GATEWAY
 445 #define CONFIG_BOOTP_HOSTNAME
 446
 447
 448 /*
 449  * Command line configuration.
 450  */
 451 #include <config_cmd_default.h>
 452
 453 #define CONFIG_CMD_PING
 454 #define CONFIG_CMD_I2C
 455 #define CONFIG_CMD_ASKENV
 456 #define CONFIG_CMD_SDRAM
 457
 458 #if defined(CONFIG_PCI)
 459     #define CONFIG_CMD_PCI
 460 #endif
 461
 462 #if defined(CONFIG_SYS_RAMBOOT)
 463     #undef CONFIG_CMD_SAVEENV
 464     #undef CONFIG_CMD_LOADS
 465 #endif
 466
 467
 468 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 469
 470 /*
 471  * Miscellaneous configurable options
 472  */
 473 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 474 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 475 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 476
 477 #if defined(CONFIG_CMD_KGDB)
 478         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 479 #else
 480         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
 481 #endif
 482
 483 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 484 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 485 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 486 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 487
 488 /*
 489  * For booting Linux, the board info and command line data
 490  * have to be in the first 8 MB of memory, since this is
 491  * the maximum mapped by the Linux kernel during initialization.
 492  */
 493 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 494
 495 /*
 496  * Core HID Setup
 497  */
 498 #define CONFIG_SYS_HID0_INIT            0x000000000
 499 #define CONFIG_SYS_HID0_FINAL           HID0_ENABLE_MACHINE_CHECK
 500 #define CONFIG_SYS_HID2         HID2_HBE
 501
 502 /*
 503  * MMU Setup
 504  */
 505
 506 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 507
 508 /* DDR/LBC SDRAM: cacheable */
 509 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 510 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 511 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 512 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 513
 514 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 515 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 516                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 517 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 518 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 519 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 520
 521 /* BCSR: cache-inhibit and guarded */
 522 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR | BATL_PP_10 | \
 523                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 524 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
 525 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 526 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 527
 528 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 529 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 530 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 531 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 532                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 533 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 534
 535 /* DDR/LBC SDRAM next 256M: cacheable */
 536 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_SDRAM_BASE2 | BATL_PP_10 | BATL_MEMCOHERENCE)
 537 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_SDRAM_BASE2 | BATU_BL_256M | BATU_VS | BATU_VP)
 538 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 539 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 540
 541 /* Stack in dcache: cacheable, no memory coherence */
 542 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 543 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 544 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 545 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 546
 547 #ifdef CONFIG_PCI
 548 /* PCI MEM space: cacheable */
 549 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 550 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 551 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 552 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 553 /* PCI MMIO space: cache-inhibit and guarded */
 554 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
 555                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 556 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 557 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 558 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 559 #else
 560 #define CONFIG_SYS_IBAT6L       (0)
 561 #define CONFIG_SYS_IBAT6U       (0)
 562 #define CONFIG_SYS_IBAT7L       (0)
 563 #define CONFIG_SYS_IBAT7U       (0)
 564 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 565 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 566 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 567 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 568 #endif
 569
 570 /*
 571  * Internal Definitions
 572  *
 573  * Boot Flags
 574  */
 575 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 576 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 577
 578 #if defined(CONFIG_CMD_KGDB)
 579 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 580 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 581 #endif
 582
 583 /*
 584  * Environment Configuration
 585  */
 586
 587 #define CONFIG_ENV_OVERWRITE
 588
 589 #if defined(CONFIG_UEC_ETH)
 590 #define CONFIG_HAS_ETH0
 591 #define CONFIG_HAS_ETH1
 592 #endif
 593
 594 #define CONFIG_BAUDRATE 115200
 595
 596 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 597
 598 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 599 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 600
 601 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 602    "netdev=eth0\0"                                                      \
 603    "consoledev=ttyS0\0"                                                 \
 604    "ramdiskaddr=1000000\0"                                              \
 605    "ramdiskfile=ramfs.83xx\0"                                           \
 606    "fdtaddr=780000\0"                                                   \
 607    "fdtfile=mpc836x_mds.dtb\0"                                          \
 608    ""
 609
 610 #define CONFIG_NFSBOOTCOMMAND                                           \
 611    "setenv bootargs root=/dev/nfs rw "                                  \
 612       "nfsroot=$serverip:$rootpath "                                    \
 613       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 614       "console=$consoledev,$baudrate $othbootargs;"                     \
 615    "tftp $loadaddr $bootfile;"                                          \
 616    "tftp $fdtaddr $fdtfile;"                                            \
 617    "bootm $loadaddr - $fdtaddr"
 618
 619 #define CONFIG_RAMBOOTCOMMAND                                           \
 620    "setenv bootargs root=/dev/ram rw "                                  \
 621       "console=$consoledev,$baudrate $othbootargs;"                     \
 622    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 623    "tftp $loadaddr $bootfile;"                                          \
 624    "tftp $fdtaddr $fdtfile;"                                            \
 625    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 626
 627
 628 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 629
 630 #endif  /* __CONFIG_H */