include/configs/MPC8548CDS.h

   1 /*
   2  * Copyright 2004, 2007 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * mpc8548cds board configuration file
  25  *
  26  * Please refer to doc/README.mpc85xxcds for more info.
  27  *
  28  */
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /* High Level Configuration Options */
  33 #define CONFIG_BOOKE            1       /* BOOKE */
  34 #define CONFIG_E500             1       /* BOOKE e500 family */
  35 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41/48 */
  36 #define CONFIG_MPC8548          1       /* MPC8548 specific */
  37 #define CONFIG_MPC8548CDS       1       /* MPC8548CDS board specific */
  38
  39 #define CONFIG_PCI              /* enable any pci type devices */
  40 #define CONFIG_PCI1             /* PCI controller 1 */
  41 #define CONFIG_PCIE1            /* PCIE controler 1 (slot 1) */
  42 #undef CONFIG_RIO
  43 #undef CONFIG_PCI2
  44 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  45 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  46 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  47
  48 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  49 #define CONFIG_ENV_OVERWRITE
  50 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  51 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  52
  53 #define CONFIG_FSL_VIA
  54
  55 /*
  56  * When initializing flash, if we cannot find the manufacturer ID,
  57  * assume this is the AMD flash associated with the CDS board.
  58  * This allows booting from a promjet.
  59  */
  60 #define CONFIG_ASSUME_AMD_FLASH
  61
  62 #ifndef __ASSEMBLY__
  63 extern unsigned long get_clock_freq(void);
  64 #endif
  65 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  66
  67 /*
  68  * These can be toggled for performance analysis, otherwise use default.
  69  */
  70 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  71 #define CONFIG_BTB                      /* toggle branch predition */
  72 #define CONFIG_CLEAR_LAW0               /* Clear LAW0 in cpu_init_r */
  73
  74 /*
  75  * Only possible on E500 Version 2 or newer cores.
  76  */
  77 #define CONFIG_ENABLE_36BIT_PHYS        1
  78
  79 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  80 #define CONFIG_SYS_MEMTEST_END          0x00400000
  81
  82 /*
  83  * Base addresses -- Note these are effective addresses where the
  84  * actual resources get mapped (not physical addresses)
  85  */
  86 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  87 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  88 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  89 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  90
  91 #define CONFIG_SYS_PCI1_ADDR    (CONFIG_SYS_CCSRBAR+0x8000)
  92 #define CONFIG_SYS_PCI2_ADDR    (CONFIG_SYS_CCSRBAR+0x9000)
  93 #define CONFIG_SYS_PCIE1_ADDR   (CONFIG_SYS_CCSRBAR+0xa000)
  94
  95 /* DDR Setup */
  96 #define CONFIG_FSL_DDR2
  97 #undef CONFIG_FSL_DDR_INTERACTIVE
  98 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  99 #define CONFIG_DDR_SPD
 100 #define CONFIG_DDR_DLL                  /* possible DLL fix needed */
 101
 102 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 103 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 104
 105 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 106 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 107
 108 #define CONFIG_NUM_DDR_CONTROLLERS      1
 109 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 110 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 111
 112 /* I2C addresses of SPD EEPROMs */
 113 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 114
 115 /* Make sure required options are set */
 116 #ifndef CONFIG_SPD_EEPROM
 117 #error ("CONFIG_SPD_EEPROM is required")
 118 #endif
 119
 120 #undef CONFIG_CLOCKS_IN_MHZ
 121
 122 /*
 123  * Local Bus Definitions
 124  */
 125
 126 /*
 127  * FLASH on the Local Bus
 128  * Two banks, 8M each, using the CFI driver.
 129  * Boot from BR0/OR0 bank at 0xff00_0000
 130  * Alternate BR1/OR1 bank at 0xff80_0000
 131  *
 132  * BR0, BR1:
 133  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 134  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 135  *    Port Size = 16 bits = BRx[19:20] = 10
 136  *    Use GPCM = BRx[24:26] = 000
 137  *    Valid = BRx[31] = 1
 138  *
 139  * 0    4    8    12   16   20   24   28
 140  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 141  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 142  *
 143  * OR0, OR1:
 144  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 145  *    Reserved ORx[17:18] = 11, confusion here?
 146  *    CSNT = ORx[20] = 1
 147  *    ACS = half cycle delay = ORx[21:22] = 11
 148  *    SCY = 6 = ORx[24:27] = 0110
 149  *    TRLX = use relaxed timing = ORx[29] = 1
 150  *    EAD = use external address latch delay = OR[31] = 1
 151  *
 152  * 0    4    8    12   16   20   24   28
 153  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 154  */
 155
 156 #define CONFIG_SYS_BOOT_BLOCK           0xff000000      /* boot TLB block */
 157 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_BOOT_BLOCK   /* start of FLASH 16M */
 158
 159 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 160 #define CONFIG_SYS_BR1_PRELIM           0xff001001
 161
 162 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 163 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 164
 165 #define CONFIG_SYS_FLASH_BANKS_LIST     {0xff800000, CONFIG_SYS_FLASH_BASE}
 166 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 167 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 168 #undef  CONFIG_SYS_FLASH_CHECKSUM
 169 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 170 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 171
 172 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 173
 174 #define CONFIG_FLASH_CFI_DRIVER
 175 #define CONFIG_SYS_FLASH_CFI
 176 #define CONFIG_SYS_FLASH_EMPTY_INFO
 177
 178
 179 /*
 180  * SDRAM on the Local Bus
 181  */
 182 #define CONFIG_SYS_LBC_CACHE_BASE       0xf0000000      /* Localbus cacheable */
 183 #define CONFIG_SYS_LBC_CACHE_SIZE       64
 184 #define CONFIG_SYS_LBC_NONCACHE_BASE    0xf8000000      /* Localbus non-cacheable */
 185 #define CONFIG_SYS_LBC_NONCACHE_SIZE    64
 186
 187 #define CONFIG_SYS_LBC_SDRAM_BASE       CONFIG_SYS_LBC_CACHE_BASE       /* Localbus SDRAM */
 188 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 189
 190 /*
 191  * Base Register 2 and Option Register 2 configure SDRAM.
 192  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 193  *
 194  * For BR2, need:
 195  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 196  *    port-size = 32-bits = BR2[19:20] = 11
 197  *    no parity checking = BR2[21:22] = 00
 198  *    SDRAM for MSEL = BR2[24:26] = 011
 199  *    Valid = BR[31] = 1
 200  *
 201  * 0    4    8    12   16   20   24   28
 202  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 203  *
 204  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 205  * FIXME: the top 17 bits of BR2.
 206  */
 207
 208 #define CONFIG_SYS_BR2_PRELIM           0xf0001861
 209
 210 /*
 211  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 212  *
 213  * For OR2, need:
 214  *    64MB mask for AM, OR2[0:7] = 1111 1100
 215  *                 XAM, OR2[17:18] = 11
 216  *    9 columns OR2[19-21] = 010
 217  *    13 rows   OR2[23-25] = 100
 218  *    EAD set for extra time OR[31] = 1
 219  *
 220  * 0    4    8    12   16   20   24   28
 221  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 222  */
 223
 224 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 225
 226 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* LB clock ratio reg */
 227 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg */
 228 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 229 #define CONFIG_SYS_LBC_MRTPR            0x00000000      /* LB refresh timer prescal*/
 230
 231 /*
 232  * Common settings for all Local Bus SDRAM commands.
 233  * At run time, either BSMA1516 (for CPU 1.1)
 234  *                  or BSMA1617 (for CPU 1.0) (old)
 235  * is OR'ed in too.
 236  */
 237 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 238                                 | LSDMR_PRETOACT7       \
 239                                 | LSDMR_ACTTORW7        \
 240                                 | LSDMR_BL8             \
 241                                 | LSDMR_WRC4            \
 242                                 | LSDMR_CL3             \
 243                                 | LSDMR_RFEN            \
 244                                 )
 245
 246 /*
 247  * The CADMUS registers are connected to CS3 on CDS.
 248  * The new memory map places CADMUS at 0xf8000000.
 249  *
 250  * For BR3, need:
 251  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 252  *    port-size = 8-bits  = BR[19:20] = 01
 253  *    no parity checking  = BR[21:22] = 00
 254  *    GPMC for MSEL       = BR[24:26] = 000
 255  *    Valid               = BR[31]    = 1
 256  *
 257  * 0    4    8    12   16   20   24   28
 258  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 259  *
 260  * For OR3, need:
 261  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 262  *    disable buffer ctrl OR[19]    = 0
 263  *    CSNT                OR[20]    = 1
 264  *    ACS                 OR[21:22] = 11
 265  *    XACS                OR[23]    = 1
 266  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 267  *    SETA                OR[28]    = 0
 268  *    TRLX                OR[29]    = 1
 269  *    EHTR                OR[30]    = 1
 270  *    EAD extra time      OR[31]    = 1
 271  *
 272  * 0    4    8    12   16   20   24   28
 273  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 274  */
 275
 276 #define CONFIG_FSL_CADMUS
 277
 278 #define CADMUS_BASE_ADDR 0xf8000000
 279 #define CONFIG_SYS_BR3_PRELIM    0xf8000801
 280 #define CONFIG_SYS_OR3_PRELIM    0xfff00ff7
 281
 282 #define CONFIG_SYS_INIT_RAM_LOCK        1
 283 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 284 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 285
 286 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000      /* relocate boot L2SRAM */
 287
 288 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 289 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 290 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 291
 292 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 293 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 294
 295 /* Serial Port */
 296 #define CONFIG_CONS_INDEX       2
 297 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 298 #define CONFIG_SYS_NS16550
 299 #define CONFIG_SYS_NS16550_SERIAL
 300 #define CONFIG_SYS_NS16550_REG_SIZE     1
 301 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 302
 303 #define CONFIG_SYS_BAUDRATE_TABLE \
 304         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 305
 306 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 307 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 308
 309 /* Use the HUSH parser */
 310 #define CONFIG_SYS_HUSH_PARSER
 311 #ifdef  CONFIG_SYS_HUSH_PARSER
 312 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 313 #endif
 314
 315 /* pass open firmware flat tree */
 316 #define CONFIG_OF_LIBFDT                1
 317 #define CONFIG_OF_BOARD_SETUP           1
 318 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 319
 320 #define CONFIG_SYS_64BIT_VSPRINTF       1
 321 #define CONFIG_SYS_64BIT_STRTOUL        1
 322
 323 /*
 324  * I2C
 325  */
 326 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 327 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 328 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 329 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 330 #define CONFIG_SYS_I2C_SLAVE            0x7F
 331 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 332 #define CONFIG_SYS_I2C_OFFSET           0x3000
 333
 334 /* EEPROM */
 335 #define CONFIG_ID_EEPROM
 336 #define CONFIG_SYS_I2C_EEPROM_CCID
 337 #define CONFIG_SYS_ID_EEPROM
 338 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 339 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 340
 341 /*
 342  * General PCI
 343  * Memory space is mapped 1-1, but I/O space must start from 0.
 344  */
 345 #define CONFIG_SYS_PCI_VIRT             0x80000000      /* 1G PCI TLB */
 346 #define CONFIG_SYS_PCI_PHYS             0x80000000      /* 1G PCI TLB */
 347
 348 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 349 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 350 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 351 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 352 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 353 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 354 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 355 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 356
 357 #ifdef CONFIG_PCI2
 358 #define CONFIG_SYS_PCI2_MEM_VIRT        0xa0000000
 359 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
 360 #define CONFIG_SYS_PCI2_MEM_PHYS        0xa0000000
 361 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 362 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000
 363 #define CONFIG_SYS_PCI2_IO_BUS  0x00000000
 364 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
 365 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 366 #endif
 367
 368 #ifdef CONFIG_PCIE1
 369 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 370 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 371 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 372 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 373 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe3000000
 374 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 375 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 376 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /*   1M */
 377 #endif
 378
 379 #ifdef CONFIG_RIO
 380 /*
 381  * RapidIO MMU
 382  */
 383 #define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000
 384 #define CONFIG_SYS_RIO_MEM_BUS  0xC0000000
 385 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 512M */
 386 #endif
 387
 388 #ifdef CONFIG_LEGACY
 389 #define BRIDGE_ID 17
 390 #define VIA_ID 2
 391 #else
 392 #define BRIDGE_ID 28
 393 #define VIA_ID 4
 394 #endif
 395
 396 #if defined(CONFIG_PCI)
 397
 398 #define CONFIG_NET_MULTI
 399 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 400
 401 #undef CONFIG_EEPRO100
 402 #undef CONFIG_TULIP
 403
 404 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 405
 406 #endif  /* CONFIG_PCI */
 407
 408
 409 #if defined(CONFIG_TSEC_ENET)
 410
 411 #ifndef CONFIG_NET_MULTI
 412 #define CONFIG_NET_MULTI        1
 413 #endif
 414
 415 #define CONFIG_MII              1       /* MII PHY management */
 416 #define CONFIG_TSEC1    1
 417 #define CONFIG_TSEC1_NAME       "eTSEC0"
 418 #define CONFIG_TSEC2    1
 419 #define CONFIG_TSEC2_NAME       "eTSEC1"
 420 #define CONFIG_TSEC3    1
 421 #define CONFIG_TSEC3_NAME       "eTSEC2"
 422 #define CONFIG_TSEC4
 423 #define CONFIG_TSEC4_NAME       "eTSEC3"
 424 #undef CONFIG_MPC85XX_FEC
 425
 426 #define TSEC1_PHY_ADDR          0
 427 #define TSEC2_PHY_ADDR          1
 428 #define TSEC3_PHY_ADDR          2
 429 #define TSEC4_PHY_ADDR          3
 430
 431 #define TSEC1_PHYIDX            0
 432 #define TSEC2_PHYIDX            0
 433 #define TSEC3_PHYIDX            0
 434 #define TSEC4_PHYIDX            0
 435 #define TSEC1_FLAGS             TSEC_GIGABIT
 436 #define TSEC2_FLAGS             TSEC_GIGABIT
 437 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 438 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 439
 440 /* Options are: eTSEC[0-3] */
 441 #define CONFIG_ETHPRIME         "eTSEC0"
 442 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 443 #endif  /* CONFIG_TSEC_ENET */
 444
 445 /*
 446  * Environment
 447  */
 448 #define CONFIG_ENV_IS_IN_FLASH  1
 449 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 450 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 451 #define CONFIG_ENV_SIZE         0x2000
 452
 453 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 454 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 455
 456 /*
 457  * BOOTP options
 458  */
 459 #define CONFIG_BOOTP_BOOTFILESIZE
 460 #define CONFIG_BOOTP_BOOTPATH
 461 #define CONFIG_BOOTP_GATEWAY
 462 #define CONFIG_BOOTP_HOSTNAME
 463
 464
 465 /*
 466  * Command line configuration.
 467  */
 468 #include <config_cmd_default.h>
 469
 470 #define CONFIG_CMD_PING
 471 #define CONFIG_CMD_I2C
 472 #define CONFIG_CMD_MII
 473 #define CONFIG_CMD_ELF
 474 #define CONFIG_CMD_IRQ
 475 #define CONFIG_CMD_SETEXPR
 476
 477 #if defined(CONFIG_PCI)
 478     #define CONFIG_CMD_PCI
 479 #endif
 480
 481
 482 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 483
 484 /*
 485  * Miscellaneous configurable options
 486  */
 487 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 488 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 489 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 490 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 491 #if defined(CONFIG_CMD_KGDB)
 492 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 493 #else
 494 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 495 #endif
 496 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 497 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 498 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 499 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 500
 501 /*
 502  * For booting Linux, the board info and command line data
 503  * have to be in the first 8 MB of memory, since this is
 504  * the maximum mapped by the Linux kernel during initialization.
 505  */
 506 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 507
 508 /*
 509  * Internal Definitions
 510  *
 511  * Boot Flags
 512  */
 513 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 514 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 515
 516 #if defined(CONFIG_CMD_KGDB)
 517 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 518 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 519 #endif
 520
 521 /*
 522  * Environment Configuration
 523  */
 524
 525 /* The mac addresses for all ethernet interface */
 526 #if defined(CONFIG_TSEC_ENET)
 527 #define CONFIG_HAS_ETH0
 528 #define CONFIG_ETHADDR   00:E0:0C:00:00:FD
 529 #define CONFIG_HAS_ETH1
 530 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 531 #define CONFIG_HAS_ETH2
 532 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
 533 #define CONFIG_HAS_ETH3
 534 #define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 535 #endif
 536
 537 #define CONFIG_IPADDR    192.168.1.253
 538
 539 #define CONFIG_HOSTNAME  unknown
 540 #define CONFIG_ROOTPATH  /nfsroot
 541 #define CONFIG_BOOTFILE 8548cds/uImage.uboot
 542 #define CONFIG_UBOOTPATH        8548cds/u-boot.bin      /* TFTP server */
 543
 544 #define CONFIG_SERVERIP  192.168.1.1
 545 #define CONFIG_GATEWAYIP 192.168.1.1
 546 #define CONFIG_NETMASK   255.255.255.0
 547
 548 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 549
 550 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 551 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 552
 553 #define CONFIG_BAUDRATE 115200
 554
 555 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 556  "netdev=eth0\0"                                                \
 557  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                         \
 558  "tftpflash=tftpboot $loadaddr $uboot; "                        \
 559         "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 560         "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 561         "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 562         "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 563         "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 564  "consoledev=ttyS1\0"                           \
 565  "ramdiskaddr=2000000\0"                        \
 566  "ramdiskfile=ramdisk.uboot\0"                  \
 567  "fdtaddr=c00000\0"                             \
 568  "fdtfile=mpc8548cds.dtb\0"
 569
 570 #define CONFIG_NFSBOOTCOMMAND                                           \
 571    "setenv bootargs root=/dev/nfs rw "                                  \
 572       "nfsroot=$serverip:$rootpath "                                    \
 573       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 574       "console=$consoledev,$baudrate $othbootargs;"                     \
 575    "tftp $loadaddr $bootfile;"                                          \
 576    "tftp $fdtaddr $fdtfile;"                                            \
 577    "bootm $loadaddr - $fdtaddr"
 578
 579
 580 #define CONFIG_RAMBOOTCOMMAND \
 581    "setenv bootargs root=/dev/ram rw "                                  \
 582       "console=$consoledev,$baudrate $othbootargs;"                     \
 583    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 584    "tftp $loadaddr $bootfile;"                                          \
 585    "tftp $fdtaddr $fdtfile;"                                            \
 586    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 587
 588 #define CONFIG_BOOTCOMMAND      CONFIG_NFSBOOTCOMMAND
 589
 590 #endif  /* __CONFIG_H */