include/configs/MPC8555CDS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8555cds board configuration file
   9  *
  10  * Please refer to doc/README.mpc85xxcds for more info.
  11  *
  12  */
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_BOOKE            1       /* BOOKE */
  18 #define CONFIG_E500             1       /* BOOKE e500 family */
  19 #define CONFIG_CPM2             1       /* has CPM2 */
  20
  21 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  22
  23 #define CONFIG_PCI_INDIRECT_BRIDGE
  24 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  25 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  26 #define CONFIG_ENV_OVERWRITE
  27 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  28
  29 #define CONFIG_FSL_VIA
  30
  31 #ifndef __ASSEMBLY__
  32 extern unsigned long get_clock_freq(void);
  33 #endif
  34 #define CONFIG_SYS_CLK_FREQ     get_clock_freq() /* sysclk for MPC85xx */
  35
  36 /*
  37  * These can be toggled for performance analysis, otherwise use default.
  38  */
  39 #define CONFIG_L2_CACHE                     /* toggle L2 cache  */
  40 #define CONFIG_BTB                          /* toggle branch predition */
  41
  42 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  43 #define CONFIG_SYS_MEMTEST_END          0x00400000
  44
  45 #define CONFIG_SYS_CCSRBAR              0xe0000000
  46 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  47
  48 /* DDR Setup */
  49 #define CONFIG_SYS_FSL_DDR1
  50 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  51 #define CONFIG_DDR_SPD
  52 #undef CONFIG_FSL_DDR_INTERACTIVE
  53
  54 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  55
  56 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  57 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  58
  59 #define CONFIG_NUM_DDR_CONTROLLERS      1
  60 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  61 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  62
  63 /* I2C addresses of SPD EEPROMs */
  64 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  65
  66 /* Make sure required options are set */
  67 #ifndef CONFIG_SPD_EEPROM
  68 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
  69 #endif
  70
  71 #undef CONFIG_CLOCKS_IN_MHZ
  72
  73 /*
  74  * Local Bus Definitions
  75  */
  76
  77 /*
  78  * FLASH on the Local Bus
  79  * Two banks, 8M each, using the CFI driver.
  80  * Boot from BR0/OR0 bank at 0xff00_0000
  81  * Alternate BR1/OR1 bank at 0xff80_0000
  82  *
  83  * BR0, BR1:
  84  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  85  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  86  *    Port Size = 16 bits = BRx[19:20] = 10
  87  *    Use GPCM = BRx[24:26] = 000
  88  *    Valid = BRx[31] = 1
  89  *
  90  * 0    4    8    12   16   20   24   28
  91  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
  92  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
  93  *
  94  * OR0, OR1:
  95  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  96  *    Reserved ORx[17:18] = 11, confusion here?
  97  *    CSNT = ORx[20] = 1
  98  *    ACS = half cycle delay = ORx[21:22] = 11
  99  *    SCY = 6 = ORx[24:27] = 0110
 100  *    TRLX = use relaxed timing = ORx[29] = 1
 101  *    EAD = use external address latch delay = OR[31] = 1
 102  *
 103  * 0    4    8    12   16   20   24   28
 104  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 105  */
 106
 107 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 8M */
 108
 109 #define CONFIG_SYS_BR0_PRELIM           0xff801001
 110 #define CONFIG_SYS_BR1_PRELIM           0xff001001
 111
 112 #define CONFIG_SYS_OR0_PRELIM           0xff806e65
 113 #define CONFIG_SYS_OR1_PRELIM           0xff806e65
 114
 115 #define CONFIG_SYS_FLASH_BANKS_LIST     {0xff800000, CONFIG_SYS_FLASH_BASE}
 116 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 117 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 118 #undef  CONFIG_SYS_FLASH_CHECKSUM
 119 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 120 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 121
 122 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 123
 124 #define CONFIG_FLASH_CFI_DRIVER
 125 #define CONFIG_SYS_FLASH_CFI
 126 #define CONFIG_SYS_FLASH_EMPTY_INFO
 127
 128 /*
 129  * SDRAM on the Local Bus
 130  */
 131 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 132 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 133
 134 /*
 135  * Base Register 2 and Option Register 2 configure SDRAM.
 136  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 137  *
 138  * For BR2, need:
 139  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 140  *    port-size = 32-bits = BR2[19:20] = 11
 141  *    no parity checking = BR2[21:22] = 00
 142  *    SDRAM for MSEL = BR2[24:26] = 011
 143  *    Valid = BR[31] = 1
 144  *
 145  * 0    4    8    12   16   20   24   28
 146  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 147  *
 148  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 149  * FIXME: the top 17 bits of BR2.
 150  */
 151
 152 #define CONFIG_SYS_BR2_PRELIM          0xf0001861
 153
 154 /*
 155  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 156  *
 157  * For OR2, need:
 158  *    64MB mask for AM, OR2[0:7] = 1111 1100
 159  *                 XAM, OR2[17:18] = 11
 160  *    9 columns OR2[19-21] = 010
 161  *    13 rows   OR2[23-25] = 100
 162  *    EAD set for extra time OR[31] = 1
 163  *
 164  * 0    4    8    12   16   20   24   28
 165  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 166  */
 167
 168 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 169
 170 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 171 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 172 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 173 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 174
 175 /*
 176  * Common settings for all Local Bus SDRAM commands.
 177  * At run time, either BSMA1516 (for CPU 1.1)
 178  *                  or BSMA1617 (for CPU 1.0) (old)
 179  * is OR'ed in too.
 180  */
 181 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 182                                 | LSDMR_PRETOACT7       \
 183                                 | LSDMR_ACTTORW7        \
 184                                 | LSDMR_BL8             \
 185                                 | LSDMR_WRC4            \
 186                                 | LSDMR_CL3             \
 187                                 | LSDMR_RFEN            \
 188                                 )
 189
 190 /*
 191  * The CADMUS registers are connected to CS3 on CDS.
 192  * The new memory map places CADMUS at 0xf8000000.
 193  *
 194  * For BR3, need:
 195  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 196  *    port-size = 8-bits  = BR[19:20] = 01
 197  *    no parity checking  = BR[21:22] = 00
 198  *    GPMC for MSEL       = BR[24:26] = 000
 199  *    Valid               = BR[31]    = 1
 200  *
 201  * 0    4    8    12   16   20   24   28
 202  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 203  *
 204  * For OR3, need:
 205  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 206  *    disable buffer ctrl OR[19]    = 0
 207  *    CSNT                OR[20]    = 1
 208  *    ACS                 OR[21:22] = 11
 209  *    XACS                OR[23]    = 1
 210  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 211  *    SETA                OR[28]    = 0
 212  *    TRLX                OR[29]    = 1
 213  *    EHTR                OR[30]    = 1
 214  *    EAD extra time      OR[31]    = 1
 215  *
 216  * 0    4    8    12   16   20   24   28
 217  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 218  */
 219
 220 #define CONFIG_FSL_CADMUS
 221
 222 #define CADMUS_BASE_ADDR 0xf8000000
 223 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 224 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 225
 226 #define CONFIG_SYS_INIT_RAM_LOCK        1
 227 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 228 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000      /* Size of used area in RAM */
 229
 230 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 231 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 232
 233 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 234 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 235
 236 /* Serial Port */
 237 #define CONFIG_CONS_INDEX     2
 238 #define CONFIG_SYS_NS16550_SERIAL
 239 #define CONFIG_SYS_NS16550_REG_SIZE    1
 240 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 241
 242 #define CONFIG_SYS_BAUDRATE_TABLE  \
 243         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 244
 245 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 246 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 247
 248 /*
 249  * I2C
 250  */
 251 #define CONFIG_SYS_I2C
 252 #define CONFIG_SYS_I2C_FSL
 253 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 254 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 255 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 256 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 257
 258 /* EEPROM */
 259 #define CONFIG_ID_EEPROM
 260 #define CONFIG_SYS_I2C_EEPROM_CCID
 261 #define CONFIG_SYS_ID_EEPROM
 262 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 263 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 264
 265 /*
 266  * General PCI
 267  * Addresses are mapped 1-1.
 268  */
 269 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 270 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 271 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 272 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 273 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 274 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 275 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 276 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 277
 278 #define CONFIG_SYS_PCI2_MEM_VIRT        0xa0000000
 279 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
 280 #define CONFIG_SYS_PCI2_MEM_PHYS        0xa0000000
 281 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 282 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
 283 #define CONFIG_SYS_PCI2_IO_BUS  0x00000000
 284 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
 285 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 286
 287 #ifdef CONFIG_LEGACY
 288 #define BRIDGE_ID 17
 289 #define VIA_ID 2
 290 #else
 291 #define BRIDGE_ID 28
 292 #define VIA_ID 4
 293 #endif
 294
 295 #if defined(CONFIG_PCI)
 296
 297 #define CONFIG_MPC85XX_PCI2
 298
 299 #undef CONFIG_EEPRO100
 300 #undef CONFIG_TULIP
 301
 302 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 303 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 304
 305 #endif  /* CONFIG_PCI */
 306
 307 #if defined(CONFIG_TSEC_ENET)
 308
 309 #define CONFIG_MII              1       /* MII PHY management */
 310 #define CONFIG_TSEC1    1
 311 #define CONFIG_TSEC1_NAME       "TSEC0"
 312 #define CONFIG_TSEC2    1
 313 #define CONFIG_TSEC2_NAME       "TSEC1"
 314 #define TSEC1_PHY_ADDR          0
 315 #define TSEC2_PHY_ADDR          1
 316 #define TSEC1_PHYIDX            0
 317 #define TSEC2_PHYIDX            0
 318 #define TSEC1_FLAGS             TSEC_GIGABIT
 319 #define TSEC2_FLAGS             TSEC_GIGABIT
 320
 321 /* Options are: TSEC[0-1] */
 322 #define CONFIG_ETHPRIME         "TSEC0"
 323
 324 #endif  /* CONFIG_TSEC_ENET */
 325
 326 /*
 327  * Environment
 328  */
 329 #define CONFIG_ENV_IS_IN_FLASH  1
 330 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 331 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 332 #define CONFIG_ENV_SIZE         0x2000
 333
 334 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 335 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 336
 337 /*
 338  * BOOTP options
 339  */
 340 #define CONFIG_BOOTP_BOOTFILESIZE
 341 #define CONFIG_BOOTP_BOOTPATH
 342 #define CONFIG_BOOTP_GATEWAY
 343 #define CONFIG_BOOTP_HOSTNAME
 344
 345 /*
 346  * Command line configuration.
 347  */
 348 #define CONFIG_CMD_IRQ
 349 #define CONFIG_CMD_REGINFO
 350
 351 #if defined(CONFIG_PCI)
 352     #define CONFIG_CMD_PCI
 353 #endif
 354
 355 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 356
 357 /*
 358  * Miscellaneous configurable options
 359  */
 360 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 361 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 362 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 363 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 364 #if defined(CONFIG_CMD_KGDB)
 365 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 366 #else
 367 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 368 #endif
 369 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 370 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 371 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 372
 373 /*
 374  * For booting Linux, the board info and command line data
 375  * have to be in the first 64 MB of memory, since this is
 376  * the maximum mapped by the Linux kernel during initialization.
 377  */
 378 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 379 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 380
 381 #if defined(CONFIG_CMD_KGDB)
 382 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 383 #endif
 384
 385 /*
 386  * Environment Configuration
 387  */
 388 #if defined(CONFIG_TSEC_ENET)
 389 #define CONFIG_HAS_ETH0
 390 #define CONFIG_HAS_ETH1
 391 #define CONFIG_HAS_ETH2
 392 #endif
 393
 394 #define CONFIG_IPADDR    192.168.1.253
 395
 396 #define CONFIG_HOSTNAME  unknown
 397 #define CONFIG_ROOTPATH  "/nfsroot"
 398 #define CONFIG_BOOTFILE  "your.uImage"
 399
 400 #define CONFIG_SERVERIP  192.168.1.1
 401 #define CONFIG_GATEWAYIP 192.168.1.1
 402 #define CONFIG_NETMASK   255.255.255.0
 403
 404 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 405
 406 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 407
 408 #define CONFIG_BAUDRATE 115200
 409
 410 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 411    "netdev=eth0\0"                                                      \
 412    "consoledev=ttyS1\0"                                                 \
 413    "ramdiskaddr=600000\0"                                               \
 414    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 415    "fdtaddr=400000\0"                                                   \
 416    "fdtfile=your.fdt.dtb\0"
 417
 418 #define CONFIG_NFSBOOTCOMMAND                                           \
 419    "setenv bootargs root=/dev/nfs rw "                                  \
 420       "nfsroot=$serverip:$rootpath "                                    \
 421       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 422       "console=$consoledev,$baudrate $othbootargs;"                     \
 423    "tftp $loadaddr $bootfile;"                                          \
 424    "tftp $fdtaddr $fdtfile;"                                            \
 425    "bootm $loadaddr - $fdtaddr"
 426
 427 #define CONFIG_RAMBOOTCOMMAND \
 428    "setenv bootargs root=/dev/ram rw "                                  \
 429       "console=$consoledev,$baudrate $othbootargs;"                     \
 430    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 431    "tftp $loadaddr $bootfile;"                                          \
 432    "bootm $loadaddr $ramdiskaddr"
 433
 434 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 435
 436 #endif  /* __CONFIG_H */