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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/MPC8560ADS.h
2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * mpc8560ads board configuration file
28 * Please refer to doc/README.mpc85xx for more info.
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
37 /* High Level Configuration Options */
38 #define CONFIG_BOOKE 1 /* BOOKE */
39 #define CONFIG_E500 1 /* BOOKE e500 family */
40 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41 #define CONFIG_CPM2 1 /* has CPM2 */
42 #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
43 #define CONFIG_MPC8560 1
46 #define CONFIG_TSEC_ENET /* tsec ethernet support */
47 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
48 #define CONFIG_ENV_OVERWRITE
49 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
54 * Two valid values are:
58 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
59 * is likely the desired value here, so that is now the default.
60 * The board, however, can run at 66MHz. In any event, this value
61 * must match the settings of some switches. Details can be found
62 * in the README.mpc85xxads.
65 #ifndef CONFIG_SYS_CLK_FREQ
66 #define CONFIG_SYS_CLK_FREQ 33000000
71 * These can be toggled for performance analysis, otherwise use default.
73 #define CONFIG_L2_CACHE /* toggle L2 cache */
74 #define CONFIG_BTB /* toggle branch predition */
75 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
77 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
79 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
80 #define CONFIG_SYS_MEMTEST_END 0x00400000
84 * Base addresses -- Note these are effective addresses where the
85 * actual resources get mapped (not physical addresses)
87 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
88 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
89 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
90 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
93 #define CONFIG_FSL_DDR1
94 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
95 #define CONFIG_DDR_SPD
96 #undef CONFIG_FSL_DDR_INTERACTIVE
98 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
100 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
101 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
103 #define CONFIG_NUM_DDR_CONTROLLERS 1
104 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
105 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
107 /* I2C addresses of SPD EEPROMs */
108 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
110 /* These are used when DDR doesn't use SPD. */
111 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
112 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
113 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
114 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
115 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
116 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
117 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
118 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
121 * SDRAM on the Local Bus
123 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
124 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
126 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
127 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
129 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
130 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
131 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
132 #undef CONFIG_SYS_FLASH_CHECKSUM
133 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
134 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
136 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
138 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
139 #define CONFIG_SYS_RAMBOOT
141 #undef CONFIG_SYS_RAMBOOT
144 #define CONFIG_FLASH_CFI_DRIVER
145 #define CONFIG_SYS_FLASH_CFI
146 #define CONFIG_SYS_FLASH_EMPTY_INFO
148 #undef CONFIG_CLOCKS_IN_MHZ
152 * Local Bus Definitions
156 * Base Register 2 and Option Register 2 configure SDRAM.
157 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
160 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
161 * port-size = 32-bits = BR2[19:20] = 11
162 * no parity checking = BR2[21:22] = 00
163 * SDRAM for MSEL = BR2[24:26] = 011
166 * 0 4 8 12 16 20 24 28
167 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
169 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
170 * FIXME: the top 17 bits of BR2.
173 #define CONFIG_SYS_BR2_PRELIM 0xf0001861
176 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
179 * 64MB mask for AM, OR2[0:7] = 1111 1100
180 * XAM, OR2[17:18] = 11
181 * 9 columns OR2[19-21] = 010
182 * 13 rows OR2[23-25] = 100
183 * EAD set for extra time OR[31] = 1
185 * 0 4 8 12 16 20 24 28
186 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
189 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
191 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
192 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
193 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
194 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
199 #define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1))
200 #define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
201 #define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
202 #define CONFIG_SYS_LBC_LSDMR_RFCR5 (3 << (31 - 16))
203 #define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16))
204 #define CONFIG_SYS_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
205 #define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
206 #define CONFIG_SYS_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
207 #define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
208 #define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
209 #define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23))
210 #define CONFIG_SYS_LBC_LSDMR_WRC2 (2 << (31 - 27))
211 #define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27))
212 #define CONFIG_SYS_LBC_LSDMR_BUFCMD (1 << (31 - 29))
213 #define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31))
215 #define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
216 #define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
217 #define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
218 #define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
219 #define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
220 #define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
221 #define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
222 #define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
224 #define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_BSMA1516 \
225 | CONFIG_SYS_LBC_LSDMR_RFCR5 \
226 | CONFIG_SYS_LBC_LSDMR_PRETOACT3 \
227 | CONFIG_SYS_LBC_LSDMR_ACTTORW3 \
228 | CONFIG_SYS_LBC_LSDMR_BL8 \
229 | CONFIG_SYS_LBC_LSDMR_WRC2 \
230 | CONFIG_SYS_LBC_LSDMR_CL3 \
231 | CONFIG_SYS_LBC_LSDMR_RFEN \
235 * SDRAM Controller configuration sequence.
237 #define CONFIG_SYS_LBC_LSDMR_1 ( CONFIG_SYS_LBC_LSDMR_COMMON \
238 | CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
239 #define CONFIG_SYS_LBC_LSDMR_2 ( CONFIG_SYS_LBC_LSDMR_COMMON \
240 | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
241 #define CONFIG_SYS_LBC_LSDMR_3 ( CONFIG_SYS_LBC_LSDMR_COMMON \
242 | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
243 #define CONFIG_SYS_LBC_LSDMR_4 ( CONFIG_SYS_LBC_LSDMR_COMMON \
244 | CONFIG_SYS_LBC_LSDMR_OP_MRW)
245 #define CONFIG_SYS_LBC_LSDMR_5 ( CONFIG_SYS_LBC_LSDMR_COMMON \
246 | CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
250 * 32KB, 8-bit wide for ADS config reg
252 #define CONFIG_SYS_BR4_PRELIM 0xf8000801
253 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
254 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
256 #define CONFIG_L1_INIT_RAM
257 #define CONFIG_SYS_INIT_RAM_LOCK 1
258 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
259 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
261 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
262 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
263 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
265 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
266 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
269 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
270 #undef CONFIG_CONS_NONE /* define if console on something else */
271 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
273 #define CONFIG_BAUDRATE 115200
275 #define CONFIG_SYS_BAUDRATE_TABLE \
276 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
278 /* Use the HUSH parser */
279 #define CONFIG_SYS_HUSH_PARSER
280 #ifdef CONFIG_SYS_HUSH_PARSER
281 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
284 /* pass open firmware flat tree */
285 #define CONFIG_OF_LIBFDT 1
286 #define CONFIG_OF_BOARD_SETUP 1
287 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
289 #define CONFIG_SYS_64BIT_VSPRINTF 1
290 #define CONFIG_SYS_64BIT_STRTOUL 1
295 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
296 #define CONFIG_HARD_I2C /* I2C with hardware support*/
297 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
298 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
299 #define CONFIG_SYS_I2C_SLAVE 0x7F
300 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
301 #define CONFIG_SYS_I2C_OFFSET 0x3000
304 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
305 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
306 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
310 * Memory space is mapped 1-1, but I/O space must start from 0.
312 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
313 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
314 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
315 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
316 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
317 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
319 #if defined(CONFIG_PCI)
321 #define CONFIG_NET_MULTI
322 #define CONFIG_PCI_PNP /* do pci plug-and-play */
324 #undef CONFIG_EEPRO100
327 #if !defined(CONFIG_PCI_PNP)
328 #define PCI_ENET0_IOADDR 0xe0000000
329 #define PCI_ENET0_MEMADDR 0xe0000000
330 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
333 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
334 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
336 #endif /* CONFIG_PCI */
339 #ifdef CONFIG_TSEC_ENET
341 #ifndef CONFIG_NET_MULTI
342 #define CONFIG_NET_MULTI 1
346 #define CONFIG_MII 1 /* MII PHY management */
348 #define CONFIG_TSEC1 1
349 #define CONFIG_TSEC1_NAME "TSEC0"
350 #define CONFIG_TSEC2 1
351 #define CONFIG_TSEC2_NAME "TSEC1"
352 #define TSEC1_PHY_ADDR 0
353 #define TSEC2_PHY_ADDR 1
354 #define TSEC1_PHYIDX 0
355 #define TSEC2_PHYIDX 0
356 #define TSEC1_FLAGS TSEC_GIGABIT
357 #define TSEC2_FLAGS TSEC_GIGABIT
359 /* Options are: TSEC[0-1] */
360 #define CONFIG_ETHPRIME "TSEC0"
362 #endif /* CONFIG_TSEC_ENET */
364 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
366 #undef CONFIG_ETHER_NONE /* define if ether on something else */
367 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
369 #if (CONFIG_ETHER_INDEX == 2)
373 * - Select bus for bd/buffers
376 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
377 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
378 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
379 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
380 #define FETH2_RST 0x01
381 #elif (CONFIG_ETHER_INDEX == 3)
382 /* need more definitions here for FE3 */
383 #define FETH3_RST 0x80
384 #endif /* CONFIG_ETHER_INDEX */
387 #define CONFIG_MII 1 /* MII PHY management */
390 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
393 * GPIO pins used for bit-banged MII communications
395 #define MDIO_PORT 2 /* Port C */
396 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
397 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
398 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
400 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
401 else iop->pdat &= ~0x00400000
403 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
404 else iop->pdat &= ~0x00200000
406 #define MIIDELAY udelay(1)
414 #ifndef CONFIG_SYS_RAMBOOT
415 #define CONFIG_ENV_IS_IN_FLASH 1
416 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
417 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
418 #define CONFIG_ENV_SIZE 0x2000
420 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
421 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
422 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
423 #define CONFIG_ENV_SIZE 0x2000
426 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
427 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
432 #define CONFIG_BOOTP_BOOTFILESIZE
433 #define CONFIG_BOOTP_BOOTPATH
434 #define CONFIG_BOOTP_GATEWAY
435 #define CONFIG_BOOTP_HOSTNAME
439 * Command line configuration.
441 #include <config_cmd_default.h>
443 #define CONFIG_CMD_PING
444 #define CONFIG_CMD_I2C
445 #define CONFIG_CMD_ELF
447 #if defined(CONFIG_PCI)
448 #define CONFIG_CMD_PCI
451 #if defined(CONFIG_ETHER_ON_FCC)
452 #define CONFIG_CMD_MII
455 #if defined(CONFIG_SYS_RAMBOOT)
456 #undef CONFIG_CMD_ENV
457 #undef CONFIG_CMD_LOADS
461 #undef CONFIG_WATCHDOG /* watchdog disabled */
464 * Miscellaneous configurable options
466 #define CONFIG_SYS_LONGHELP /* undef to save memory */
467 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
468 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
469 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
471 #if defined(CONFIG_CMD_KGDB)
472 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
474 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
477 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
478 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
479 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
480 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
483 * For booting Linux, the board info and command line data
484 * have to be in the first 8 MB of memory, since this is
485 * the maximum mapped by the Linux kernel during initialization.
487 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
490 * Internal Definitions
494 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
495 #define BOOTFLAG_WARM 0x02 /* Software reboot */
497 #if defined(CONFIG_CMD_KGDB)
498 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
499 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
504 * Environment Configuration
507 /* The mac addresses for all ethernet interface */
508 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
509 #define CONFIG_HAS_ETH0
510 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
511 #define CONFIG_HAS_ETH1
512 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
513 #define CONFIG_HAS_ETH2
514 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
515 #define CONFIG_HAS_ETH3
516 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
519 #define CONFIG_IPADDR 192.168.1.253
521 #define CONFIG_HOSTNAME unknown
522 #define CONFIG_ROOTPATH /nfsroot
523 #define CONFIG_BOOTFILE your.uImage
525 #define CONFIG_SERVERIP 192.168.1.1
526 #define CONFIG_GATEWAYIP 192.168.1.1
527 #define CONFIG_NETMASK 255.255.255.0
529 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
531 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
532 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
534 #define CONFIG_BAUDRATE 115200
536 #define CONFIG_EXTRA_ENV_SETTINGS \
538 "consoledev=ttyCPM\0" \
539 "ramdiskaddr=1000000\0" \
540 "ramdiskfile=your.ramdisk.u-boot\0" \
542 "fdtfile=mpc8560ads.dtb\0"
544 #define CONFIG_NFSBOOTCOMMAND \
545 "setenv bootargs root=/dev/nfs rw " \
546 "nfsroot=$serverip:$rootpath " \
547 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
548 "console=$consoledev,$baudrate $othbootargs;" \
549 "tftp $loadaddr $bootfile;" \
550 "tftp $fdtaddr $fdtfile;" \
551 "bootm $loadaddr - $fdtaddr"
553 #define CONFIG_RAMBOOTCOMMAND \
554 "setenv bootargs root=/dev/ram rw " \
555 "console=$consoledev,$baudrate $othbootargs;" \
556 "tftp $ramdiskaddr $ramdiskfile;" \
557 "tftp $loadaddr $bootfile;" \
558 "tftp $fdtaddr $fdtfile;" \
559 "bootm $loadaddr $ramdiskaddr $fdtaddr"
561 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
563 #endif /* __CONFIG_H */