include/configs/MPC8560ADS.h

   1 /*
   2  * Copyright 2004, 2011 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * mpc8560ads board configuration file
  11  *
  12  * Please refer to doc/README.mpc85xx for more info.
  13  *
  14  * Make sure you change the MAC address and other network params first,
  15  * search for CONFIG_SERVERIP, etc. in this file.
  16  */
  17
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 /* High Level Configuration Options */
  22 #define CONFIG_BOOKE            1       /* BOOKE */
  23 #define CONFIG_E500             1       /* BOOKE e500 family */
  24 #define CONFIG_CPM2             1       /* has CPM2 */
  25 #define CONFIG_MPC8560ADS       1       /* MPC8560ADS board specific */
  26
  27 /*
  28  * default CCARBAR is at 0xff700000
  29  * assume U-Boot is less than 0.5MB
  30  */
  31 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  32
  33 #define CONFIG_PCI_INDIRECT_BRIDGE
  34 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  35 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  36 #undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
  37 #define CONFIG_ENV_OVERWRITE
  38 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  39 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy() */
  40
  41 /*
  42  * sysclk for MPC85xx
  43  *
  44  * Two valid values are:
  45  *    33000000
  46  *    66000000
  47  *
  48  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  49  * is likely the desired value here, so that is now the default.
  50  * The board, however, can run at 66MHz.  In any event, this value
  51  * must match the settings of some switches.  Details can be found
  52  * in the README.mpc85xxads.
  53  */
  54
  55 #ifndef CONFIG_SYS_CLK_FREQ
  56 #define CONFIG_SYS_CLK_FREQ     33000000
  57 #endif
  58
  59 /*
  60  * These can be toggled for performance analysis, otherwise use default.
  61  */
  62 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  63 #define CONFIG_BTB                      /* toggle branch predition */
  64
  65 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions */
  66
  67 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  68 #define CONFIG_SYS_MEMTEST_END          0x00400000
  69
  70 #define CONFIG_SYS_CCSRBAR              0xe0000000
  71 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  72
  73 /* DDR Setup */
  74 #define CONFIG_SYS_FSL_DDR1
  75 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  76 #define CONFIG_DDR_SPD
  77 #undef CONFIG_FSL_DDR_INTERACTIVE
  78
  79 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  80
  81 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  82 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  83
  84 #define CONFIG_NUM_DDR_CONTROLLERS      1
  85 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  86 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  87
  88 /* I2C addresses of SPD EEPROMs */
  89 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  90
  91 /* These are used when DDR doesn't use SPD.  */
  92 #define CONFIG_SYS_SDRAM_SIZE   128             /* DDR is 128MB */
  93 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007      /* 0-128MB */
  94 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000002
  95 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
  96 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  97 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
  98 #define CONFIG_SYS_DDR_MODE             0x00000062      /* DLL,normal,seq,4/2.5 */
  99 #define CONFIG_SYS_DDR_INTERVAL 0x05200100      /* autocharge,no open page */
 100
 101 /*
 102  * SDRAM on the Local Bus
 103  */
 104 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 105 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 106
 107 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH 16M */
 108 #define CONFIG_SYS_BR0_PRELIM           0xff001801      /* port size 32bit */
 109
 110 #define CONFIG_SYS_OR0_PRELIM           0xff006ff7      /* 16MB Flash */
 111 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 112 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 113 #undef  CONFIG_SYS_FLASH_CHECKSUM
 114 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 115 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 116
 117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 118
 119 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 120 #define CONFIG_SYS_RAMBOOT
 121 #else
 122 #undef  CONFIG_SYS_RAMBOOT
 123 #endif
 124
 125 #define CONFIG_FLASH_CFI_DRIVER
 126 #define CONFIG_SYS_FLASH_CFI
 127 #define CONFIG_SYS_FLASH_EMPTY_INFO
 128
 129 #undef CONFIG_CLOCKS_IN_MHZ
 130
 131 /*
 132  * Local Bus Definitions
 133  */
 134
 135 /*
 136  * Base Register 2 and Option Register 2 configure SDRAM.
 137  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 138  *
 139  * For BR2, need:
 140  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 141  *    port-size = 32-bits = BR2[19:20] = 11
 142  *    no parity checking = BR2[21:22] = 00
 143  *    SDRAM for MSEL = BR2[24:26] = 011
 144  *    Valid = BR[31] = 1
 145  *
 146  * 0    4    8    12   16   20   24   28
 147  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 148  *
 149  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 150  * FIXME: the top 17 bits of BR2.
 151  */
 152
 153 #define CONFIG_SYS_BR2_PRELIM           0xf0001861
 154
 155 /*
 156  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 157  *
 158  * For OR2, need:
 159  *    64MB mask for AM, OR2[0:7] = 1111 1100
 160  *                 XAM, OR2[17:18] = 11
 161  *    9 columns OR2[19-21] = 010
 162  *    13 rows   OR2[23-25] = 100
 163  *    EAD set for extra time OR[31] = 1
 164  *
 165  * 0    4    8    12   16   20   24   28
 166  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 167  */
 168
 169 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 170
 171 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 172 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 173 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 174 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer prescal*/
 175
 176 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_BSMA1516        \
 177                                 | LSDMR_RFCR5           \
 178                                 | LSDMR_PRETOACT3       \
 179                                 | LSDMR_ACTTORW3        \
 180                                 | LSDMR_BL8             \
 181                                 | LSDMR_WRC2            \
 182                                 | LSDMR_CL3             \
 183                                 | LSDMR_RFEN            \
 184                                 )
 185
 186 /*
 187  * SDRAM Controller configuration sequence.
 188  */
 189 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 190 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 191 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 192 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 193 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 194
 195 /*
 196  * 32KB, 8-bit wide for ADS config reg
 197  */
 198 #define CONFIG_SYS_BR4_PRELIM          0xf8000801
 199 #define CONFIG_SYS_OR4_PRELIM           0xffffe1f1
 200 #define CONFIG_SYS_BCSR         (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
 201
 202 #define CONFIG_SYS_INIT_RAM_LOCK        1
 203 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 204 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 205
 206 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 207 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 208
 209 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 210 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 211
 212 /* Serial Port */
 213 #define CONFIG_CONS_ON_SCC      /* define if console on SCC */
 214 #undef  CONFIG_CONS_NONE        /* define if console on something else */
 215 #define CONFIG_CONS_INDEX       1  /* which serial channel for console */
 216
 217 #define CONFIG_BAUDRATE         115200
 218
 219 #define CONFIG_SYS_BAUDRATE_TABLE  \
 220         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 221
 222 /*
 223  * I2C
 224  */
 225 #define CONFIG_SYS_I2C
 226 #define CONFIG_SYS_I2C_FSL
 227 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 228 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 229 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 230 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 231
 232 /* RapidIO MMU */
 233 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000      /* base address */
 234 #define CONFIG_SYS_RIO_MEM_BUS  0xc0000000      /* base address */
 235 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
 236 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 237
 238 /*
 239  * General PCI
 240  * Memory space is mapped 1-1, but I/O space must start from 0.
 241  */
 242 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 243 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 244 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 245 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 246 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 247 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 248 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 249 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000        /* 1M */
 250
 251 #if defined(CONFIG_PCI)
 252 #undef CONFIG_EEPRO100
 253 #undef CONFIG_TULIP
 254
 255 #if !defined(CONFIG_PCI_PNP)
 256     #define PCI_ENET0_IOADDR    0xe0000000
 257     #define PCI_ENET0_MEMADDR   0xe0000000
 258     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 259 #endif
 260
 261 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 262 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 263
 264 #endif  /* CONFIG_PCI */
 265
 266 #ifdef CONFIG_TSEC_ENET
 267
 268 #ifndef CONFIG_MII
 269 #define CONFIG_MII              1       /* MII PHY management */
 270 #endif
 271 #define CONFIG_TSEC1    1
 272 #define CONFIG_TSEC1_NAME       "TSEC0"
 273 #define CONFIG_TSEC2    1
 274 #define CONFIG_TSEC2_NAME       "TSEC1"
 275 #define TSEC1_PHY_ADDR          0
 276 #define TSEC2_PHY_ADDR          1
 277 #define TSEC1_PHYIDX            0
 278 #define TSEC2_PHYIDX            0
 279 #define TSEC1_FLAGS             TSEC_GIGABIT
 280 #define TSEC2_FLAGS             TSEC_GIGABIT
 281
 282 /* Options are: TSEC[0-1] */
 283 #define CONFIG_ETHPRIME         "TSEC0"
 284
 285 #endif /* CONFIG_TSEC_ENET */
 286
 287 #ifdef CONFIG_ETHER_ON_FCC              /* CPM FCC Ethernet */
 288
 289 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 290 #define CONFIG_ETHER_INDEX      2       /* which channel for ether */
 291
 292 #if (CONFIG_ETHER_INDEX == 2)
 293   /*
 294    * - Rx-CLK is CLK13
 295    * - Tx-CLK is CLK14
 296    * - Select bus for bd/buffers
 297    * - Full duplex
 298    */
 299   #define CONFIG_SYS_CMXFCR_MASK2      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 300   #define CONFIG_SYS_CMXFCR_VALUE2     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 301   #define CONFIG_SYS_CPMFCR_RAMTYPE    0
 302   #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
 303   #define FETH2_RST             0x01
 304 #elif (CONFIG_ETHER_INDEX == 3)
 305   /* need more definitions here for FE3 */
 306   #define FETH3_RST             0x80
 307 #endif                                  /* CONFIG_ETHER_INDEX */
 308
 309 #ifndef CONFIG_MII
 310 #define CONFIG_MII              1       /* MII PHY management */
 311 #endif
 312
 313 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 314
 315 /*
 316  * GPIO pins used for bit-banged MII communications
 317  */
 318 #define MDIO_PORT       2               /* Port C */
 319 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 320                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 321 #define MDC_DECLARE     MDIO_DECLARE
 322
 323 #define MDIO_ACTIVE     (iop->pdir |=  0x00400000)
 324 #define MDIO_TRISTATE   (iop->pdir &= ~0x00400000)
 325 #define MDIO_READ       ((iop->pdat &  0x00400000) != 0)
 326
 327 #define MDIO(bit)       if(bit) iop->pdat |=  0x00400000; \
 328                         else    iop->pdat &= ~0x00400000
 329
 330 #define MDC(bit)        if(bit) iop->pdat |=  0x00200000; \
 331                         else    iop->pdat &= ~0x00200000
 332
 333 #define MIIDELAY        udelay(1)
 334
 335 #endif
 336
 337 /*
 338  * Environment
 339  */
 340 #ifndef CONFIG_SYS_RAMBOOT
 341   #define CONFIG_ENV_IS_IN_FLASH        1
 342   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + 0x40000)
 343   #define CONFIG_ENV_SECT_SIZE  0x40000 /* 256K(one sector) for env */
 344   #define CONFIG_ENV_SIZE               0x2000
 345 #else
 346   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now */
 347   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only */
 348   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 349   #define CONFIG_ENV_SIZE               0x2000
 350 #endif
 351
 352 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 353 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 354
 355 /*
 356  * BOOTP options
 357  */
 358 #define CONFIG_BOOTP_BOOTFILESIZE
 359 #define CONFIG_BOOTP_BOOTPATH
 360 #define CONFIG_BOOTP_GATEWAY
 361 #define CONFIG_BOOTP_HOSTNAME
 362
 363 /*
 364  * Command line configuration.
 365  */
 366 #define CONFIG_CMD_IRQ
 367 #define CONFIG_CMD_REGINFO
 368
 369 #if defined(CONFIG_PCI)
 370     #define CONFIG_CMD_PCI
 371 #endif
 372
 373 #if defined(CONFIG_ETHER_ON_FCC)
 374 #endif
 375
 376 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 377
 378 /*
 379  * Miscellaneous configurable options
 380  */
 381 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 382 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 383 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 384 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 385
 386 #if defined(CONFIG_CMD_KGDB)
 387     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 388 #else
 389     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 390 #endif
 391
 392 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 393 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 394 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 395
 396 /*
 397  * For booting Linux, the board info and command line data
 398  * have to be in the first 64 MB of memory, since this is
 399  * the maximum mapped by the Linux kernel during initialization.
 400  */
 401 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 402 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 403
 404 #if defined(CONFIG_CMD_KGDB)
 405 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 406 #endif
 407
 408 /*
 409  * Environment Configuration
 410  */
 411 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 412 #define CONFIG_HAS_ETH0
 413 #define CONFIG_HAS_ETH1
 414 #define CONFIG_HAS_ETH2
 415 #define CONFIG_HAS_ETH3
 416 #endif
 417
 418 #define CONFIG_IPADDR    192.168.1.253
 419
 420 #define CONFIG_HOSTNAME         unknown
 421 #define CONFIG_ROOTPATH         "/nfsroot"
 422 #define CONFIG_BOOTFILE         "your.uImage"
 423
 424 #define CONFIG_SERVERIP  192.168.1.1
 425 #define CONFIG_GATEWAYIP 192.168.1.1
 426 #define CONFIG_NETMASK   255.255.255.0
 427
 428 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 429
 430 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 431
 432 #define CONFIG_BAUDRATE 115200
 433
 434 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 435         "netdev=eth0\0"                                                 \
 436         "consoledev=ttyCPM\0"                                           \
 437         "ramdiskaddr=1000000\0"                                         \
 438         "ramdiskfile=your.ramdisk.u-boot\0"                             \
 439         "fdtaddr=400000\0"                                              \
 440         "fdtfile=mpc8560ads.dtb\0"
 441
 442 #define CONFIG_NFSBOOTCOMMAND                                           \
 443         "setenv bootargs root=/dev/nfs rw "                             \
 444                 "nfsroot=$serverip:$rootpath "                          \
 445                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 446                 "console=$consoledev,$baudrate $othbootargs;"           \
 447         "tftp $loadaddr $bootfile;"                                     \
 448         "tftp $fdtaddr $fdtfile;"                                       \
 449         "bootm $loadaddr - $fdtaddr"
 450
 451 #define CONFIG_RAMBOOTCOMMAND \
 452         "setenv bootargs root=/dev/ram rw "                             \
 453                 "console=$consoledev,$baudrate $othbootargs;"           \
 454         "tftp $ramdiskaddr $ramdiskfile;"                               \
 455         "tftp $loadaddr $bootfile;"                                     \
 456         "tftp $fdtaddr $fdtfile;"                                       \
 457         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 458
 459 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 460
 461 #endif  /* __CONFIG_H */