include/configs/MPC8568MDS.h

   1 /*
   2  * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * mpc8568mds board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  14
  15 #define CONFIG_SYS_SRIO
  16 #define CONFIG_SRIO1                    /* SRIO port 1 */
  17
  18 #define CONFIG_PCI1             1       /* PCI controller */
  19 #define CONFIG_PCIE1            1       /* PCIE controller */
  20 #define CONFIG_FSL_PCI_INIT     1       /* use common fsl pci init code */
  21 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  22 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  23 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  24 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  25 #define CONFIG_QE                       /* Enable QE */
  26 #define CONFIG_ENV_OVERWRITE
  27
  28 #ifndef __ASSEMBLY__
  29 extern unsigned long get_clock_freq(void);
  30 #endif                                            /*Replace a call to get_clock_freq (after it is implemented)*/
  31 #define CONFIG_SYS_CLK_FREQ     66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
  32
  33 /*
  34  * These can be toggled for performance analysis, otherwise use default.
  35  */
  36 #define CONFIG_L2_CACHE                         /* toggle L2 cache      */
  37 #define CONFIG_BTB                              /* toggle branch predition */
  38
  39 /*
  40  * Only possible on E500 Version 2 or newer cores.
  41  */
  42 #define CONFIG_ENABLE_36BIT_PHYS        1
  43
  44 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  45
  46 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  47 #define CONFIG_SYS_MEMTEST_END          0x00400000
  48
  49 #define CONFIG_SYS_CCSRBAR              0xe0000000
  50 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  51
  52 /* DDR Setup */
  53 #undef CONFIG_FSL_DDR_INTERACTIVE
  54 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
  55 #define CONFIG_DDR_SPD
  56 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  57
  58 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  59
  60 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  61 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  62
  63 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  64 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  65
  66 /* I2C addresses of SPD EEPROMs */
  67 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  68
  69 /* Make sure required options are set */
  70 #ifndef CONFIG_SPD_EEPROM
  71 #error ("CONFIG_SPD_EEPROM is required")
  72 #endif
  73
  74 #undef CONFIG_CLOCKS_IN_MHZ
  75
  76 /*
  77  * Local Bus Definitions
  78  */
  79
  80 /*
  81  * FLASH on the Local Bus
  82  * Two banks, 8M each, using the CFI driver.
  83  * Boot from BR0/OR0 bank at 0xff00_0000
  84  * Alternate BR1/OR1 bank at 0xff80_0000
  85  *
  86  * BR0, BR1:
  87  *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  88  *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  89  *    Port Size = 16 bits = BRx[19:20] = 10
  90  *    Use GPCM = BRx[24:26] = 000
  91  *    Valid = BRx[31] = 1
  92  *
  93  * 0    4    8    12   16   20   24   28
  94  * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
  95  * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
  96  *
  97  * OR0, OR1:
  98  *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  99  *    Reserved ORx[17:18] = 11, confusion here?
 100  *    CSNT = ORx[20] = 1
 101  *    ACS = half cycle delay = ORx[21:22] = 11
 102  *    SCY = 6 = ORx[24:27] = 0110
 103  *    TRLX = use relaxed timing = ORx[29] = 1
 104  *    EAD = use external address latch delay = OR[31] = 1
 105  *
 106  * 0    4    8    12   16   20   24   28
 107  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 108  */
 109 #define CONFIG_SYS_BCSR_BASE            0xf8000000
 110
 111 #define CONFIG_SYS_FLASH_BASE           0xfe000000      /* start of FLASH 32M */
 112
 113 /*Chip select 0 - Flash*/
 114 #define CONFIG_SYS_BR0_PRELIM           0xfe001001
 115 #define CONFIG_SYS_OR0_PRELIM           0xfe006ff7
 116
 117 /*Chip slelect 1 - BCSR*/
 118 #define CONFIG_SYS_BR1_PRELIM           0xf8000801
 119 #define CONFIG_SYS_OR1_PRELIM           0xffffe9f7
 120
 121 /*#define CONFIG_SYS_FLASH_BANKS_LIST   {0xff800000, CONFIG_SYS_FLASH_BASE} */
 122 #define CONFIG_SYS_MAX_FLASH_BANKS              1               /* number of banks */
 123 #define CONFIG_SYS_MAX_FLASH_SECT               512             /* sectors per device */
 124 #undef  CONFIG_SYS_FLASH_CHECKSUM
 125 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 126 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 127
 128 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 129
 130 #define CONFIG_FLASH_CFI_DRIVER
 131 #define CONFIG_SYS_FLASH_CFI
 132 #define CONFIG_SYS_FLASH_EMPTY_INFO
 133
 134 /*
 135  * SDRAM on the LocalBus
 136  */
 137 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM        */
 138 #define CONFIG_SYS_LBC_SDRAM_SIZE       64                      /* LBC SDRAM is 64MB */
 139
 140 /*Chip select 2 - SDRAM*/
 141 #define CONFIG_SYS_BR2_PRELIM      0xf0001861
 142 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 143
 144 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* LB clock ratio reg */
 145 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg */
 146 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 147 #define CONFIG_SYS_LBC_MRTPR            0x00000000      /* LB refresh timer prescal*/
 148
 149 /*
 150  * Common settings for all Local Bus SDRAM commands.
 151  * At run time, either BSMA1516 (for CPU 1.1)
 152  *                  or BSMA1617 (for CPU 1.0) (old)
 153  * is OR'ed in too.
 154  */
 155 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 156                                 | LSDMR_PRETOACT7       \
 157                                 | LSDMR_ACTTORW7        \
 158                                 | LSDMR_BL8             \
 159                                 | LSDMR_WRC4            \
 160                                 | LSDMR_CL3             \
 161                                 | LSDMR_RFEN            \
 162                                 )
 163
 164 /*
 165  * The bcsr registers are connected to CS3 on MDS.
 166  * The new memory map places bcsr at 0xf8000000.
 167  *
 168  * For BR3, need:
 169  *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 170  *    port-size = 8-bits  = BR[19:20] = 01
 171  *    no parity checking  = BR[21:22] = 00
 172  *    GPMC for MSEL       = BR[24:26] = 000
 173  *    Valid               = BR[31]    = 1
 174  *
 175  * 0    4    8    12   16   20   24   28
 176  * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 177  *
 178  * For OR3, need:
 179  *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 180  *    disable buffer ctrl OR[19]    = 0
 181  *    CSNT                OR[20]    = 1
 182  *    ACS                 OR[21:22] = 11
 183  *    XACS                OR[23]    = 1
 184  *    SCY 15 wait states  OR[24:27] = 1111      max is suboptimal but safe
 185  *    SETA                OR[28]    = 0
 186  *    TRLX                OR[29]    = 1
 187  *    EHTR                OR[30]    = 1
 188  *    EAD extra time      OR[31]    = 1
 189  *
 190  * 0    4    8    12   16   20   24   28
 191  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 192  */
 193 #define CONFIG_SYS_BCSR (0xf8000000)
 194
 195 /*Chip slelect 4 - PIB*/
 196 #define CONFIG_SYS_BR4_PRELIM   0xf8008801
 197 #define CONFIG_SYS_OR4_PRELIM   0xffffe9f7
 198
 199 /*Chip select 5 - PIB*/
 200 #define CONFIG_SYS_BR5_PRELIM    0xf8010801
 201 #define CONFIG_SYS_OR5_PRELIM    0xffff69f7
 202
 203 #define CONFIG_SYS_INIT_RAM_LOCK        1
 204 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 205 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000      /* Size of used area in RAM */
 206
 207 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 208 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 209
 210 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 211 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 212
 213 /* Serial Port */
 214 #define CONFIG_CONS_INDEX               1
 215 #define CONFIG_SYS_NS16550_SERIAL
 216 #define CONFIG_SYS_NS16550_REG_SIZE    1
 217 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 218
 219 #define CONFIG_SYS_BAUDRATE_TABLE  \
 220         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 221
 222 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 223 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 224
 225 /*
 226  * I2C
 227  */
 228 #define CONFIG_SYS_I2C
 229 #define CONFIG_SYS_I2C_FSL
 230 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 231 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 232 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 233 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 234 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 235 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 236 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 237 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 238
 239 /*
 240  * General PCI
 241  * Memory Addresses are mapped 1-1. I/O is mapped from 0
 242  */
 243 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 244 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
 245 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 246 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 247 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
 248 #define CONFIG_SYS_PCI1_IO_BUS  0x00000000
 249 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 250 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000      /* 8M */
 251
 252 #define CONFIG_SYS_PCIE1_NAME           "Slot"
 253 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 254 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 255 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 256 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 257 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe2800000
 258 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
 259 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe2800000
 260 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 261
 262 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xC0000000
 263 #define CONFIG_SYS_SRIO1_MEM_BUS        0xC0000000
 264 #define CONFIG_SYS_SRIO1_MEM_PHYS       CONFIG_SYS_SRIO1_MEM_BUS
 265 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 512M */
 266
 267 #ifdef CONFIG_QE
 268 /*
 269  * QE UEC ethernet configuration
 270  */
 271 #define CONFIG_UEC_ETH
 272 #ifndef CONFIG_TSEC_ENET
 273 #define CONFIG_ETHPRIME         "UEC0"
 274 #endif
 275 #define CONFIG_PHY_MODE_NEED_CHANGE
 276 #define CONFIG_eTSEC_MDIO_BUS
 277
 278 #ifdef CONFIG_eTSEC_MDIO_BUS
 279 #define CONFIG_MIIM_ADDRESS     0xE0024520
 280 #endif
 281
 282 #define CONFIG_UEC_ETH1         /* GETH1 */
 283
 284 #ifdef CONFIG_UEC_ETH1
 285 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
 286 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
 287 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16
 288 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 289 #define CONFIG_SYS_UEC1_PHY_ADDR       7
 290 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 291 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 292 #endif
 293
 294 #define CONFIG_UEC_ETH2         /* GETH2 */
 295
 296 #ifdef CONFIG_UEC_ETH2
 297 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
 298 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
 299 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16
 300 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 301 #define CONFIG_SYS_UEC2_PHY_ADDR       1
 302 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 303 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 304 #endif
 305 #endif /* CONFIG_QE */
 306
 307 #if defined(CONFIG_PCI)
 308 #undef CONFIG_EEPRO100
 309 #undef CONFIG_TULIP
 310
 311 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 312 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 313
 314 #endif  /* CONFIG_PCI */
 315
 316 #if defined(CONFIG_TSEC_ENET)
 317
 318 #define CONFIG_MII              1       /* MII PHY management */
 319 #define CONFIG_TSEC1    1
 320 #define CONFIG_TSEC1_NAME       "eTSEC0"
 321 #define CONFIG_TSEC2    1
 322 #define CONFIG_TSEC2_NAME       "eTSEC1"
 323
 324 #define TSEC1_PHY_ADDR          2
 325 #define TSEC2_PHY_ADDR          3
 326
 327 #define TSEC1_PHYIDX            0
 328 #define TSEC2_PHYIDX            0
 329
 330 #define TSEC1_FLAGS             TSEC_GIGABIT
 331 #define TSEC2_FLAGS             TSEC_GIGABIT
 332
 333 /* Options are: eTSEC[0-1] */
 334 #define CONFIG_ETHPRIME         "eTSEC0"
 335
 336 #endif  /* CONFIG_TSEC_ENET */
 337
 338 /*
 339  * Environment
 340  */
 341 #define CONFIG_ENV_IS_IN_FLASH  1
 342 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 343 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 344 #define CONFIG_ENV_SIZE         0x2000
 345
 346 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 347 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 348
 349 /*
 350  * BOOTP options
 351  */
 352 #define CONFIG_BOOTP_BOOTFILESIZE
 353 #define CONFIG_BOOTP_BOOTPATH
 354 #define CONFIG_BOOTP_GATEWAY
 355 #define CONFIG_BOOTP_HOSTNAME
 356
 357 /*
 358  * Command line configuration.
 359  */
 360 #define CONFIG_CMD_IRQ
 361 #define CONFIG_CMD_REGINFO
 362
 363 #if defined(CONFIG_PCI)
 364     #define CONFIG_CMD_PCI
 365 #endif
 366
 367 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 368
 369 /*
 370  * Miscellaneous configurable options
 371  */
 372 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 373 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 374 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 375 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 376 #if defined(CONFIG_CMD_KGDB)
 377 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 378 #else
 379 #define CONFIG_SYS_CBSIZE       256                     /* Console I/O Buffer Size */
 380 #endif
 381 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 382 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 383 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 384
 385 /*
 386  * For booting Linux, the board info and command line data
 387  * have to be in the first 64 MB of memory, since this is
 388  * the maximum mapped by the Linux kernel during initialization.
 389  */
 390 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 391 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 392
 393 #if defined(CONFIG_CMD_KGDB)
 394 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 395 #endif
 396
 397 /*
 398  * Environment Configuration
 399  */
 400
 401 /* The mac addresses for all ethernet interface */
 402 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
 403 #define CONFIG_HAS_ETH0
 404 #define CONFIG_HAS_ETH1
 405 #define CONFIG_HAS_ETH2
 406 #define CONFIG_HAS_ETH3
 407 #endif
 408
 409 #define CONFIG_IPADDR    192.168.1.253
 410
 411 #define CONFIG_HOSTNAME  unknown
 412 #define CONFIG_ROOTPATH  "/nfsroot"
 413 #define CONFIG_BOOTFILE  "your.uImage"
 414
 415 #define CONFIG_SERVERIP  192.168.1.1
 416 #define CONFIG_GATEWAYIP 192.168.1.1
 417 #define CONFIG_NETMASK   255.255.255.0
 418
 419 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 420
 421 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 422
 423 #define CONFIG_BAUDRATE 115200
 424
 425 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 426    "netdev=eth0\0"                                                      \
 427    "consoledev=ttyS0\0"                                                 \
 428    "ramdiskaddr=600000\0"                                               \
 429    "ramdiskfile=your.ramdisk.u-boot\0"                                  \
 430    "fdtaddr=400000\0"                                                   \
 431    "fdtfile=your.fdt.dtb\0"                                             \
 432    "nfsargs=setenv bootargs root=/dev/nfs rw "                          \
 433       "nfsroot=$serverip:$rootpath "                                    \
 434       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 435       "console=$consoledev,$baudrate $othbootargs\0"                    \
 436    "ramargs=setenv bootargs root=/dev/ram rw "                          \
 437       "console=$consoledev,$baudrate $othbootargs\0"                    \
 438
 439 #define CONFIG_NFSBOOTCOMMAND                                           \
 440    "run nfsargs;"                                                       \
 441    "tftp $loadaddr $bootfile;"                                          \
 442    "tftp $fdtaddr $fdtfile;"                                            \
 443    "bootm $loadaddr - $fdtaddr"
 444
 445 #define CONFIG_RAMBOOTCOMMAND \
 446    "run ramargs;"                                                       \
 447    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 448    "tftp $loadaddr $bootfile;"                                          \
 449    "bootm $loadaddr $ramdiskaddr"
 450
 451 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 452
 453 #endif  /* __CONFIG_H */