include/configs/MUSENKI.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  *
  26  * Configuration settings for the MUSENKI board.
  27  *
  28  */
  29
  30 /* ------------------------------------------------------------------------- */
  31
  32 /*
  33  * board/config.h - configuration options, board specific
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43
  44 #define CONFIG_MPC824X          1
  45 #define CONFIG_MPC8245          1
  46 #define CONFIG_MUSENKI          1
  47
  48
  49 #define CONFIG_CONS_INDEX       1
  50 #define CONFIG_BAUDRATE         9600
  51 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
  52
  53 #define CONFIG_BOOTDELAY        5
  54
  55 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL)
  56
  57 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any)       */
  58
  59 #include <cmd_confdefs.h>
  60
  61
  62 /*
  63  * Miscellaneous configurable options
  64  */
  65 #undef CFG_LONGHELP                     /* undef to save memory         */
  66 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
  67 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
  68
  69 /* Print Buffer Size
  70  */
  71 #define CFG_PBSIZE      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
  72 #define CFG_MAXARGS     8               /* Max number of command args   */
  73 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
  74 #define CFG_LOAD_ADDR   0x00100000      /* Default load address         */
  75
  76 /*-----------------------------------------------------------------------
  77  * PCI stuff
  78  *-----------------------------------------------------------------------
  79  */
  80 #define CONFIG_PCI                      /* include pci support          */
  81 #undef CONFIG_PCI_PNP
  82
  83 #define CONFIG_NET_MULTI                /* Multi ethernet cards support */
  84
  85 #define CONFIG_TULIP
  86
  87 #define PCI_ENET0_IOADDR                0x80000000
  88 #define PCI_ENET0_MEMADDR               0x80000000
  89 #define PCI_ENET1_IOADDR                0x81000000
  90 #define PCI_ENET1_MEMADDR               0x81000000
  91
  92
  93 /*-----------------------------------------------------------------------
  94  * Start addresses for the final memory configuration
  95  * (Set up by the startup code)
  96  * Please note that CFG_SDRAM_BASE _must_ start at 0
  97  */
  98 #define CFG_SDRAM_BASE      0x00000000
  99
 100 #define CFG_FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank on RCS#0 */
 101 #define CFG_FLASH_BASE1_PRELIM      0xFF000000      /* FLASH bank on RCS#1 */
 102 #define CFG_FLASH_BASE  CFG_FLASH_BASE0_PRELIM
 103
 104 /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
 105  * reset vector is actually located at FFB00100, but the 8245
 106  * takes care of us.
 107  */
 108 #define CFG_RESET_ADDRESS   0xFFF00100
 109
 110 #define CFG_EUMB_ADDR       0xFC000000
 111
 112 #define CFG_MONITOR_BASE    TEXT_BASE
 113 #define CFG_MONITOR_LEN     (256 << 10) /* Reserve 256 kB for Monitor   */
 114 #define CFG_MALLOC_LEN      (128 << 10) /* Reserve 128 kB for malloc()  */
 115
 116 #define CFG_MEMTEST_START   0x00004000  /* memtest works on             */
 117 #define CFG_MEMTEST_END     0x02000000  /* 0 ... 32 MB in DRAM          */
 118
 119         /* Maximum amount of RAM.
 120          */
 121 #define CFG_MAX_RAM_SIZE    0x08000000  /* 0 .. 128 MB of (S)DRAM */
 122
 123
 124 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 125 #undef CFG_RAMBOOT
 126 #else
 127 #define CFG_RAMBOOT
 128 #endif
 129
 130 /*
 131  * NS16550 Configuration
 132  */
 133 #define CFG_NS16550
 134 #define CFG_NS16550_SERIAL
 135
 136 #define CFG_NS16550_REG_SIZE    1
 137
 138 #define CFG_NS16550_CLK         get_bus_freq(0)
 139
 140 #define CFG_NS16550_COM1        (CFG_EUMB_ADDR + 0x4500)
 141 #define CFG_NS16550_COM2        (CFG_EUMB_ADDR + 0x4600)
 142
 143 /*-----------------------------------------------------------------------
 144  * Definitions for initial stack pointer and data area
 145  */
 146
 147 /* #define CFG_MONITOR_BASE        TEXT_BASE */
 148 /*#define CFG_GBL_DATA_SIZE    256*/
 149 #define CFG_GBL_DATA_SIZE      128
 150 #define CFG_INIT_RAM_ADDR     0x40000000
 151 #define CFG_INIT_RAM_END      0x1000
 152 #define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 153
 154
 155 /*
 156  * Low Level Configuration Settings
 157  * (address mappings, register initial values, etc.)
 158  * You should know what you are doing if you make changes here.
 159  * For the detail description refer to the MPC8240 user's manual.
 160  */
 161
 162 #define CONFIG_SYS_CLK_FREQ  33333333   /* external frequency to pll */
 163 #define CFG_HZ               1000
 164
 165         /* Bit-field values for MCCR1.
 166          */
 167 #define CFG_ROMNAL          7
 168 #define CFG_ROMFAL          11
 169 #define CFG_DBUS_SIZE       0x3
 170
 171         /* Bit-field values for MCCR2.
 172          */
 173 #define CFG_TSWAIT          0x5             /* Transaction Start Wait States timer */
 174 #define CFG_REFINT          0x400           /* Refresh interval FIXME: was 0t430                */
 175
 176         /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 177          */
 178 #define CFG_BSTOPRE         121
 179
 180         /* Bit-field values for MCCR3.
 181          */
 182 #define CFG_REFREC          8       /* Refresh to activate interval */
 183
 184         /* Bit-field values for MCCR4.
 185          */
 186 #define CFG_PRETOACT        3       /* Precharge to activate interval FIXME: was 2      */
 187 #define CFG_ACTTOPRE        5       /* Activate to Precharge interval FIXME: was 5      */
 188 #define CFG_ACTORW          3           /* FIXME was 2 */
 189 #define CFG_SDMODE_CAS_LAT  3       /* SDMODE CAS latancy */
 190 #define CFG_SDMODE_WRAP     0       /* SDMODE wrap type */
 191 #define CFG_REGISTERD_TYPE_BUFFER 1
 192 #define CFG_EXTROM          1
 193 #define CFG_REGDIMM         0
 194
 195 #define CFG_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
 196
 197 #define CFG_SDRAM_DSCD  0x20    /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
 198
 199 /* Memory bank settings.
 200  * Only bits 20-29 are actually used from these vales to set the
 201  * start/end addresses. The upper two bits will always be 0, and the lower
 202  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 203  * address. Refer to the MPC8240 book.
 204  */
 205
 206 #define CFG_BANK0_START     0x00000000
 207 #define CFG_BANK0_END       (CFG_MAX_RAM_SIZE - 1)
 208 #define CFG_BANK0_ENABLE    1
 209 #define CFG_BANK1_START     0x3ff00000
 210 #define CFG_BANK1_END       0x3fffffff
 211 #define CFG_BANK1_ENABLE    0
 212 #define CFG_BANK2_START     0x3ff00000
 213 #define CFG_BANK2_END       0x3fffffff
 214 #define CFG_BANK2_ENABLE    0
 215 #define CFG_BANK3_START     0x3ff00000
 216 #define CFG_BANK3_END       0x3fffffff
 217 #define CFG_BANK3_ENABLE    0
 218 #define CFG_BANK4_START     0x3ff00000
 219 #define CFG_BANK4_END       0x3fffffff
 220 #define CFG_BANK4_ENABLE    0
 221 #define CFG_BANK5_START     0x3ff00000
 222 #define CFG_BANK5_END       0x3fffffff
 223 #define CFG_BANK5_ENABLE    0
 224 #define CFG_BANK6_START     0x3ff00000
 225 #define CFG_BANK6_END       0x3fffffff
 226 #define CFG_BANK6_ENABLE    0
 227 #define CFG_BANK7_START     0x3ff00000
 228 #define CFG_BANK7_END       0x3fffffff
 229 #define CFG_BANK7_ENABLE    0
 230
 231 #define CFG_ODCR            0xff
 232
 233 #define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 234 #define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 235
 236 #define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 237 #define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 238
 239 #define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 240 #define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 241
 242 #define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 243 #define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 244
 245 #define CFG_DBAT0L  CFG_IBAT0L
 246 #define CFG_DBAT0U  CFG_IBAT0U
 247 #define CFG_DBAT1L  CFG_IBAT1L
 248 #define CFG_DBAT1U  CFG_IBAT1U
 249 #define CFG_DBAT2L  CFG_IBAT2L
 250 #define CFG_DBAT2U  CFG_IBAT2U
 251 #define CFG_DBAT3L  CFG_IBAT3L
 252 #define CFG_DBAT3U  CFG_IBAT3U
 253
 254 /*
 255  * For booting Linux, the board info and command line data
 256  * have to be in the first 8 MB of memory, since this is
 257  * the maximum mapped by the Linux kernel during initialization.
 258  */
 259 #define CFG_BOOTMAPSZ       (8 << 20)   /* Initial Memory map for Linux */
 260
 261 /*-----------------------------------------------------------------------
 262  * FLASH organization
 263  */
 264 #define CFG_MAX_FLASH_BANKS     2       /* Max number of flash banks            */
 265 #define CFG_MAX_FLASH_SECT      64      /* Max number of sectors per flash      */
 266
 267 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms) */
 268 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms) */
 269
 270
 271         /* Warining: environment is not EMBEDDED in the U-Boot code.
 272          * It's stored in flash separately.
 273          */
 274 #define CFG_ENV_IS_IN_FLASH         1
 275 #define CFG_ENV_ADDR            0xFFFF0000
 276 #define CFG_ENV_SIZE            0x00010000 /* Size of the Environment           */
 277 #define CFG_ENV_SECT_SIZE       0x20000 /* Size of the Environment Sector       */
 278
 279 /*-----------------------------------------------------------------------
 280  * Cache Configuration
 281  */
 282 #define CFG_CACHELINE_SIZE      32
 283 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 284 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value        */
 285 #endif
 286
 287 /*
 288  * Internal Definitions
 289  *
 290  * Boot Flags
 291  */
 292 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
 293 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 294
 295 #endif  /* __CONFIG_H */