include/configs/P2041RDB.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * P2041 RDB board configuration file
  25  * Also supports P2040 RDB
  26  */
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #define CONFIG_P2041RDB
  31 #define CONFIG_PHYS_64BIT
  32 #define CONFIG_PPC_P2041
  33
  34 #ifdef CONFIG_RAMBOOT_PBL
  35 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  36 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  37 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
  38 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
  39 #endif
  40
  41 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  42 /* Set 1M boot space */
  43 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  45                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  46 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  47 #define CONFIG_SYS_NO_FLASH
  48 #endif
  49
  50 /* High Level Configuration Options */
  51 #define CONFIG_BOOKE
  52 #define CONFIG_E500                     /* BOOKE e500 family */
  53 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  54 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  55 #define CONFIG_MPC85xx                  /* MPC85xx/PQ3 platform */
  56 #define CONFIG_FSL_CORENET              /* Freescale CoreNet platform */
  57 #define CONFIG_MP                       /* support multiple processors */
  58
  59 #ifndef CONFIG_SYS_TEXT_BASE
  60 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  61 #endif
  62
  63 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  64 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  65 #endif
  66
  67 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  68 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  69 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  70 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  71 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  72 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  73 #define CONFIG_PCIE3                    /* PCIE controler 3 */
  74 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  75 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  76
  77 #define CONFIG_SYS_SRIO
  78 #define CONFIG_SRIO1                    /* SRIO port 1 */
  79 #define CONFIG_SRIO2                    /* SRIO port 2 */
  80 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  81 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  82
  83 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  84
  85 #define CONFIG_ENV_OVERWRITE
  86
  87 #ifdef CONFIG_SYS_NO_FLASH
  88 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  89 #define CONFIG_ENV_IS_NOWHERE
  90 #endif
  91 #else
  92 #define CONFIG_FLASH_CFI_DRIVER
  93 #define CONFIG_SYS_FLASH_CFI
  94 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  95 #endif
  96
  97 #if defined(CONFIG_SPIFLASH)
  98         #define CONFIG_SYS_EXTRA_ENV_RELOC
  99         #define CONFIG_ENV_IS_IN_SPI_FLASH
 100         #define CONFIG_ENV_SPI_BUS              0
 101         #define CONFIG_ENV_SPI_CS               0
 102         #define CONFIG_ENV_SPI_MAX_HZ           10000000
 103         #define CONFIG_ENV_SPI_MODE             0
 104         #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 105         #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 106         #define CONFIG_ENV_SECT_SIZE            0x10000
 107 #elif defined(CONFIG_SDCARD)
 108         #define CONFIG_SYS_EXTRA_ENV_RELOC
 109         #define CONFIG_ENV_IS_IN_MMC
 110         #define CONFIG_FSL_FIXED_MMC_LOCATION
 111         #define CONFIG_SYS_MMC_ENV_DEV          0
 112         #define CONFIG_ENV_SIZE                 0x2000
 113         #define CONFIG_ENV_OFFSET               (512 * 1097)
 114 #elif defined(CONFIG_NAND)
 115 #define CONFIG_SYS_EXTRA_ENV_RELOC
 116 #define CONFIG_ENV_IS_IN_NAND
 117 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 118 #define CONFIG_ENV_OFFSET               (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 119 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 120 #define CONFIG_ENV_IS_IN_REMOTE
 121 #define CONFIG_ENV_ADDR         0xffe20000
 122 #define CONFIG_ENV_SIZE         0x2000
 123 #elif defined(CONFIG_ENV_IS_NOWHERE)
 124 #define CONFIG_ENV_SIZE         0x2000
 125 #else
 126         #define CONFIG_ENV_IS_IN_FLASH
 127         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
 128                         - CONFIG_ENV_SECT_SIZE)
 129         #define CONFIG_ENV_SIZE         0x2000
 130         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 131 #endif
 132
 133 #ifndef __ASSEMBLY__
 134 unsigned long get_board_sys_clk(unsigned long dummy);
 135 #endif
 136 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
 137
 138 /*
 139  * These can be toggled for performance analysis, otherwise use default.
 140  */
 141 #define CONFIG_SYS_CACHE_STASHING
 142 #define CONFIG_BACKSIDE_L2_CACHE
 143 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 144 #define CONFIG_BTB                      /* toggle branch predition */
 145
 146 #define CONFIG_ENABLE_36BIT_PHYS
 147
 148 #ifdef CONFIG_PHYS_64BIT
 149 #define CONFIG_ADDR_MAP
 150 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 151 #endif
 152
 153 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 154 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 155 #define CONFIG_SYS_MEMTEST_END          0x00400000
 156 #define CONFIG_SYS_ALT_MEMTEST
 157 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 158
 159 /*
 160  *  Config the L3 Cache as L3 SRAM
 161  */
 162 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 163 #ifdef CONFIG_PHYS_64BIT
 164 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
 165                 CONFIG_RAMBOOT_TEXT_BASE)
 166 #else
 167 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 168 #endif
 169 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 170 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 171
 172 #ifdef CONFIG_PHYS_64BIT
 173 #define CONFIG_SYS_DCSRBAR              0xf0000000
 174 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 175 #endif
 176
 177 /* EEPROM */
 178 #define CONFIG_ID_EEPROM
 179 #define CONFIG_SYS_I2C_EEPROM_NXID
 180 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 181 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 182 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 183
 184 /*
 185  * DDR Setup
 186  */
 187 #define CONFIG_VERY_BIG_RAM
 188 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 189 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 190
 191 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 192 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 193
 194 #define CONFIG_DDR_SPD
 195 #define CONFIG_FSL_DDR3
 196
 197 #define CONFIG_SYS_SPD_BUS_NUM  0
 198 #define SPD_EEPROM_ADDRESS      0x52
 199 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 200
 201 /*
 202  * Local Bus Definitions
 203  */
 204
 205 /* Set the local bus clock 1/8 of platform clock */
 206 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 207
 208 /*
 209  * This board doesn't have a promjet connector.
 210  * However, it uses commone corenet board LAW and TLB.
 211  * It is necessary to use the same start address with proper offset.
 212  */
 213 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 214 #ifdef CONFIG_PHYS_64BIT
 215 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 216 #else
 217 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 218 #endif
 219
 220 #define CONFIG_SYS_FLASH_BR_PRELIM \
 221                 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 222                 BR_PS_16 | BR_V)
 223 #define CONFIG_SYS_FLASH_OR_PRELIM \
 224                 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 225                  | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 226
 227 #define CONFIG_FSL_CPLD
 228 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
 229 #ifdef CONFIG_PHYS_64BIT
 230 #define CPLD_BASE_PHYS          0xfffdf0000ull
 231 #else
 232 #define CPLD_BASE_PHYS          CPLD_BASE
 233 #endif
 234
 235 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
 236 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 237
 238 #define PIXIS_LBMAP_SWITCH      7
 239 #define PIXIS_LBMAP_MASK        0xf0
 240 #define PIXIS_LBMAP_SHIFT       4
 241 #define PIXIS_LBMAP_ALTBANK     0x40
 242
 243 #define CONFIG_SYS_FLASH_QUIET_TEST
 244 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 245
 246 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 247 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 248 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Erase Timeout (ms) */
 249 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Write Timeout (ms) */
 250
 251 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 252
 253 #if defined(CONFIG_RAMBOOT_PBL)
 254 #define CONFIG_SYS_RAMBOOT
 255 #endif
 256
 257 #define CONFIG_NAND_FSL_ELBC
 258 /* Nand Flash */
 259 #ifdef CONFIG_NAND_FSL_ELBC
 260 #define CONFIG_SYS_NAND_BASE            0xffa00000
 261 #ifdef CONFIG_PHYS_64BIT
 262 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 263 #else
 264 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 265 #endif
 266
 267 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 268 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 269 #define CONFIG_MTD_NAND_VERIFY_WRITE
 270 #define CONFIG_CMD_NAND
 271 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 272
 273 /* NAND flash config */
 274 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 275                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 276                                | BR_PS_8               /* Port Size = 8 bit */ \
 277                                | BR_MS_FCM             /* MSEL = FCM */ \
 278                                | BR_V)                 /* valid */
 279 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 280                                | OR_FCM_PGS            /* Large Page*/ \
 281                                | OR_FCM_CSCT \
 282                                | OR_FCM_CST \
 283                                | OR_FCM_CHT \
 284                                | OR_FCM_SCY_1 \
 285                                | OR_FCM_TRLX \
 286                                | OR_FCM_EHTR)
 287
 288 #ifdef CONFIG_NAND
 289 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 290 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 291 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 292 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 293 #else
 294 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 295 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 296 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 297 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 298 #endif
 299 #else
 300 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 301 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 302 #endif /* CONFIG_NAND_FSL_ELBC */
 303
 304 #define CONFIG_SYS_FLASH_EMPTY_INFO
 305 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 306 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 307
 308 #define CONFIG_BOARD_EARLY_INIT_F
 309 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 310 #define CONFIG_MISC_INIT_R
 311
 312 #define CONFIG_HWCONFIG
 313
 314 /* define to use L1 as initial stack */
 315 #define CONFIG_L1_INIT_RAM
 316 #define CONFIG_SYS_INIT_RAM_LOCK
 317 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 318 #ifdef CONFIG_PHYS_64BIT
 319 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 320 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 321 /* The assembler doesn't like typecast */
 322 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 323         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 324           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 325 #else
 326 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 327 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 328 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 329 #endif
 330 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 331
 332 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 333                                         GENERATED_GBL_DATA_SIZE)
 334 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 335
 336 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 337 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 338
 339 /* Serial Port - controlled on board with jumper J8
 340  * open - index 2
 341  * shorted - index 1
 342  */
 343 #define CONFIG_CONS_INDEX       1
 344 #define CONFIG_SYS_NS16550
 345 #define CONFIG_SYS_NS16550_SERIAL
 346 #define CONFIG_SYS_NS16550_REG_SIZE     1
 347 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 348
 349 #define CONFIG_SYS_BAUDRATE_TABLE       \
 350         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 351
 352 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 353 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 354 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 355 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 356
 357 /* Use the HUSH parser */
 358 #define CONFIG_SYS_HUSH_PARSER
 359
 360 /* pass open firmware flat tree */
 361 #define CONFIG_OF_LIBFDT
 362 #define CONFIG_OF_BOARD_SETUP
 363 #define CONFIG_OF_STDOUT_VIA_ALIAS
 364
 365 /* new uImage format support */
 366 #define CONFIG_FIT
 367 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 368
 369 /* I2C */
 370 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 371 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 372 #define CONFIG_I2C_MULTI_BUS
 373 #define CONFIG_I2C_CMD_TREE
 374 #define CONFIG_SYS_I2C_SPEED            400000
 375 #define CONFIG_SYS_I2C_SLAVE            0x7F
 376 #define CONFIG_SYS_I2C_OFFSET           0x118000
 377 #define CONFIG_SYS_I2C2_OFFSET          0x118100
 378
 379 /*
 380  * RapidIO
 381  */
 382 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 383 #ifdef CONFIG_PHYS_64BIT
 384 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 385 #else
 386 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 387 #endif
 388 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 389
 390 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 391 #ifdef CONFIG_PHYS_64BIT
 392 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 393 #else
 394 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 395 #endif
 396 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 397
 398 /*
 399  * for slave u-boot IMAGE instored in master memory space,
 400  * PHYS must be aligned based on the SIZE
 401  */
 402 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
 403 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
 404 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000        /* 512K */
 405 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
 406 /*
 407  * for slave UCODE and ENV instored in master memory space,
 408  * PHYS must be aligned based on the SIZE
 409  */
 410 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
 411 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 412 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 413
 414 /* slave core release by master*/
 415 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 416 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 417
 418 /*
 419  * SRIO_PCIE_BOOT - SLAVE
 420  */
 421 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 422 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 423 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 424                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 425 #endif
 426
 427 /*
 428  * eSPI - Enhanced SPI
 429  */
 430 #define CONFIG_FSL_ESPI
 431 #define CONFIG_SPI_FLASH
 432 #define CONFIG_SPI_FLASH_SPANSION
 433 #define CONFIG_CMD_SF
 434 #define CONFIG_SF_DEFAULT_SPEED         10000000
 435 #define CONFIG_SF_DEFAULT_MODE          0
 436
 437 /*
 438  * General PCI
 439  * Memory space is mapped 1-1, but I/O space must start from 0.
 440  */
 441
 442 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 443 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 444 #ifdef CONFIG_PHYS_64BIT
 445 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 446 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 447 #else
 448 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 449 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 450 #endif
 451 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 452 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 453 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 454 #ifdef CONFIG_PHYS_64BIT
 455 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 456 #else
 457 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 458 #endif
 459 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 460
 461 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 462 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 463 #ifdef CONFIG_PHYS_64BIT
 464 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 465 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 466 #else
 467 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 468 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 469 #endif
 470 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 471 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 472 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 473 #ifdef CONFIG_PHYS_64BIT
 474 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 475 #else
 476 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 477 #endif
 478 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 479
 480 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 481 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 482 #ifdef CONFIG_PHYS_64BIT
 483 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 484 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 485 #else
 486 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 487 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 488 #endif
 489 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 490 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 491 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 492 #ifdef CONFIG_PHYS_64BIT
 493 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 494 #else
 495 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 496 #endif
 497 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 498
 499 /* Qman/Bman */
 500 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 501 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 502 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 503 #ifdef CONFIG_PHYS_64BIT
 504 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 505 #else
 506 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 507 #endif
 508 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 509 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 510 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 511 #ifdef CONFIG_PHYS_64BIT
 512 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 513 #else
 514 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 515 #endif
 516 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 517
 518 #define CONFIG_SYS_DPAA_FMAN
 519 #define CONFIG_SYS_DPAA_PME
 520 /* Default address of microcode for the Linux Fman driver */
 521 #if defined(CONFIG_SPIFLASH)
 522 /*
 523  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 524  * env, so we got 0x110000.
 525  */
 526 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 527 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x110000
 528 #elif defined(CONFIG_SDCARD)
 529 /*
 530  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 531  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 532  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 533  */
 534 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 535 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (512 * 1130)
 536 #elif defined(CONFIG_NAND)
 537 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 538 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
 539 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 540 /*
 541  * Slave has no ucode locally, it can fetch this from remote. When implementing
 542  * in two corenet boards, slave's ucode could be stored in master's memory
 543  * space, the address can be mapped from slave TLB->slave LAW->
 544  * slave SRIO or PCIE outbound window->master inbound window->
 545  * master LAW->the ucode address in master's memory space.
 546  */
 547 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 548 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xFFE00000
 549 #else
 550 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 551 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xEFF40000
 552 #endif
 553 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 554 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 555
 556 #ifdef CONFIG_SYS_DPAA_FMAN
 557 #define CONFIG_FMAN_ENET
 558 #define CONFIG_PHYLIB_10G
 559 #define CONFIG_PHY_VITESSE
 560 #define CONFIG_PHY_TERANETICS
 561 #endif
 562
 563 #ifdef CONFIG_PCI
 564 #define CONFIG_PCI_INDIRECT_BRIDGE
 565 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 566 #define CONFIG_E1000
 567
 568 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 569 #define CONFIG_DOS_PARTITION
 570 #endif  /* CONFIG_PCI */
 571
 572 /* SATA */
 573 #define CONFIG_FSL_SATA_V2
 574
 575 #ifdef CONFIG_FSL_SATA_V2
 576 #define CONFIG_FSL_SATA
 577 #define CONFIG_LIBATA
 578
 579 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 580 #define CONFIG_SATA1
 581 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 582 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 583 #define CONFIG_SATA2
 584 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 585 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 586
 587 #define CONFIG_LBA48
 588 #define CONFIG_CMD_SATA
 589 #define CONFIG_DOS_PARTITION
 590 #define CONFIG_CMD_EXT2
 591 #endif
 592
 593 #ifdef CONFIG_FMAN_ENET
 594 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 595 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 596 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 597 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 598 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 599
 600 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 601 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 602 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 603 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 604
 605 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 606
 607 #define CONFIG_SYS_TBIPA_VALUE  8
 608 #define CONFIG_MII              /* MII PHY management */
 609 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 610 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 611 #endif
 612
 613 /*
 614  * Environment
 615  */
 616 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 617 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 618
 619 /*
 620  * Command line configuration.
 621  */
 622 #include <config_cmd_default.h>
 623
 624 #define CONFIG_CMD_DHCP
 625 #define CONFIG_CMD_ELF
 626 #define CONFIG_CMD_ERRATA
 627 #define CONFIG_CMD_GREPENV
 628 #define CONFIG_CMD_IRQ
 629 #define CONFIG_CMD_I2C
 630 #define CONFIG_CMD_MII
 631 #define CONFIG_CMD_PING
 632 #define CONFIG_CMD_SETEXPR
 633
 634 #ifdef CONFIG_PCI
 635 #define CONFIG_CMD_PCI
 636 #define CONFIG_CMD_NET
 637 #endif
 638
 639 /*
 640 * USB
 641 */
 642 #define CONFIG_HAS_FSL_DR_USB
 643 #define CONFIG_HAS_FSL_MPH_USB
 644
 645 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 646 #define CONFIG_CMD_USB
 647 #define CONFIG_USB_STORAGE
 648 #define CONFIG_USB_EHCI
 649 #define CONFIG_USB_EHCI_FSL
 650 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 651 #endif
 652
 653 #define CONFIG_CMD_EXT2
 654
 655 #define CONFIG_MMC
 656
 657 #ifdef CONFIG_MMC
 658 #define CONFIG_FSL_ESDHC
 659 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 660 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 661 #define CONFIG_CMD_MMC
 662 #define CONFIG_GENERIC_MMC
 663 #define CONFIG_CMD_EXT2
 664 #define CONFIG_CMD_FAT
 665 #define CONFIG_DOS_PARTITION
 666 #endif
 667
 668 /*
 669  * Miscellaneous configurable options
 670  */
 671 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 672 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 673 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 674 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 675 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 676 #ifdef CONFIG_CMD_KGDB
 677 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 678 #else
 679 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 680 #endif
 681 /* Print Buffer Size */
 682 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 683                                 sizeof(CONFIG_SYS_PROMPT)+16)
 684 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 685 /* Boot Argument Buffer Size */
 686 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 687 #define CONFIG_SYS_HZ           1000            /* decrementer freq 1ms ticks */
 688
 689 /*
 690  * For booting Linux, the board info and command line data
 691  * have to be in the first 64 MB of memory, since this is
 692  * the maximum mapped by the Linux kernel during initialization.
 693  */
 694 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 695 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 696
 697 #ifdef CONFIG_CMD_KGDB
 698 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 699 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 700 #endif
 701
 702 /*
 703  * Environment Configuration
 704  */
 705 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 706 #define CONFIG_BOOTFILE         "uImage"
 707 #define CONFIG_UBOOTPATH        u-boot.bin
 708
 709 /* default location for tftp and bootm */
 710 #define CONFIG_LOADADDR         1000000
 711
 712 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 713
 714 #define CONFIG_BAUDRATE 115200
 715
 716 #define __USB_PHY_TYPE  utmi
 717
 718 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 719         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 720         "bank_intlv=cs0_cs1\0"                                  \
 721         "netdev=eth0\0"                                         \
 722         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 723         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 724         "tftpflash=tftpboot $loadaddr $uboot && "               \
 725         "protect off $ubootaddr +$filesize && "                 \
 726         "erase $ubootaddr +$filesize && "                       \
 727         "cp.b $loadaddr $ubootaddr $filesize && "               \
 728         "protect on $ubootaddr +$filesize && "                  \
 729         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 730         "consoledev=ttyS0\0"                                    \
 731         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 732         "usb_dr_mode=host\0"                                    \
 733         "ramdiskaddr=2000000\0"                                 \
 734         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 735         "fdtaddr=c00000\0"                                      \
 736         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 737         "bdev=sda3\0"                                           \
 738         "c=ffe\0"
 739
 740 #define CONFIG_HDBOOT                                   \
 741         "setenv bootargs root=/dev/$bdev rw "           \
 742         "console=$consoledev,$baudrate $othbootargs;"   \
 743         "tftp $loadaddr $bootfile;"                     \
 744         "tftp $fdtaddr $fdtfile;"                       \
 745         "bootm $loadaddr - $fdtaddr"
 746
 747 #define CONFIG_NFSBOOTCOMMAND                   \
 748         "setenv bootargs root=/dev/nfs rw "     \
 749         "nfsroot=$serverip:$rootpath "          \
 750         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 751         "console=$consoledev,$baudrate $othbootargs;"   \
 752         "tftp $loadaddr $bootfile;"             \
 753         "tftp $fdtaddr $fdtfile;"               \
 754         "bootm $loadaddr - $fdtaddr"
 755
 756 #define CONFIG_RAMBOOTCOMMAND                           \
 757         "setenv bootargs root=/dev/ram rw "             \
 758         "console=$consoledev,$baudrate $othbootargs;"   \
 759         "tftp $ramdiskaddr $ramdiskfile;"               \
 760         "tftp $loadaddr $bootfile;"                     \
 761         "tftp $fdtaddr $fdtfile;"                       \
 762         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 763
 764 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 765
 766 #ifdef CONFIG_SECURE_BOOT
 767 #include <asm/fsl_secure_boot.h>
 768 #endif
 769
 770 #endif  /* __CONFIG_H */