include/configs/PATI.h

   1 /*
   2  * (C) Copyright 2003
   3  * Denis Peter d.peter@mpl.ch
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation,
  21  */
  22
  23 /*
  24  * File:                PATI.h
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  */
  33
  34 #define CONFIG_MPC555           1               /* This is an MPC555 CPU                */
  35 #define CONFIG_PATI             1               /* ...On a PATI board   */
  36 /* Serial Console Configuration */
  37 #define CONFIG_5xx_CONS_SCI1
  38 #undef  CONFIG_5xx_CONS_SCI2
  39
  40 #define CONFIG_BAUDRATE         9600
  41
  42 #define CONFIG_COMMANDS         (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO |             \
  43                                  CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ENV |  CFG_CMD_REGINFO |               \
  44                                  CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_RUN | CFG_CMD_BSP |    \
  45                                  CFG_CMD_IMI | CFG_CMD_EEPROM  | CFG_CMD_IRQ | CFG_CMD_MISC \
  46 )
  47
  48 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  49 #include <cmd_confdefs.h>
  50
  51 #if 0
  52 #define CONFIG_BOOTDELAY        -1              /* autoboot disabled                    */
  53 #else
  54 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds             */
  55 #endif
  56 #define CONFIG_BOOTCOMMAND      ""      /* autoboot command                     */
  57
  58 #define CONFIG_BOOTARGS         ""              /* */
  59
  60 #define CONFIG_WATCHDOG                         /* turn on platform specific watchdog   */
  61
  62 /*#define CONFIG_STATUS_LED     1               */ /* Enable status led */
  63
  64 #define CONFIG_LOADS_ECHO       1               /* Echo on for serial download */
  65
  66 /*
  67  * Miscellaneous configurable options
  68  */
  69 #define CFG_CONSOLE_IS_IN_ENV   /* stdin, stdout and stderr are in evironment */
  70 #define CONFIG_PREBOOT
  71
  72 #define CFG_LONGHELP                            /* undef to save memory         */
  73 #define CFG_PROMPT              "pati=> "               /* Monitor Command Prompt       */
  74 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  75 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size      */
  76 #else
  77 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
  78 #endif
  79 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  80 #define CFG_MAXARGS             16             /* max number of command args    */
  81 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
  82
  83 #define CFG_MEMTEST_START       0x00010000      /* memtest works on             */
  84 #define CFG_MEMTEST_END         0x00A00000      /* 10 MB in SRAM                        */
  85
  86 #define CFG_LOAD_ADDR           0x100000        /* default load address         */
  87
  88 #define CFG_HZ                  1000            /* Decrementer freq: 1 ms ticks */
  89
  90 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 1250000 }
  91
  92
  93 /***********************************************************************
  94  * Last Stage Init
  95  ***********************************************************************/
  96 #define CONFIG_LAST_STAGE_INIT
  97
  98 /*
  99  * Low Level Configuration Settings
 100  */
 101
 102 /*
 103  * Internal Memory Mapped (This is not the IMMR content)
 104  */
 105 #define CFG_IMMR                0x01C00000                              /* Physical start adress of internal memory map */
 106
 107 /*
 108  * Definitions for initial stack pointer and data area
 109  */
 110 #define CFG_INIT_RAM_ADDR       (CFG_IMMR + 0x003f9800)                 /* Physical start adress of internal MPC555 writable RAM */
 111 #define CFG_INIT_RAM_END        (CFG_IMMR + 0x003fffff)                 /* Physical end adress of internal MPC555 used RAM area */
 112 #define CFG_GBL_DATA_SIZE       128                                     /* Size in bytes reserved for initial global data */
 113 #define CFG_GBL_DATA_OFFSET     ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
 114 #define CFG_INIT_SP_ADDR        (CFG_IMMR + 0x03fa000)                  /* Physical start adress of inital stack */
 115 /*
 116  * Start addresses for the final memory configuration
 117  * Please note that CFG_SDRAM_BASE _must_ start at 0
 118  */
 119 #define CFG_SDRAM_BASE          0x00000000      /* Monitor won't change memory map                      */
 120 #define CFG_FLASH_BASE          0xffC00000      /* External flash */
 121 #define PCI_BASE                0x03000000      /* PCI Base (CS2) */
 122 #define PCI_CONFIG_BASE         0x04000000      /* PCI & PLD  (CS3) */
 123 #define PLD_CONFIG_BASE         0x04001000      /* PLD  (CS3) */
 124
 125 #define CFG_MONITOR_BASE        0xFFF00000
 126 /* CFG_FLASH_BASE       */ /* TEXT_BASE is defined in the board config.mk file.         */
 127                                                 /* This adress is given to the linker with -Ttext to    */
 128                                                 /* locate the text section at this adress.              */
 129 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 192 kB for Monitor                           */
 130 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()                          */
 131
 132 #define CFG_RESET_ADDRESS       (PLD_CONFIG_BASE + 0x10)         /* Adress which causes reset */
 133
 134 /*
 135  * For booting Linux, the board info and command line data
 136  * have to be in the first 8 MB of memory, since this is
 137  * the maximum mapped by the Linux kernel during initialization.
 138  */
 139 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux         */
 140
 141
 142 /*-----------------------------------------------------------------------
 143  * FLASH organization
 144  *-----------------------------------------------------------------------
 145  *
 146  */
 147
 148 #define CFG_MAX_FLASH_BANKS             1               /* Max number of memory banks           */
 149 #define CFG_MAX_FLASH_SECT              128             /* Max number of sectors on one chip    */
 150 #define CFG_FLASH_ERASE_TOUT    180000          /* Timeout for Flash Erase (in ms)      */
 151 #define CFG_FLASH_WRITE_TOUT    600             /* Timeout for Flash Write (in ms)      */
 152
 153
 154 #define CFG_ENV_IS_IN_EEPROM
 155 #ifdef  CFG_ENV_IS_IN_EEPROM
 156 #define CFG_ENV_OFFSET          0
 157 #define CFG_ENV_SIZE            2048
 158 #endif
 159
 160 #undef  CFG_ENV_IS_IN_FLASH
 161 #ifdef  CFG_ENV_IS_IN_FLASH
 162 #define CFG_ENV_SIZE            0x00002000              /* Set whole sector as env              */
 163 #define CFG_ENV_OFFSET          ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE)           /* Environment starts at this adress    */
 164 #endif
 165
 166
 167 #define CONFIG_SPI              1
 168 #define CFG_SPI_CS_USED 0x09 /* CS0 and CS3 are used */
 169 #define CFG_SPI_CS_BASE 0x08 /* CS3 is active low */
 170 #define CFG_SPI_CS_ACT  0x00 /* CS3 is active low */
 171 /*-----------------------------------------------------------------------
 172  * SYPCR - System Protection Control
 173  * SYPCR can only be written once after reset!
 174  *-----------------------------------------------------------------------
 175  * SW Watchdog freeze
 176  */
 177 #undef CONFIG_WATCHDOG
 178 #if defined(CONFIG_WATCHDOG)
 179 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 180                          SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
 181 #else
 182 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 183                          SYPCR_SWP)
 184 #endif  /* CONFIG_WATCHDOG */
 185
 186 /*-----------------------------------------------------------------------
 187  * TBSCR - Time Base Status and Control
 188  *-----------------------------------------------------------------------
 189  * Clear Reference Interrupt Status, Timebase freezing enabled
 190  */
 191 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 192
 193 /*-----------------------------------------------------------------------
 194  * PISCR - Periodic Interrupt Status and Control
 195  *-----------------------------------------------------------------------
 196  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 197  */
 198 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 199
 200 /*-----------------------------------------------------------------------
 201  * SCCR - System Clock and reset Control Register
 202  *-----------------------------------------------------------------------
 203  * Set clock output, timebase and RTC source and divider,
 204  * power management and some other internal clocks
 205  */
 206 #define SCCR_MASK       SCCR_EBDF00
 207 #define CFG_SCCR        (SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 208                          SCCR_COM01   | SCCR_DFNL000 | SCCR_DFNH000)
 209
 210 /*-----------------------------------------------------------------------
 211  * SIUMCR - SIU Module Configuration
 212  *-----------------------------------------------------------------------
 213  * Data show cycle
 214  */
 215 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle         */
 216
 217 /*-----------------------------------------------------------------------
 218  * PLPRCR - PLL, Low-Power, and Reset Control Register
 219  *-----------------------------------------------------------------------
 220  * Set all bits to 40 Mhz
 221  *
 222  */
 223 #define CFG_OSC_CLK     ((uint)4000000)         /* Oscillator clock is 4MHz     */
 224
 225
 226 #define CFG_PLPRCR      (PLPRCR_MF_9 | PLPRCR_DIVF_0)
 227
 228 /*-----------------------------------------------------------------------
 229  * UMCR - UIMB Module Configuration Register
 230  *-----------------------------------------------------------------------
 231  *
 232  */
 233 #define CFG_UMCR        (UMCR_FSPEED)           /* IMB clock same as U-bus      */
 234
 235 /*-----------------------------------------------------------------------
 236  * ICTRL - I-Bus Support Control Register
 237  */
 238 #define CFG_ICTRL       (ICTRL_ISCT_SER_7)      /* Take out of serialized mode  */
 239
 240 /*-----------------------------------------------------------------------
 241  * USIU - Memory Controller Register
 242  *-----------------------------------------------------------------------
 243  */
 244 #define CFG_BR0_PRELIM          (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
 245 #define CFG_OR0_PRELIM          (0xffc00000) /* SCY is not used if external TA is set */
 246 /* SDRAM */
 247 #define CFG_BR1_PRELIM          (CFG_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
 248 #define CFG_OR1_PRELIM          (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
 249 /* PCI */
 250 #define CFG_BR2_PRELIM          (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
 251 #define CFG_OR2_PRELIM          (OR_ADDR_MK_FF)
 252 /* config registers: */
 253 #define CFG_BR3_PRELIM          (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
 254 #define CFG_OR3_PRELIM          (0xffff0000)
 255
 256 #define FLASH_BASE0_PRELIM      CFG_FLASH_BASE  /* We don't realign the flash   */
 257
 258 /*-----------------------------------------------------------------------
 259  * DER - Timer Decrementer
 260  *-----------------------------------------------------------------------
 261  * Initialise to zero
 262  */
 263 #define CFG_DER                 0x00000000
 264
 265
 266 /*
 267  * Internal Definitions
 268  *
 269  * Boot Flags
 270  */
 271 #define BOOTFLAG_COLD   0x01                    /* Normal Power-On: Boot from FLASH     */
 272 #define BOOTFLAG_WARM   0x02                    /* Software reboot                      */
 273
 274
 275 #define VERSION_TAG "released"
 276 #define CONFIG_ISO_STRING "MEV-10084-001"
 277
 278 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 279
 280 #endif  /* __CONFIG_H */