include/configs/PM520.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC5200
  33 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  34 #define CONFIG_PM520            1       /* ... on PM520 board */
  35
  36 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33MHz */
  37
  38 #define CONFIG_MISC_INIT_R
  39
  40 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  41 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  42
  43 /*
  44  * Serial console configuration
  45  */
  46 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  47 #define CONFIG_BAUDRATE         9600    /* ... at 9600 bps */
  48 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  49
  50
  51 #ifdef CONFIG_MPC5200   /* MPC5100 PCI is not supported yet. */
  52 /*
  53  * PCI Mapping:
  54  * 0x40000000 - 0x4fffffff - PCI Memory
  55  * 0x50000000 - 0x50ffffff - PCI IO Space
  56  */
  57 #define CONFIG_PCI              1
  58 #define CONFIG_PCI_PNP          1
  59 #define CONFIG_PCI_SCAN_SHOW    1
  60
  61 #define CONFIG_PCI_MEM_BUS      0x40000000
  62 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  63 #define CONFIG_PCI_MEM_SIZE     0x10000000
  64
  65 #define CONFIG_PCI_IO_BUS       0x50000000
  66 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  67 #define CONFIG_PCI_IO_SIZE      0x01000000
  68
  69 #define CONFIG_NET_MULTI        1
  70 #define CONFIG_MII              1
  71 #define CONFIG_EEPRO100         1
  72 #define CFG_RX_ETH_BUFFER       8  /* use 8 rx buffer on eepro100  */
  73 #undef  CONFIG_NS8382X
  74
  75 #endif
  76
  77 /* Partitions */
  78 #define CONFIG_DOS_PARTITION
  79
  80 /* USB */
  81 #if 1
  82 #define CONFIG_USB_OHCI
  83 #define CONFIG_USB_STORAGE
  84 #endif
  85
  86 #if !defined(CONFIG_BOOT_ROM)
  87 /* DoC requires legacy NAND for now */
  88 #define CFG_NAND_LEGACY
  89 #endif
  90
  91
  92 /*
  93  * BOOTP options
  94  */
  95 #define CONFIG_BOOTP_BOOTFILESIZE
  96 #define CONFIG_BOOTP_BOOTPATH
  97 #define CONFIG_BOOTP_GATEWAY
  98 #define CONFIG_BOOTP_HOSTNAME
  99
 100
 101 /*
 102  * Command line configuration.
 103  */
 104 #include <config_cmd_default.h>
 105
 106 #define CONFIG_CMD_BEDBUG
 107 #define CONFIG_CMD_DATE
 108 #define CONFIG_CMD_DHCP
 109 #define CONFIG_CMD_EEPROM
 110 #define CONFIG_CMD_FAT
 111 #define CONFIG_CMD_I2C
 112 #define CONFIG_CMD_IDE
 113 #define CONFIG_CMD_NFS
 114 #define CONFIG_CMD_SNTP
 115 #define CONFIG_CMD_USB
 116
 117 #if !defined(CONFIG_BOOT_ROM)
 118 #define CONFIG_CMD_DOC
 119 #endif
 120
 121 #if defined(CONFIG_MPC5200)
 122 #define CONFIG_CMD_PCI
 123 #endif
 124
 125
 126 /*
 127  * Autobooting
 128  */
 129 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 130
 131 #define CONFIG_PREBOOT  "echo;" \
 132         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 133         "echo"
 134
 135 #undef  CONFIG_BOOTARGS
 136
 137 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 138         "netdev=eth0\0"                                                 \
 139         "hostname=pm520\0"                                                      \
 140         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 141                 "nfsroot=${serverip}:${rootpath}\0"                     \
 142         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 143         "addip=setenv bootargs ${bootargs} "                            \
 144                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 145                 ":${hostname}:${netdev}:off panic=1\0"                  \
 146         "flash_nfs=run nfsargs addip;"                                  \
 147                 "bootm ${kernel_addr}\0"                                \
 148         "flash_self=run ramargs addip;"                                 \
 149                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 150         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 151         "rootpath=/opt/eldk30/ppc_82xx\0"                                       \
 152         "bootfile=/tftpboot/PM520/uImage\0"                             \
 153         ""
 154
 155 #define CONFIG_BOOTCOMMAND      "run flash_self"
 156
 157 #if defined(CONFIG_MPC5200)
 158 /*
 159  * IPB Bus clocking configuration.
 160  */
 161 #undef CFG_IPBCLK_EQUALS_XLBCLK                 /* define for 133MHz speed */
 162 #endif
 163 /*
 164  * I2C configuration
 165  */
 166 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 167 #define CFG_I2C_MODULE          2       /* Select I2C module #1 or #2 */
 168
 169 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 170 #define CFG_I2C_SLAVE           0x7F
 171
 172 /*
 173  * EEPROM configuration
 174  */
 175 #define CFG_I2C_EEPROM_ADDR             0x58
 176 #define CFG_I2C_EEPROM_ADDR_LEN         1
 177 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 178 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10
 179
 180 /*
 181  * RTC configuration
 182  */
 183 #define CONFIG_RTC_PCF8563
 184 #define CFG_I2C_RTC_ADDR                0x51
 185
 186 /*
 187  * Disk-On-Chip configuration
 188  */
 189
 190 #define CFG_DOC_SHORT_TIMEOUT
 191 #define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices    */
 192
 193 #define CFG_DOC_SUPPORT_2000
 194 #define CFG_DOC_SUPPORT_MILLENNIUM
 195 #define CFG_DOC_BASE            0xE0000000
 196 #define CFG_DOC_SIZE            0x00100000
 197
 198 #if defined(CONFIG_BOOT_ROM)
 199 /*
 200  * Flash configuration (8,16 or 32 MB)
 201  * TEXT base always at 0xFFF00000
 202  * ENV_ADDR always at  0xFFF40000
 203  * FLASH_BASE at 0xFA000000 for 64 MB
 204  *               0xFC000000 for 32 MB
 205  *               0xFD000000 for 16 MB
 206  *               0xFD800000 for  8 MB
 207  */
 208 #define CFG_FLASH_BASE          0xFA000000
 209 #define CFG_FLASH_SIZE          0x04000000
 210 #define CFG_BOOTROM_BASE        0xFFF00000
 211 #define CFG_BOOTROM_SIZE        0x00080000
 212 #define CFG_ENV_ADDR            (0xFDF00000 + 0x40000)
 213 #else
 214 /*
 215  * Flash configuration (8,16 or 32 MB)
 216  * TEXT base always at 0xFFF00000
 217  * ENV_ADDR always at  0xFFF40000
 218  * FLASH_BASE at 0xFC000000 for 64 MB
 219  *               0xFE000000 for 32 MB
 220  *               0xFF000000 for 16 MB
 221  *               0xFF800000 for  8 MB
 222  */
 223 #define CFG_FLASH_BASE          0xFC000000
 224 #define CFG_FLASH_SIZE          0x04000000
 225 #define CFG_ENV_ADDR            (0xFFF00000 + 0x40000)
 226 #endif
 227 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 228
 229 #define CFG_MAX_FLASH_SECT      256     /* max num of sects on one chip */
 230
 231 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 232 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 233 #define CFG_FLASH_LOCK_TOUT     5       /* Timeout for Flash Set Lock Bit (in ms) */
 234 #define CFG_FLASH_UNLOCK_TOUT   10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 235 #define CFG_FLASH_PROTECTION            /* "Real" (hardware) sectors protection */
 236
 237 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 238
 239 #undef CONFIG_FLASH_16BIT       /* Flash is 32-bit */
 240
 241
 242 /*
 243  * Environment settings
 244  */
 245 #define CFG_ENV_IS_IN_FLASH     1
 246 #define CFG_ENV_SIZE            0x10000
 247 #define CFG_ENV_SECT_SIZE       0x40000
 248 #define CONFIG_ENV_OVERWRITE    1
 249
 250 /*
 251  * Memory map
 252  */
 253 #define CFG_MBAR                0xf0000000
 254 #define CFG_SDRAM_BASE          0x00000000
 255 #define CFG_DEFAULT_MBAR        0x80000000
 256
 257 /* Use SRAM until RAM will be available */
 258 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 259 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 260
 261
 262 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 263 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 264 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 265
 266 #define CFG_MONITOR_BASE    TEXT_BASE
 267 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 268 #   define CFG_RAMBOOT          1
 269 #endif
 270
 271 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 272 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 273 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 274
 275 /*
 276  * Ethernet configuration
 277  */
 278 #define CONFIG_MPC5xxx_FEC      1
 279 /*
 280  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 281  */
 282 /* #define CONFIG_FEC_10MBIT 1 */
 283 #define CONFIG_PHY_ADDR         0x00
 284
 285 /*
 286  * GPIO configuration
 287  */
 288 #define CFG_GPS_PORT_CONFIG     0x10000004
 289
 290 /*
 291  * Miscellaneous configurable options
 292  */
 293 #define CFG_LONGHELP                    /* undef to save memory     */
 294 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 295 #if defined(CONFIG_CMD_KGDB)
 296 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 297 #else
 298 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 299 #endif
 300 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 301 #define CFG_MAXARGS             16              /* max number of command args   */
 302 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 303
 304 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 305 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 306
 307 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 308
 309 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 310
 311 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
 312 #if defined(CONFIG_CMD_KGDB)
 313 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 314 #endif
 315
 316 /*
 317  * Various low-level settings
 318  */
 319 #if defined(CONFIG_MPC5200)
 320 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 321 #define CFG_HID0_FINAL          HID0_ICE
 322 #else
 323 #define CFG_HID0_INIT           0
 324 #define CFG_HID0_FINAL          0
 325 #endif
 326
 327 #if defined(CONFIG_BOOT_ROM)
 328 #define CFG_BOOTCS_START        CFG_BOOTROM_BASE
 329 #define CFG_BOOTCS_SIZE         CFG_BOOTROM_SIZE
 330 #define CFG_BOOTCS_CFG          0x00047800
 331 #define CFG_CS0_START           CFG_BOOTROM_BASE
 332 #define CFG_CS0_SIZE            CFG_BOOTROM_SIZE
 333 #define CFG_CS1_START           CFG_FLASH_BASE
 334 #define CFG_CS1_SIZE            CFG_FLASH_SIZE
 335 #define CFG_CS1_CFG             0x0004FF00
 336 #else
 337 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 338 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 339 #define CFG_BOOTCS_CFG          0x0004FF00
 340 #define CFG_CS0_START           CFG_FLASH_BASE
 341 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 342 #define CFG_CS1_START           CFG_DOC_BASE
 343 #define CFG_CS1_SIZE            CFG_DOC_SIZE
 344 #define CFG_CS1_CFG             0x00047800
 345 #endif
 346
 347 #define CFG_CS_BURST            0x00000000
 348 #define CFG_CS_DEADCYCLE        0x33333333
 349
 350 #define CFG_RESET_ADDRESS       0xff000000
 351
 352 /*-----------------------------------------------------------------------
 353  * USB stuff
 354  *-----------------------------------------------------------------------
 355  */
 356 #define CONFIG_USB_CLOCK        0x0001BBBB
 357 #define CONFIG_USB_CONFIG       0x00005000
 358
 359 /*-----------------------------------------------------------------------
 360  * IDE/ATA stuff Supports IDE harddisk
 361  *-----------------------------------------------------------------------
 362  */
 363
 364 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 365
 366 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 367 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 368
 369 #undef  CONFIG_IDE_RESET                /* reset for ide supported      */
 370 #define CONFIG_IDE_PREINIT
 371
 372 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 373 #define CFG_IDE_MAXDEVICE       2       /* max. 2 drive per IDE bus     */
 374
 375 #define CFG_ATA_IDE0_OFFSET     0x0000
 376
 377 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 378
 379 /* Offset for data I/O                  */
 380 #define CFG_ATA_DATA_OFFSET     (0x0060)
 381
 382 /* Offset for normal register accesses  */
 383 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)
 384
 385 /* Offset for alternate registers       */
 386 #define CFG_ATA_ALT_OFFSET      (0x005C)
 387
 388 /* Interval between registers                                                */
 389 #define CFG_ATA_STRIDE          4
 390
 391 #endif /* __CONFIG_H */