include/configs/RPXClassic.h

   1 /*
   2  * (C) Copyright 2000, 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
  13  * U-Boot port on RPXlite board
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 #define RPXClassic_50MHz
  20
  21 /*
  22  * High Level Configuration Options
  23  * (easy to change)
  24  */
  25
  26 #define CONFIG_MPC860           1
  27 #define CONFIG_RPXCLASSIC               1
  28
  29 #define CONFIG_SYS_TEXT_BASE    0xff000000
  30
  31 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  32 #undef  CONFIG_8xx_CONS_SMC2
  33 #undef  CONFIG_8xx_CONS_NONE
  34 #define CONFIG_BAUDRATE         9600    /* console baudrate = 9600bps   */
  35
  36 /* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1   */
  37 #define CONFIG_FEC_ENET
  38 #ifdef CONFIG_FEC_ENET
  39 #define CONFIG_SYS_DISCOVER_PHY        1
  40 #define CONFIG_MII              1
  41 #endif /* CONFIG_FEC_ENET */
  42 #define CONFIG_MISC_INIT_R
  43
  44 /* Video console (graphic: Epson SED13806 on ECCX board, no keyboard         */
  45 #if 1
  46 #define CONFIG_VIDEO_SED13806
  47 #define CONFIG_NEC_NL6448BC20
  48 #define CONFIG_VIDEO_SED13806_16BPP
  49
  50 #define CONFIG_CFB_CONSOLE
  51 #define CONFIG_VIDEO_LOGO
  52 #define CONFIG_VIDEO_BMP_LOGO
  53 #define CONFIG_CONSOLE_EXTRA_INFO
  54 #define CONFIG_VGA_AS_SINGLE_DEVICE
  55 #define CONFIG_VIDEO_SW_CURSOR
  56 #endif
  57
  58 #if 0
  59 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  60 #else
  61 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  62 #endif
  63
  64 #define CONFIG_ZERO_BOOTDELAY_CHECK 1
  65
  66 #undef  CONFIG_BOOTARGS
  67 #define CONFIG_BOOTCOMMAND                                                      \
  68         "tftpboot; "                                                            \
  69         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  70         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  71         "bootm"
  72
  73 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  74 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  75
  76 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  77
  78 /*
  79  * BOOTP options
  80  */
  81 #define CONFIG_BOOTP_SUBNETMASK
  82 #define CONFIG_BOOTP_GATEWAY
  83 #define CONFIG_BOOTP_HOSTNAME
  84 #define CONFIG_BOOTP_BOOTPATH
  85 #define CONFIG_BOOTP_BOOTFILESIZE
  86
  87
  88 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  89
  90
  91 /*
  92  * Command line configuration.
  93  */
  94 #include <config_cmd_default.h>
  95
  96 #define CONFIG_CMD_ELF
  97
  98
  99 /*
 100  * Miscellaneous configurable options
 101  */
 102 #define CONFIG_SYS_RESET_ADDRESS        0x80000000
 103 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 104 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 105 #if defined(CONFIG_CMD_KGDB)
 106 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 107 #else
 108 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 109 #endif
 110 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 111 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 112 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 113
 114 #define CONFIG_SYS_MEMTEST_START        0x0040000       /* memtest works on     */
 115 #define CONFIG_SYS_MEMTEST_END          0x00C0000       /* 4 ... 12 MB in DRAM  */
 116
 117 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 118
 119 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 120
 121 /*
 122  * Low Level Configuration Settings
 123  * (address mappings, register initial values, etc.)
 124  * You should know what you are doing if you make changes here.
 125  */
 126 /*-----------------------------------------------------------------------
 127  * Internal Memory Mapped Register
 128  */
 129 #define CONFIG_SYS_IMMR         0xFA200000
 130
 131 /*-----------------------------------------------------------------------------
 132  * I2C Configuration
 133  *-----------------------------------------------------------------------------
 134  */
 135 #define CONFIG_I2C              1
 136 #define CONFIG_SYS_I2C_SPEED           50000
 137 #define CONFIG_SYS_I2C_SLAVE           0x34
 138
 139
 140 /* enable I2C and select the hardware/software driver */
 141 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 142 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 143 /*
 144  * Software (bit-bang) I2C driver configuration
 145  */
 146 #define I2C_PORT        1               /* Port A=0, B=1, C=2, D=3 */
 147 #define I2C_ACTIVE      (iop->pdir |=  0x00000010)
 148 #define I2C_TRISTATE    (iop->pdir &= ~0x00000010)
 149 #define I2C_READ        ((iop->pdat & 0x00000010) != 0)
 150 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00000010; \
 151                         else    iop->pdat &= ~0x00000010
 152 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00000020; \
 153                         else    iop->pdat &= ~0x00000020
 154 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 155
 156
 157 # define CONFIG_SYS_I2C_SPEED           50000
 158 # define CONFIG_SYS_I2C_SLAVE           0x34
 159 # define CONFIG_SYS_I2C_EEPROM_ADDR     0x50    /* EEPROM X24C16                */
 160 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1       /* bytes of address             */
 161 /* mask of address bits that overflow into the "EEPROM chip address"    */
 162 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 163
 164 /*-----------------------------------------------------------------------
 165  * Definitions for initial stack pointer and data area (in DPRAM)
 166  */
 167 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 168 #define CONFIG_SYS_INIT_RAM_SIZE        0x3000  /* Size of used area in DPRAM   */
 169 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 170 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 171
 172 /*-----------------------------------------------------------------------
 173  * Start addresses for the final memory configuration
 174  * (Set up by the startup code)
 175  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 176  */
 177 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 178 #define CONFIG_SYS_FLASH_BASE   0xFF000000
 179
 180 #if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE)
 181 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 182 #else
 183 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 184 #endif
 185 #define CONFIG_SYS_MONITOR_BASE 0xFF000000
 186 /*%%% #define CONFIG_SYS_MONITOR_BASE   CONFIG_SYS_FLASH_BASE */
 187 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 188
 189 /*
 190  * For booting Linux, the board info and command line data
 191  * have to be in the first 8 MB of memory, since this is
 192  * the maximum mapped by the Linux kernel during initialization.
 193  */
 194 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 195
 196 /*-----------------------------------------------------------------------
 197  * FLASH organization
 198  */
 199 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 200 #define CONFIG_SYS_MAX_FLASH_SECT       71      /* max number of sectors on one chip    */
 201
 202 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 203 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 204
 205 #if 0
 206 #define CONFIG_ENV_IS_IN_FLASH  1
 207 #define CONFIG_ENV_OFFSET               0x20000 /*   Offset   of Environment Sector  */
 208 #define CONFIG_ENV_SECT_SIZE       0x8000
 209 #define CONFIG_ENV_SIZE         0x8000  /* Total Size of Environment Sector  */
 210 #else
 211 #define CONFIG_ENV_IS_IN_NVRAM     1
 212 #define CONFIG_ENV_ADDR            0xfa000100
 213 #define CONFIG_ENV_SIZE            0x1000
 214 #endif
 215
 216 /*-----------------------------------------------------------------------
 217  * Cache Configuration
 218  */
 219 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 220 #if defined(CONFIG_CMD_KGDB)
 221 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 222 #endif
 223
 224 /*-----------------------------------------------------------------------
 225  * SYPCR - System Protection Control                            11-9
 226  * SYPCR can only be written once after reset!
 227  *-----------------------------------------------------------------------
 228  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 229  */
 230 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 231                          SYPCR_SWP)
 232
 233 /*-----------------------------------------------------------------------
 234  * SIUMCR - SIU Module Configuration                            11-6
 235  *-----------------------------------------------------------------------
 236  * PCMCIA config., multi-function pin tri-state
 237  */
 238 #define CONFIG_SYS_SIUMCR       (SIUMCR_MLRC10)
 239
 240 /*-----------------------------------------------------------------------
 241  * TBSCR - Time Base Status and Control                         11-26
 242  *-----------------------------------------------------------------------
 243  * Clear Reference Interrupt Status, Timebase freezing enabled
 244  */
 245 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 246
 247 /*-----------------------------------------------------------------------
 248  * RTCSC - Real-Time Clock Status and Control Register          11-27
 249  *-----------------------------------------------------------------------
 250  */
 251 /*%%%#define CONFIG_SYS_RTCSC   (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
 252 #define CONFIG_SYS_RTCSC        (RTCSC_SEC |  RTCSC_ALR | RTCSC_RTE)
 253
 254 /*-----------------------------------------------------------------------
 255  * PISCR - Periodic Interrupt Status and Control                11-31
 256  *-----------------------------------------------------------------------
 257  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 258  */
 259 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
 260
 261 /*-----------------------------------------------------------------------
 262  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 263  *-----------------------------------------------------------------------
 264  * Reset PLL lock status sticky bit, timer expired status bit and timer
 265  * interrupt status bit
 266  *
 267  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 268  */
 269 /* up to 50 MHz we use a 1:1 clock */
 270 #define CONFIG_SYS_PLPRCR       ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST)
 271
 272 /*-----------------------------------------------------------------------
 273  * SCCR - System Clock and reset Control Register               15-27
 274  *-----------------------------------------------------------------------
 275  * Set clock output, timebase and RTC source and divider,
 276  * power management and some other internal clocks
 277  */
 278 #define SCCR_MASK       SCCR_EBDF00
 279 /* up to 50 MHz we use a 1:1 clock */
 280 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
 281
 282 /*-----------------------------------------------------------------------
 283  * PCMCIA stuff
 284  *-----------------------------------------------------------------------
 285  *
 286  */
 287 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 288 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 289 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 290 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 291 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 292 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 293 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 294 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 295
 296 /*-----------------------------------------------------------------------
 297  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 298  *-----------------------------------------------------------------------
 299  */
 300
 301 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 302 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 303
 304 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 305 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 306 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 307
 308 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 309 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 310
 311 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 312
 313 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 314
 315 /* Offset for data I/O                  */
 316 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 317
 318 /* Offset for normal register accesses  */
 319 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 320
 321 /* Offset for alternate registers       */
 322 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 323
 324 /*-----------------------------------------------------------------------
 325  *
 326  *-----------------------------------------------------------------------
 327  *
 328  */
 329 /* #define      CONFIG_SYS_DER  0x2002000F */
 330 #define CONFIG_SYS_DER  0
 331
 332 /*
 333  * Init Memory Controller:
 334  *
 335  * BR0 and OR0 (FLASH)
 336  */
 337
 338 #define FLASH_BASE_PRELIM       0xFE000000      /* FLASH base */
 339 #define CONFIG_SYS_PRELIM_OR_AM 0xFE000000      /* OR addr mask */
 340
 341 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
 342 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
 343
 344 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 345 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 346
 347 /*
 348  * BR1 and OR1 (SDRAM)
 349  *
 350  */
 351 #define SDRAM_BASE_PRELIM       0x00000000      /* SDRAM base   */
 352 #define SDRAM_MAX_SIZE          0x01000000      /* max 16 MB */
 353
 354 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 355 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000E00
 356
 357 #define CONFIG_SYS_OR1_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 358 #define CONFIG_SYS_BR1_PRELIM   ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 359
 360 /* RPXLITE mem setting */
 361 #define CONFIG_SYS_BR3_PRELIM   0xFA400001              /* BCSR */
 362 #define CONFIG_SYS_OR3_PRELIM   0xff7f8970
 363 #define CONFIG_SYS_BR4_PRELIM   0xFA000401              /* NVRAM&SRAM */
 364 #define CONFIG_SYS_OR4_PRELIM   0xFFF80970
 365
 366 /* ECCX CS settings                                                          */
 367 #define SED13806_OR             0xFFC00108     /* - 4 Mo
 368                                                    - Burst inhibit
 369                                                    - external TA             */
 370 #define SED13806_REG_ADDR       0xa0000000
 371 #define SED13806_ACCES          0x801           /* 16 bit access             */
 372
 373
 374 /* Global definitions for the ECCX board                                     */
 375 #define ECCX_CSR_ADDR           (0xfac00000)
 376 #define ECCX_CSR8_OFFSET        (0x8)
 377 #define ECCX_CSR11_OFFSET       (0xB)
 378 #define ECCX_CSR12_OFFSET       (0xC)
 379
 380 #define ECCX_CSR8  (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET)
 381 #define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET)
 382 #define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET)
 383
 384
 385 #define REG_GPIO_CTRL 0x008
 386
 387 /* Definitions for CSR8                                                      */
 388 #define ECCX_ENEPSON            0x80    /* Bit 0:
 389                                            0= disable and reset SED1386
 390                                            1= enable SED1386                 */
 391 /* Bit 1:   0= SED1386 in Big Endian mode                                    */
 392 /*          1= SED1386 in little endian mode                                 */
 393 #define ECCX_LE                 0x40
 394 #define ECCX_BE                 0x00
 395
 396 /* Bit 2,3: Selection                                                        */
 397 /*      00 = Disabled                                                        */
 398 /*      01 = CS2 is used for the SED1386                                     */
 399 /*      10 = CS5 is used for the SED1386                                     */
 400 /*      11 = reserved                                                        */
 401 #define ECCX_CS2                0x10
 402 #define ECCX_CS5                0x20
 403
 404 /* Definitions for CSR12                                                     */
 405 #define ECCX_ID                 0x02
 406 #define ECCX_860                0x01
 407
 408 /*
 409  * Memory Periodic Timer Prescaler
 410  */
 411
 412 /* periodic timer for refresh */
 413 #define CONFIG_SYS_MAMR_PTA     58
 414
 415 /*
 416  * Refresh clock Prescalar
 417  */
 418 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV8
 419
 420 /*
 421  * MAMR settings for SDRAM
 422  */
 423
 424 /* 10 column SDRAM */
 425 #define CONFIG_SYS_MAMR_10COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 426                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |   \
 427                          MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
 428
 429 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
 430 /* Configuration variable added by yooth. */
 431 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
 432
 433 /*
 434  * BCSRx
 435  *
 436  * Board Status and Control Registers
 437  *
 438  */
 439
 440 #define BCSR0 0xFA400000
 441 #define BCSR1 0xFA400001
 442 #define BCSR2 0xFA400002
 443 #define BCSR3 0xFA400003
 444
 445 #define BCSR0_ENMONXCVR 0x01    /* Monitor XVCR Control */
 446 #define BCSR0_ENNVRAM   0x02    /* CS4# Control */
 447 #define BCSR0_LED5              0x04    /* LED5 control 0='on' 1='off' */
 448 #define BCSR0_LED4              0x08    /* LED4 control 0='on' 1='off' */
 449 #define BCSR0_FULLDPLX  0x10    /* Ethernet XCVR Control */
 450 #define BCSR0_COLTEST   0x20
 451 #define BCSR0_ETHLPBK   0x40
 452 #define BCSR0_ETHEN     0x80
 453
 454 #define BCSR1_PCVCTL7   0x01    /* PC Slot B Control */
 455 #define BCSR1_PCVCTL6   0x02
 456 #define BCSR1_PCVCTL5   0x04
 457 #define BCSR1_PCVCTL4   0x08
 458 #define BCSR1_IPB5SEL   0x10
 459
 460 #define BCSR2_MIIRST    0x80
 461 #define BCSR2_MIIPWRDWN 0x40
 462 #define BCSR2_MIICTL    0x08
 463
 464 #define BCSR3_BWRTC             0x01    /* Real Time Clock Battery */
 465 #define BCSR3_BWNVR             0x02    /* NVRAM Battery */
 466 #define BCSR3_RDY_BSY   0x04    /* Flash Operation */
 467 #define BCSR3_RPXL              0x08    /* Reserved (reads back '1') */
 468 #define BCSR3_D27               0x10    /* Dip Switch settings */
 469 #define BCSR3_D26               0x20
 470 #define BCSR3_D25               0x40
 471 #define BCSR3_D24               0x80
 472
 473
 474 /*
 475  * Environment setting
 476  */
 477
 478 /* #define CONFIG_ETHADDR       00:10:EC:00:2C:A2 */
 479 /* #define CONFIG_IPADDR        10.10.106.1 */
 480 /* #define CONFIG_SERVERIP      10.10.104.11 */
 481
 482 #endif  /* __CONFIG_H */