]> git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/SM850.h
rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / include / configs / SM850.h
1 /*
2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * board/config.h - configuration options, board specific
26 */
27
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
30
31 #undef TQM8xxL_80MHz /* 1 / * define for 80 MHz CPU only */
32
33 /*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
39 #define CONFIG_SM850 1 /*...on a MPC850 Service Module */
40
41 #undef CONFIG_8xx_CONS_SMC1 /* SMC1 not usable because Ethernet on SCC3 */
42 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
43 #undef CONFIG_8xx_CONS_NONE
44 #define CONFIG_BAUDRATE 115200
45 #if 0
46 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
47 #else
48 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49 #endif
50
51 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
52
53 #define CONFIG_BOARD_TYPES 1 /* support board types */
54
55 #undef CONFIG_BOOTARGS
56 #define CONFIG_BOOTCOMMAND \
57 "bootp; " \
58 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
59 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
60 "bootm"
61
62 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
63 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
64
65 #undef CONFIG_WATCHDOG /* watchdog disabled */
66
67 #undef CONFIG_STATUS_LED /* Status LED not enabled */
68
69 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
70
71 /*
72 * BOOTP options
73 */
74 #define CONFIG_BOOTP_SUBNETMASK
75 #define CONFIG_BOOTP_GATEWAY
76 #define CONFIG_BOOTP_HOSTNAME
77 #define CONFIG_BOOTP_BOOTPATH
78 #define CONFIG_BOOTP_BOOTFILESIZE
79
80
81 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
82
83
84 /*
85 * Command line configuration.
86 */
87 #include <config_cmd_default.h>
88
89 #define CONFIG_CMD_DHCP
90 #define CONFIG_CMD_DATE
91
92
93 /*
94 * Miscellaneous configurable options
95 */
96 #define CONFIG_SYS_LONGHELP /* undef to save memory */
97 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
98 #if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG)
99 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
100 #else
101 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
102 #endif
103 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
104 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
105 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
106
107 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
108 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
109
110 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
111
112 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
113
114 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
115
116 /*
117 * Low Level Configuration Settings
118 * (address mappings, register initial values, etc.)
119 * You should know what you are doing if you make changes here.
120 */
121 /*-----------------------------------------------------------------------
122 * Internal Memory Mapped Register
123 */
124 #define CONFIG_SYS_IMMR 0xFFF00000
125
126 /*-----------------------------------------------------------------------
127 * Definitions for initial stack pointer and data area (in DPRAM)
128 */
129 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
130 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
131 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
132 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
133 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
134
135 /*-----------------------------------------------------------------------
136 * Start addresses for the final memory configuration
137 * (Set up by the startup code)
138 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
139 */
140 #define CONFIG_SYS_SDRAM_BASE 0x00000000
141 #define CONFIG_SYS_FLASH_BASE 0x40000000
142 #if defined(DEBUG)
143 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
144 #else
145 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
146 #endif
147 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
148 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
149
150 /*
151 * For booting Linux, the board info and command line data
152 * have to be in the first 8 MB of memory, since this is
153 * the maximum mapped by the Linux kernel during initialization.
154 */
155 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
156
157 /*-----------------------------------------------------------------------
158 * FLASH organization
159 */
160 /* use CFI flash driver */
161 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
162 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
163 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
164 #define CONFIG_SYS_FLASH_EMPTY_INFO
165 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
166 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
167 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
168
169 #define CONFIG_ENV_IS_IN_FLASH 1
170 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
171 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
172
173 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
174
175 /*-----------------------------------------------------------------------
176 * Hardware Information Block
177 */
178 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
179 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
180 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
181
182 /*-----------------------------------------------------------------------
183 * Cache Configuration
184 */
185 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
186 #if defined(CONFIG_CMD_KGDB)
187 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
188 #endif
189
190 /*-----------------------------------------------------------------------
191 * SYPCR - System Protection Control 11-9
192 * SYPCR can only be written once after reset!
193 *-----------------------------------------------------------------------
194 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
195 */
196 #if defined(CONFIG_WATCHDOG)
197 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
198 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
199 #else
200 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
201 #endif
202
203 /*-----------------------------------------------------------------------
204 * SIUMCR - SIU Module Configuration 11-6
205 *-----------------------------------------------------------------------
206 * PCMCIA config., multi-function pin tri-state
207 */
208 #ifndef CONFIG_CAN_DRIVER
209 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
210 #else /* we must activate GPL5 in the SIUMCR for CAN */
211 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
212 #endif /* CONFIG_CAN_DRIVER */
213
214 /*-----------------------------------------------------------------------
215 * TBSCR - Time Base Status and Control 11-26
216 *-----------------------------------------------------------------------
217 * Clear Reference Interrupt Status, Timebase freezing enabled
218 */
219 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
220
221 /*-----------------------------------------------------------------------
222 * RTCSC - Real-Time Clock Status and Control Register 11-27
223 *-----------------------------------------------------------------------
224 */
225 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
226
227 /*-----------------------------------------------------------------------
228 * PISCR - Periodic Interrupt Status and Control 11-31
229 *-----------------------------------------------------------------------
230 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
231 */
232 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
233
234 /*-----------------------------------------------------------------------
235 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
236 *-----------------------------------------------------------------------
237 * Reset PLL lock status sticky bit, timer expired status bit and timer
238 * interrupt status bit
239 *
240 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
241 */
242 #ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
243 #define CONFIG_SYS_PLPRCR \
244 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
245 #else
246 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
247 #endif /* TQM8xxL_80MHz */
248
249 /*-----------------------------------------------------------------------
250 * SCCR - System Clock and reset Control Register 15-27
251 *-----------------------------------------------------------------------
252 * Set clock output, timebase and RTC source and divider,
253 * power management and some other internal clocks
254 */
255 #define SCCR_MASK SCCR_EBDF11
256 #ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
257 #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ \
258 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
259 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
260 SCCR_DFALCD00)
261 #else /* up to 50 MHz we use a 1:1 clock */
262 #define CONFIG_SYS_SCCR (SCCR_TBS | \
263 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
264 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
265 SCCR_DFALCD00)
266 #endif /* TQM8xxL_80MHz */
267
268 /*-----------------------------------------------------------------------
269 * PCMCIA stuff
270 *-----------------------------------------------------------------------
271 *
272 */
273 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
274 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
275 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
276 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
277 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
278 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
279 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
280 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
281
282 /*-----------------------------------------------------------------------
283 *
284 *-----------------------------------------------------------------------
285 *
286 */
287 #define CONFIG_SYS_DER 0
288
289 /*
290 * Init Memory Controller:
291 *
292 * BR0/1 and OR0/1 (FLASH)
293 */
294
295 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
296 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
297
298 /* used to re-map FLASH both when starting from SRAM or FLASH:
299 * restrict access enough to keep SRAM working (if any)
300 * but not too much to meddle with FLASH accesses
301 */
302 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
303 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
304
305 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
306 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
307 OR_SCY_5_CLK | OR_EHTR)
308
309 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
310 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
311 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
312
313 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
314 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
315 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
316
317 /*
318 * BR2/3 and OR2/3 (SDRAM)
319 *
320 */
321 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
322 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
323 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
324
325 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
326 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
327
328 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
329 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
330
331 #ifndef CONFIG_CAN_DRIVER
332 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
333 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
334 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
335 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
336 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
337 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
338 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
339 BR_PS_8 | BR_MS_UPMB | BR_V )
340 #endif /* CONFIG_CAN_DRIVER */
341
342 /*
343 * Memory Periodic Timer Prescaler
344 */
345
346 /* periodic timer for refresh */
347 #define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
348
349 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
350 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
351 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
352
353 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
354 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
355 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
356
357 /*
358 * MAMR settings for SDRAM
359 */
360
361 /* 8 column SDRAM */
362 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
363 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
364 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
365 /* 9 column SDRAM */
366 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
367 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
368 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
369
370
371 /*
372 * Internal Definitions
373 *
374 * Boot Flags
375 */
376 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
377 #define BOOTFLAG_WARM 0x02 /* Software reboot */
378
379 #endif /* __CONFIG_H */