include/configs/SXNI855T.h

   1 /*
   2  * U-Boot configuration for SIXNET SXNI855T CPU board.
   3  * This board is based (loosely) on the Motorola FADS board, so this
   4  * file is based (loosely) on config_FADS860T.h, see it for additional
   5  * credits.
   6  *
   7  * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  *
  27  */
  28
  29 /*
  30  * Memory map:
  31  *
  32  *   ff100000 -> ff13ffff : FPGA        CS1
  33  *   ff030000 -> ff03ffff : EXPANSION   CS7
  34  *   ff020000 -> ff02ffff : DATA FLASH  CS4
  35  *   ff018000 -> ff01ffff : UART B      CS6/UPMB
  36  *   ff010000 -> ff017fff : UART A      CS5/UPMB
  37  *   ff000000 -> ff00ffff : IMAP                   internal to the MPC855T
  38  *   f8000000 -> fbffffff : FLASH       CS0        up to 64MB
  39  *   f4000000 -> f7ffffff : NVSRAM      CS2        up to 64MB
  40  *   00000000 -> 0fffffff : SDRAM       CS3/UPMA   up to 256MB
  41  */
  42
  43 /* ------------------------------------------------------------------------- */
  44
  45 /*
  46  * board/config.h - configuration options, board specific
  47  */
  48
  49 #ifndef __CONFIG_H
  50 #define __CONFIG_H
  51
  52 /*
  53  * High Level Configuration Options
  54  * (easy to change)
  55  */
  56 #include <mpc8xx_irq.h>
  57
  58 #define CONFIG_SXNI855T         1       /* SIXNET IPm 855T CPU module */
  59
  60 /* The 855T is just a stripped 860T and needs code for 860, so for now
  61  * at least define 860, 860T and 855T
  62  */
  63 #define CONFIG_MPC860           1
  64 #define CONFIG_MPC860T          1
  65 #define CONFIG_MPC855T          1
  66
  67 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  68 #undef  CONFIG_8xx_CONS_SMC2
  69 #undef  CONFIG_8xx_CONS_SCC1
  70 #undef  CONFIG_8xx_CONS_NONE
  71 #define CONFIG_BAUDRATE         9600
  72 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  73
  74 #define MPC8XX_FACT             10      /* 50 MHz is 5 MHz in times 10  */
  75
  76 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  77
  78 #if 0
  79 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  80 #else
  81 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  82 #endif
  83
  84 #define CONFIG_HAS_ETH1
  85
  86 /*-----------------------------------------------------------------------
  87  * Definitions for status LED
  88  */
  89 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  90
  91 # define STATUS_LED_PAR         im_ioport.iop_papar
  92 # define STATUS_LED_DIR         im_ioport.iop_padir
  93 # define STATUS_LED_ODR         im_ioport.iop_paodr
  94 # define STATUS_LED_DAT         im_ioport.iop_padat
  95
  96 # define STATUS_LED_BIT         0x8000          /* LED 0 is on PA.0 */
  97 # define STATUS_LED_PERIOD      ((CONFIG_SYS_HZ / 2) / 5)       /* blink at 5 Hz */
  98 # define STATUS_LED_STATE       STATUS_LED_BLINKING
  99
 100 # define STATUS_LED_ACTIVE      0               /* LED on for bit == 0  */
 101
 102 # define STATUS_LED_BOOT        0               /* LED 0 used for boot status */
 103
 104 #ifdef DEV      /* development (debug) settings */
 105 #define CONFIG_BOOT_LED_STATE   STATUS_LED_OFF
 106 #else           /* production settings */
 107 #define CONFIG_BOOT_LED_STATE   STATUS_LED_ON
 108 #endif
 109
 110 #define CONFIG_SHOW_BOOT_PROGRESS 1
 111
 112 #define CONFIG_BOOTCOMMAND      "bootm f8040000 f8100000" /* autoboot command */
 113 #define CONFIG_BOOTARGS         "root=/dev/ram ip=off"
 114
 115 #define CONFIG_MISC_INIT_R              /* have misc_init_r() function */
 116 #define CONFIG_BOARD_POSTCLK_INIT       /* have board_postclk_init() function */
 117
 118 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 119
 120 #define CONFIG_RTC_DS1306               /* Dallas 1306 real time clock  */
 121
 122 #define CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 123 /*
 124  * Software (bit-bang) I2C driver configuration
 125  */
 126 #define PB_SCL          0x00000020      /* PB 26 */
 127 #define PB_SDA          0x00000010      /* PB 27 */
 128
 129 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 130 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 131 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 132 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 133 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 134                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 135 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 136                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 137 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 138
 139 # define CONFIG_SYS_I2C_SPEED           50000
 140 # define CONFIG_SYS_I2C_SLAVE           0xFE
 141 # define CONFIG_SYS_I2C_EEPROM_ADDR     0x50    /* Atmel 24C64                  */
 142 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2       /* two byte address             */
 143
 144 #define CONFIG_FEC_ENET         1       /* use FEC ethernet  */
 145 #define CONFIG_MII              1
 146
 147 #define CONFIG_SYS_DISCOVER_PHY
 148
 149
 150 /*
 151  * BOOTP options
 152  */
 153 #define CONFIG_BOOTP_BOOTFILESIZE
 154 #define CONFIG_BOOTP_BOOTPATH
 155 #define CONFIG_BOOTP_GATEWAY
 156 #define CONFIG_BOOTP_HOSTNAME
 157
 158
 159 /*
 160  * Command line configuration.
 161  */
 162 #include <config_cmd_default.h>
 163
 164 #define CONFIG_CMD_EEPROM
 165 #define CONFIG_CMD_JFFS2
 166 #define CONFIG_CMD_NAND
 167 #define CONFIG_CMD_DATE
 168
 169
 170 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 171
 172 /*
 173  * JFFS2 partitions
 174  *
 175  */
 176 /* No command line, one static partition */
 177 #undef CONFIG_JFFS2_CMDLINE
 178
 179 /*
 180 #define CONFIG_JFFS2_DEV                "nor0"
 181 #define CONFIG_JFFS2_PART_SIZE          0x00780000
 182 #define CONFIG_JFFS2_PART_OFFSET        0x00080000
 183 */
 184
 185 #define CONFIG_JFFS2_DEV                "nand0"
 186 #define CONFIG_JFFS2_PART_SIZE          0x00200000
 187 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 188
 189 /* mtdparts command line support */
 190 /* Note: fake mtd_id used, no linux mtd map file */
 191 /*
 192 #define CONFIG_JFFS2_CMDLINE
 193 #define MTDIDS_DEFAULT          "nor0=sixnet-0,nand0=sixnet-nand"
 194 #define MTDPARTS_DEFAULT        "mtdparts=sixnet-0:7680k@512k();sixnet-nand:2m(jffs2-nand)"
 195 */
 196
 197 /* NAND flash support */
 198 #define CONFIG_NAND_LEGACY
 199 #define CONFIG_MTD_NAND_ECC_JFFS2
 200 #define CONFIG_SYS_MAX_NAND_DEVICE      1       /* Max number of NAND devices   */
 201 #define SECTORSIZE 512
 202
 203 #define ADDR_COLUMN 1
 204 #define ADDR_PAGE 2
 205 #define ADDR_COLUMN_PAGE 3
 206
 207 #define NAND_ChipID_UNKNOWN     0x00
 208 #define NAND_MAX_FLOORS 1
 209 #define NAND_MAX_CHIPS 1
 210
 211 /* DFBUSY is available on Port C, bit 12; 0 if busy */
 212 #define NAND_WAIT_READY(nand)   \
 213         while (!(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & 0x0008));
 214 #define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr))
 215 #define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr))
 216 #define WRITE_NAND(d, adr)      \
 217          do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0)
 218 #define READ_NAND(adr) (*(volatile uint8_t *)(adr))
 219 #define CLE_LO  0x01    /* 0 selects CLE mode (CLE high) */
 220 #define ALE_LO  0x02    /* 0 selects ALE mode (ALE high) */
 221 #define CE_LO   0x04    /* 1 selects chip (CE low) */
 222 #define nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0)
 223 #define NAND_DISABLE_CE(nand) \
 224         nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO)
 225 #define NAND_ENABLE_CE(nand) \
 226         nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO)
 227 #define NAND_CTL_CLRALE(nandptr) \
 228         nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
 229 #define NAND_CTL_SETALE(nandptr) \
 230         nand_setcr((nandptr) + 1, CE_LO | CLE_LO)
 231 #define NAND_CTL_CLRCLE(nandptr) \
 232         nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
 233 #define NAND_CTL_SETCLE(nandptr) \
 234         nand_setcr((nandptr) + 1, CE_LO | ALE_LO)
 235
 236 /*
 237  * Miscellaneous configurable options
 238  */
 239 #define CONFIG_SYS_LONGHELP                     /* undef to save a little memory */
 240 #define CONFIG_SYS_PROMPT               "=>"    /* Monitor Command Prompt       */
 241 #if defined(CONFIG_CMD_KGDB)
 242 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 243 #else
 244 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 245 #endif
 246 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 247 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 248 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 249
 250 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 251 #define CONFIG_SYS_MEMTEST_END          0x0400000       /* 1 ... 4 MB in DRAM   */
 252
 253 #define CONFIG_SYS_LOAD_ADDR            0x00100000
 254
 255 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 256
 257 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 258
 259 /*
 260  * Low Level Configuration Settings
 261  * (address mappings, register initial values, etc.)
 262  * You should know what you are doing if you make changes here.
 263  */
 264 /*-----------------------------------------------------------------------
 265  * Internal Memory Mapped Register
 266  */
 267 #define CONFIG_SYS_IMMR         0xFF000000
 268 #define CONFIG_SYS_IMMR_SIZE            ((uint)(64 * 1024))
 269
 270 /*-----------------------------------------------------------------------
 271  * Definitions for initial stack pointer and data area (in DPRAM)
 272  */
 273 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 274 #define CONFIG_SYS_INIT_RAM_END 0x2F00  /* End of used area in DPRAM    */
 275 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 276 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 277 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 278
 279 /*-----------------------------------------------------------------------
 280  * Start addresses for the final memory configuration
 281  * (Set up by the startup code)
 282  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 283  */
 284 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 285 #define CONFIG_SYS_SRAM_BASE            0xF4000000
 286 #define CONFIG_SYS_SRAM_SIZE            0x04000000      /* autosize up to 64Mbyte */
 287
 288 #define CONFIG_SYS_FLASH_BASE           0xF8000000
 289 #define CONFIG_SYS_FLASH_SIZE           ((uint)(8 * 1024 * 1024))       /* max 8Mbyte */
 290
 291 #define CONFIG_SYS_DFLASH_BASE          0xff020000 /* DiskOnChip or NAND FLASH */
 292 #define CONFIG_SYS_DFLASH_SIZE          0x00010000
 293
 294 #define CONFIG_SYS_FPGA_BASE            0xFF100000      /* Xilinx FPGA */
 295 #define CONFIG_SYS_FPGA_PROG            0xFF130000      /* Programming address */
 296 #define CONFIG_SYS_FPGA_SIZE            0x00040000      /* 256KiB usable */
 297
 298 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 299 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 300 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 301
 302 /*
 303  * For booting Linux, the board info and command line data
 304  * have to be in the first 8 MB of memory, since this is
 305  * the maximum mapped by the Linux kernel during initialization.
 306  */
 307 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 308 /*-----------------------------------------------------------------------
 309  * FLASH organization
 310  */
 311 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 312 /* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
 313  * AMD 29LV641 has 128 64K sectors in 8MB
 314  */
 315 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* max number of sectors on one chip    */
 316
 317 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 318 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 319
 320 /*-----------------------------------------------------------------------
 321  * Cache Configuration
 322  */
 323 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 324 #if defined(CONFIG_CMD_KGDB)
 325 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 326 #endif
 327
 328 /*-----------------------------------------------------------------------
 329  * SYPCR - System Protection Control                                    11-9
 330  * SYPCR can only be written once after reset!
 331  *-----------------------------------------------------------------------
 332  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 333  */
 334 #if defined(CONFIG_WATCHDOG)
 335 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 336                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 337 #else
 338 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 339 #endif
 340
 341 /*-----------------------------------------------------------------------
 342  * SIUMCR - SIU Module Configuration                                    11-6
 343  *-----------------------------------------------------------------------
 344  * PCMCIA config., multi-function pin tri-state
 345  */
 346 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 347
 348 /*-----------------------------------------------------------------------
 349  * TBSCR - Time Base Status and Control                                 11-26
 350  *-----------------------------------------------------------------------
 351  * Clear Reference Interrupt Status, Timebase freezing enabled
 352  */
 353 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 354
 355 /*-----------------------------------------------------------------------
 356  * PISCR - Periodic Interrupt Status and Control                11-31
 357  *-----------------------------------------------------------------------
 358  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 359  */
 360 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 361
 362 /*-----------------------------------------------------------------------
 363  * PLPRCR - PLL, Low-Power, and Reset Control Register  15-30
 364  *-----------------------------------------------------------------------
 365  * set the PLL, the low-power modes and the reset control (15-29)
 366  */
 367 #define CONFIG_SYS_PLPRCR       (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
 368                                 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 369
 370 /*-----------------------------------------------------------------------
 371  * SCCR - System Clock and reset Control Register               15-27
 372  *-----------------------------------------------------------------------
 373  * Set clock output, timebase and RTC source and divider,
 374  * power management and some other internal clocks
 375  */
 376 #define SCCR_MASK       SCCR_EBDF11
 377 #define CONFIG_SYS_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
 378
 379  /*-----------------------------------------------------------------------
 380  *
 381  *-----------------------------------------------------------------------
 382  *
 383  */
 384 #define CONFIG_SYS_DER          0
 385
 386 /* Because of the way the 860 starts up and assigns CS0 the
 387  * entire address space, we have to set the memory controller
 388  * differently.  Normally, you write the option register
 389  * first, and then enable the chip select by writing the
 390  * base register.  For CS0, you must write the base register
 391  * first, followed by the option register.
 392  */
 393
 394 /*
 395  * Init Memory Controller:
 396  *
 397  **********************************************************
 398  * BR0 and OR0 (FLASH)
 399  */
 400
 401 #define CONFIG_SYS_PRELIM_OR0_AM        0xFC000000      /* OR addr mask */
 402
 403 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0        */
 404 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 405
 406 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR0_AM | CONFIG_SYS_OR_TIMING_FLASH)
 407
 408 #define CONFIG_FLASH_16BIT
 409 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
 410 #define CONFIG_SYS_FLASH_PROTECTION     /* need to lock/unlock sectors in hardware */
 411
 412 /**********************************************************
 413  * BR1 and OR1 (FPGA)
 414  * These preliminary values are also the final values.
 415  */
 416 #define CONFIG_SYS_OR_TIMING_FPGA \
 417         (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX)
 418 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 419 #define CONFIG_SYS_OR1_PRELIM   (((-CONFIG_SYS_FPGA_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_FPGA)
 420
 421 /**********************************************************
 422  * BR4 and OR4 (data flash)
 423  * These preliminary values are also the final values.
 424  */
 425 #define CONFIG_SYS_OR_TIMING_DFLASH \
 426         (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX)
 427 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 428 #define CONFIG_SYS_OR4_PRELIM   (((-CONFIG_SYS_DFLASH_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_DFLASH)
 429
 430 /**********************************************************
 431  * BR5/6 and OR5/6 (Dual UART)
 432  */
 433 #define CONFIG_SYS_DUART_SIZE   0x8000  /* 32K window, only uses 8 bytes */
 434 #define CONFIG_SYS_DUARTA_BASE  0xff010000
 435 #define CONFIG_SYS_DUARTB_BASE  0xff018000
 436
 437 #define DUART_MBMR      0
 438 #define DUART_OR_VALUE (ORMASK(CONFIG_SYS_DUART_SIZE) | OR_G5LS| OR_BI)
 439 #define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)
 440 #define DUART_BR5_VALUE ((CONFIG_SYS_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
 441 #define DUART_BR6_VALUE ((CONFIG_SYS_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
 442
 443 /**********************************************************
 444  *
 445  * Boot Flags
 446  */
 447 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 448 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 449
 450 #define CONFIG_RESET_ON_PANIC           /* reset if system panic() */
 451
 452 #define CONFIG_ENV_IS_IN_FLASH
 453 #ifdef CONFIG_ENV_IS_IN_FLASH
 454   /* environment is in FLASH */
 455   #define CONFIG_ENV_ADDR               0xF8040000      /* AM29LV641 or AM29LV800BT */
 456   #define CONFIG_ENV_ADDR_REDUND        0xF8050000      /* AM29LV641 or AM29LV800BT */
 457   #define CONFIG_ENV_SECT_SIZE  0x00010000
 458   #define CONFIG_ENV_SIZE               0x00002000
 459 #else
 460   /* environment is in EEPROM */
 461   #define CONFIG_ENV_IS_IN_EEPROM               1
 462   #define CONFIG_ENV_OFFSET             0       /* at beginning of EEPROM */
 463   #define CONFIG_ENV_SIZE                    1024       /* Use only a part of it*/
 464 #endif
 465
 466 #if 1
 467 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot */
 468 #define CONFIG_AUTOBOOT_PROMPT          "autoboot in %d seconds\n", bootdelay
 469 #define CONFIG_AUTOBOOT_DELAY_STR       "delayabit"
 470 #define CONFIG_AUTOBOOT_STOP_STR        " " /* easy to stop for now */
 471 #endif
 472
 473 #endif  /* __CONFIG_H */